target/linux/ramips/patches-4.14/102-mt7621-fix-cpu-clk-add-clkdev.patch

   1 --- a/arch/mips/include/asm/mach-ralink/mt7621.h
   2 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
   3 @@ -19,6 +19,10 @@
   4  #define SYSC_REG_CHIP_REV              0x0c
   5  #define SYSC_REG_SYSTEM_CONFIG0                0x10
   6  #define SYSC_REG_SYSTEM_CONFIG1                0x14
   7 +#define SYSC_REG_CLKCFG0               0x2c
   8 +#define SYSC_REG_CUR_CLK_STS           0x44
   9 +
  10 +#define MEMC_REG_CPU_PLL               0x648
  11
  12  #define CHIP_REV_PKG_MASK              0x1
  13  #define CHIP_REV_PKG_SHIFT             16
  14 @@ -26,6 +30,22 @@
  15  #define CHIP_REV_VER_SHIFT             8
  16  #define CHIP_REV_ECO_MASK              0xf
  17
  18 +#define XTAL_MODE_SEL_MASK             0x7
  19 +#define XTAL_MODE_SEL_SHIFT            6
  20 +
  21 +#define CPU_CLK_SEL_MASK               0x3
  22 +#define CPU_CLK_SEL_SHIFT              30
  23 +
  24 +#define CUR_CPU_FDIV_MASK              0x1f
  25 +#define CUR_CPU_FDIV_SHIFT             8
  26 +#define CUR_CPU_FFRAC_MASK             0x1f
  27 +#define CUR_CPU_FFRAC_SHIFT            0
  28 +
  29 +#define CPU_PLL_PREDIV_MASK            0x3
  30 +#define CPU_PLL_PREDIV_SHIFT           12
  31 +#define CPU_PLL_FBDIV_MASK             0x7f
  32 +#define CPU_PLL_FBDIV_SHIFT            4
  33 +
  34  #define MT7621_DRAM_BASE                0x0
  35  #define MT7621_DDR2_SIZE_MIN           32
  36  #define MT7621_DDR2_SIZE_MAX           256
  37 --- a/arch/mips/ralink/mt7621.c
  38 +++ b/arch/mips/ralink/mt7621.c
  39 @@ -10,6 +10,10 @@
  40  #include <linux/kernel.h>
  41  #include <linux/init.h>
  42  #include <linux/jiffies.h>
  43 +#include <linux/clk.h>
  44 +#include <linux/clkdev.h>
  45 +#include <linux/clk-provider.h>
  46 +#include <dt-bindings/clock/mt7621-clk.h>
  47
  48  #include <asm/mipsregs.h>
  49  #include <asm/smp-ops.h>
  50 @@ -18,16 +22,12 @@
  51  #include <asm/mach-ralink/mt7621.h>
  52  #include <asm/mips-boards/launch.h>
  53  #include <asm/delay.h>
  54 +#include <asm/time.h>
  55
  56  #include <pinmux.h>
  57
  58  #include "common.h"
  59
  60 -#define SYSC_REG_SYSCFG                0x10
  61 -#define SYSC_REG_CPLL_CLKCFG0  0x2c
  62 -#define SYSC_REG_CUR_CLK_STS   0x44
  63 -#define CPU_CLK_SEL            (BIT(30) | BIT(31))
  64 -
  65  #define MT7621_GPIO_MODE_UART1         1
  66  #define MT7621_GPIO_MODE_I2C           2
  67  #define MT7621_GPIO_MODE_UART3_MASK    0x3
  68 @@ -113,49 +113,89 @@ static struct rt2880_pmx_group mt7621_pi
  69         { 0 }
  70  };
  71
  72 +static struct clk *clks[MT7621_CLK_MAX];
  73 +static struct clk_onecell_data clk_data = {
  74 +       .clks = clks,
  75 +       .clk_num = ARRAY_SIZE(clks),
  76 +};
  77 +
  78  phys_addr_t mips_cpc_default_phys_base(void)
  79  {
  80         panic("Cannot detect cpc address");
  81  }
  82
  83 -void __init ralink_clk_init(void)
  84 +static struct clk *__init mt7621_add_sys_clkdev(
  85 +       const char *id, unsigned long rate)
  86  {
  87 -       int cpu_fdiv = 0;
  88 -       int cpu_ffrac = 0;
  89 -       int fbdiv = 0;
  90 -       u32 clk_sts, syscfg;
  91 -       u8 clk_sel = 0, xtal_mode;
  92 -       u32 cpu_clk;
  93 +       struct clk *clk;
  94 +       int err;
  95 +
  96 +       clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
  97 +       if (IS_ERR(clk))
  98 +               panic("failed to allocate %s clock structure", id);
  99 +
 100 +       err = clk_register_clkdev(clk, id, NULL);
 101 +       if (err)
 102 +               panic("unable to register %s clock device", id);
 103
 104 -       if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
 105 -               clk_sel = 1;
 106 +       return clk;
 107 +}
 108 +
 109 +void __init ralink_clk_init(void)
 110 +{
 111 +       u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
 112 +       u32 pll, prediv, fbdiv;
 113 +       u32 xtal_clk, cpu_clk, bus_clk;
 114 +       const static u32 prediv_tbl[] = {0, 1, 2, 2};
 115 +
 116 +       syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
 117 +       xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
 118 +
 119 +       clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0);
 120 +       clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK;
 121 +
 122 +       curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
 123 +       ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK;
 124 +       ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK;
 125 +
 126 +       if (xtal_sel <= 2)
 127 +               xtal_clk = 20 * 1000 * 1000;
 128 +       else if (xtal_sel <= 5)
 129 +               xtal_clk = 40 * 1000 * 1000;
 130 +       else
 131 +               xtal_clk = 25 * 1000 * 1000;
 132
 133         switch (clk_sel) {
 134         case 0:
 135 -               clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
 136 -               cpu_fdiv = ((clk_sts >> 8) & 0x1F);
 137 -               cpu_ffrac = (clk_sts & 0x1F);
 138 -               cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
 139 +               cpu_clk = 500 * 1000 * 1000;
 140                 break;
 141 -
 142         case 1:
 143 -               fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
 144 -               syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
 145 -               xtal_mode = (syscfg >> 6) & 0x7;
 146 -               if (xtal_mode >= 6) {
 147 -                       /* 25Mhz Xtal */
 148 -                       cpu_clk = 25 * fbdiv * 1000 * 1000;
 149 -               } else if (xtal_mode >= 3) {
 150 -                       /* 40Mhz Xtal */
 151 -                       cpu_clk = 40 * fbdiv * 1000 * 1000;
 152 -               } else {
 153 -                       /* 20Mhz Xtal */
 154 -                       cpu_clk = 20 * fbdiv * 1000 * 1000;
 155 -               }
 156 +               pll = rt_memc_r32(MEMC_REG_CPU_PLL);
 157 +               fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
 158 +               prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
 159 +               cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
 160                 break;
 161 +       default:
 162 +               cpu_clk = xtal_clk;
 163         }
 164 +
 165 +       cpu_clk = cpu_clk / ffiv * ffrac;
 166 +       bus_clk = cpu_clk / 4;
 167 +
 168 +       clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk);
 169 +       clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk);
 170 +
 171 +       pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000);
 172 +       mips_hpt_frequency = cpu_clk / 2;
 173  }
 174
 175 +static void __init mt7621_clocks_init_dt(struct device_node *np)
 176 +{
 177 +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 178 +}
 179 +
 180 +CLK_OF_DECLARE(ar7100, "mediatek,mt7621-pll", mt7621_clocks_init_dt);
 181 +
 182  void __init ralink_of_remap(void)
 183  {
 184         rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
 185 --- a/arch/mips/ralink/timer-gic.c
 186 +++ b/arch/mips/ralink/timer-gic.c
 187 @@ -11,14 +11,14 @@
 188
 189  #include <linux/of.h>
 190  #include <linux/clk-provider.h>
 191 -#include <linux/clocksource.h>
 192 +#include <asm/time.h>
 193
 194  #include "common.h"
 195
 196  void __init plat_time_init(void)
 197  {
 198         ralink_of_remap();
 199 -
 200 +       ralink_clk_init();
 201         of_clk_init(NULL);
 202         timer_probe();
 203  }
 204 --- /dev/null
 205 +++ b/include/dt-bindings/clock/mt7621-clk.h
 206 @@ -0,0 +1,18 @@
 207 +/*
 208 + * Copyright (C) 2018 Weijie Gao <hackpascal@gmail.com>
 209 + *
 210 + * This program is free software; you can redistribute it and/or modify
 211 + * it under the terms of the GNU General Public License version 2 as
 212 + * published by the Free Software Foundation.
 213 + *
 214 + */
 215 +
 216 +#ifndef __DT_BINDINGS_MT7621_CLK_H
 217 +#define __DT_BINDINGS_MT7621_CLK_H
 218 +
 219 +#define MT7621_CLK_CPU         0
 220 +#define MT7621_CLK_BUS         1
 221 +
 222 +#define MT7621_CLK_MAX         2
 223 +
 224 +#endif /* __DT_BINDINGS_MT7621_CLK_H */