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ramips: backport series of patches that ensure GCRs of other CPUs are accessed properly
[openwrt/openwrt.git] / target / linux / ramips / patches-4.3 / 0038-mtd-ralink-add-mt7620-nand-driver.patch
1 From fb6e1578cd73d7d81f675e75247a676423f32412 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 17 Nov 2013 17:41:46 +0100
4 Subject: [PATCH 38/53] mtd: ralink: add mt7620 nand driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mtd/maps/Kconfig | 4 +
9 drivers/mtd/maps/Makefile | 2 +
10 drivers/mtd/maps/ralink_nand.c | 2136 ++++++++++++++++++++++++++++++++++++++++
11 drivers/mtd/maps/ralink_nand.h | 232 +++++
12 4 files changed, 2374 insertions(+)
13 create mode 100644 drivers/mtd/maps/ralink_nand.c
14 create mode 100644 drivers/mtd/maps/ralink_nand.h
15
16 diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
17 index 7c95a65..c2739db 100644
18 --- a/drivers/mtd/maps/Kconfig
19 +++ b/drivers/mtd/maps/Kconfig
20 @@ -399,4 +399,8 @@ config MTD_LATCH_ADDR
21
22 If compiled as a module, it will be called latch-addr-flash.
23
24 +config MTD_NAND_MT7620
25 + tristate "Support for NAND on Mediatek MT7620"
26 + depends on RALINK && SOC_MT7620
27 +
28 endmenu
29 diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
30 index 141c91a..94d2aa0 100644
31 --- a/drivers/mtd/maps/Makefile
32 +++ b/drivers/mtd/maps/Makefile
33 @@ -43,3 +43,5 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o
34 obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
35 obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o
36 obj-$(CONFIG_MTD_LANTIQ) += lantiq-flash.o
37 +obj-$(CONFIG_MTD_NAND_MT7620) += ralink_nand.o
38 +
39 diff --git a/drivers/mtd/maps/ralink_nand.c b/drivers/mtd/maps/ralink_nand.c
40 new file mode 100644
41 index 0000000..64f9119
42 --- /dev/null
43 +++ b/drivers/mtd/maps/ralink_nand.c
44 @@ -0,0 +1,2136 @@
45 +#define DEBUG
46 +#include <linux/device.h>
47 +#undef DEBUG
48 +#include <linux/slab.h>
49 +#include <linux/mtd/mtd.h>
50 +#include <linux/delay.h>
51 +#include <linux/module.h>
52 +#include <linux/interrupt.h>
53 +#include <linux/dma-mapping.h>
54 +#include <linux/mtd/partitions.h>
55 +#include <asm/io.h>
56 +#include <linux/delay.h>
57 +#include <linux/sched.h>
58 +#include <linux/of.h>
59 +#include <linux/platform_device.h>
60 +
61 +#include "ralink_nand.h"
62 +#ifdef RANDOM_GEN_BAD_BLOCK
63 +#include <linux/random.h>
64 +#endif
65 +
66 +#define LARGE_MTD_BOOT_PART_SIZE (CFG_BLOCKSIZE<<2)
67 +#define LARGE_MTD_CONFIG_PART_SIZE (CFG_BLOCKSIZE<<2)
68 +#define LARGE_MTD_FACTORY_PART_SIZE (CFG_BLOCKSIZE<<1)
69 +
70 +
71 +#define BLOCK_ALIGNED(a) ((a) & (CFG_BLOCKSIZE - 1))
72 +
73 +#define READ_STATUS_RETRY 1000
74 +
75 +struct mtd_info *ranfc_mtd = NULL;
76 +
77 +int skipbbt = 0;
78 +int ranfc_debug = 1;
79 +static int ranfc_bbt = 1;
80 +#if defined (WORKAROUND_RX_BUF_OV)
81 +static int ranfc_verify = 1;
82 +#endif
83 +static u32 nand_addrlen;
84 +
85 +#if 0
86 +module_param(ranfc_debug, int, 0644);
87 +module_param(ranfc_bbt, int, 0644);
88 +module_param(ranfc_verify, int, 0644);
89 +#endif
90 +
91 +#if 0
92 +#define ra_dbg(args...) do { if (ranfc_debug) printk(args); } while(0)
93 +#else
94 +#define ra_dbg(args...)
95 +#endif
96 +
97 +#define CLEAR_INT_STATUS() ra_outl(NFC_INT_ST, ra_inl(NFC_INT_ST))
98 +#define NFC_TRANS_DONE() (ra_inl(NFC_INT_ST) & INT_ST_ND_DONE)
99 +
100 +int is_nand_page_2048 = 0;
101 +const unsigned int nand_size_map[2][3] = {{25, 30, 30}, {20, 27, 30}};
102 +
103 +static int nfc_wait_ready(int snooze_ms);
104 +
105 +static const char * const mtk_probe_types[] = { "cmdlinepart", "ofpart", NULL };
106 +
107 +/**
108 + * reset nand chip
109 + */
110 +static int nfc_chip_reset(void)
111 +{
112 + int status;
113 +
114 + //ra_dbg("%s:\n", __func__);
115 +
116 + // reset nand flash
117 + ra_outl(NFC_CMD1, 0x0);
118 + ra_outl(NFC_CMD2, 0xff);
119 + ra_outl(NFC_ADDR, 0x0);
120 + ra_outl(NFC_CONF, 0x0411);
121 +
122 + status = nfc_wait_ready(5); //erase wait 5us
123 + if (status & NAND_STATUS_FAIL) {
124 + printk("%s: fail \n", __func__);
125 + }
126 +
127 + return (int)(status & NAND_STATUS_FAIL);
128 +
129 +}
130 +
131 +
132 +
133 +/**
134 + * clear NFC and flash chip.
135 + */
136 +static int nfc_all_reset(void)
137 +{
138 + int retry;
139 +
140 + ra_dbg("%s: \n", __func__);
141 +
142 + // reset controller
143 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
144 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
145 +
146 + CLEAR_INT_STATUS();
147 +
148 + retry = READ_STATUS_RETRY;
149 + while ((ra_inl(NFC_INT_ST) & 0x02) != 0x02 && retry--);
150 + if (retry <= 0) {
151 + printk("nfc_all_reset: clean buffer fail \n");
152 + return -1;
153 + }
154 +
155 + retry = READ_STATUS_RETRY;
156 + while ((ra_inl(NFC_STATUS) & 0x1) != 0x0 && retry--) { //fixme, controller is busy ?
157 + udelay(1);
158 + }
159 +
160 + nfc_chip_reset();
161 +
162 + return 0;
163 +}
164 +
165 +/** NOTICE: only called by nfc_wait_ready().
166 + * @return -1, nfc can not get transction done
167 + * @return 0, ok.
168 + */
169 +static int _nfc_read_status(char *status)
170 +{
171 + unsigned long cmd1, conf;
172 + int int_st, nfc_st;
173 + int retry;
174 +
175 + cmd1 = 0x70;
176 + conf = 0x000101 | (1 << 20);
177 +
178 + //fixme, should we check nfc status?
179 + CLEAR_INT_STATUS();
180 +
181 + ra_outl(NFC_CMD1, cmd1);
182 + ra_outl(NFC_CONF, conf);
183 +
184 + /* FIXME,
185 + * 1. since we have no wired ready signal, directly
186 + * calling this function is not gurantee to read right status under ready state.
187 + * 2. the other side, we can not determine how long to become ready, this timeout retry is nonsense.
188 + * 3. SUGGESTION: call nfc_read_status() from nfc_wait_ready(),
189 + * that is aware about caller (in sementics) and has snooze plused nfc ND_DONE.
190 + */
191 + retry = READ_STATUS_RETRY;
192 + do {
193 + nfc_st = ra_inl(NFC_STATUS);
194 + int_st = ra_inl(NFC_INT_ST);
195 +
196 + ndelay(10);
197 + } while (!(int_st & INT_ST_RX_BUF_RDY) && retry--);
198 +
199 + if (!(int_st & INT_ST_RX_BUF_RDY)) {
200 + printk("nfc_read_status: NFC fail, int_st(%x), retry:%x. nfc:%x, reset nfc and flash. \n",
201 + int_st, retry, nfc_st);
202 + nfc_all_reset();
203 + *status = NAND_STATUS_FAIL;
204 + return -1;
205 + }
206 +
207 + *status = (char)(le32_to_cpu(ra_inl(NFC_DATA)) & 0x0ff);
208 + return 0;
209 +}
210 +
211 +/**
212 + * @return !0, chip protect.
213 + * @return 0, chip not protected.
214 + */
215 +static int nfc_check_wp(void)
216 +{
217 + /* Check the WP bit */
218 +#if !defined CONFIG_NOT_SUPPORT_WP
219 + return !!(ra_inl(NFC_CTRL) & 0x01);
220 +#else
221 + char result = 0;
222 + int ret;
223 +
224 + ret = _nfc_read_status(&result);
225 + //FIXME, if ret < 0
226 +
227 + return !(result & NAND_STATUS_WP);
228 +#endif
229 +}
230 +
231 +#if !defined CONFIG_NOT_SUPPORT_RB
232 +/*
233 + * @return !0, chip ready.
234 + * @return 0, chip busy.
235 + */
236 +static int nfc_device_ready(void)
237 +{
238 + /* Check the ready */
239 + return !!(ra_inl(NFC_STATUS) & 0x04);
240 +}
241 +#endif
242 +
243 +
244 +/**
245 + * generic function to get data from flash.
246 + * @return data length reading from flash.
247 + */
248 +static int _ra_nand_pull_data(char *buf, int len, int use_gdma)
249 +{
250 +#ifdef RW_DATA_BY_BYTE
251 + char *p = buf;
252 +#else
253 + __u32 *p = (__u32 *)buf;
254 +#endif
255 + int retry, int_st;
256 + unsigned int ret_data;
257 + int ret_size;
258 +
259 + // receive data by use_gdma
260 + if (use_gdma) {
261 + //if (_ra_nand_dma_pull((unsigned long)p, len)) {
262 + if (1) {
263 + printk("%s: fail \n", __func__);
264 + len = -1; //return error
265 + }
266 +
267 + return len;
268 + }
269 +
270 + //fixme: retry count size?
271 + retry = READ_STATUS_RETRY;
272 + // no gdma
273 + while (len > 0) {
274 + int_st = ra_inl(NFC_INT_ST);
275 + if (int_st & INT_ST_RX_BUF_RDY) {
276 +
277 + ret_data = ra_inl(NFC_DATA);
278 + ra_outl(NFC_INT_ST, INT_ST_RX_BUF_RDY);
279 +#ifdef RW_DATA_BY_BYTE
280 + ret_size = sizeof(unsigned int);
281 + ret_size = min(ret_size, len);
282 + len -= ret_size;
283 + while (ret_size-- > 0) {
284 + //nfc is little endian
285 + *p++ = ret_data & 0x0ff;
286 + ret_data >>= 8;
287 + }
288 +#else
289 + ret_size = min(len, 4);
290 + len -= ret_size;
291 + if (ret_size == 4)
292 + *p++ = ret_data;
293 + else {
294 + __u8 *q = (__u8 *)p;
295 + while (ret_size-- > 0) {
296 + *q++ = ret_data & 0x0ff;
297 + ret_data >>= 8;
298 + }
299 + p = (__u32 *)q;
300 + }
301 +#endif
302 + retry = READ_STATUS_RETRY;
303 + }
304 + else if (int_st & INT_ST_ND_DONE) {
305 + break;
306 + }
307 + else {
308 + udelay(1);
309 + if (retry-- < 0)
310 + break;
311 + }
312 + }
313 +
314 +#ifdef RW_DATA_BY_BYTE
315 + return (int)(p - buf);
316 +#else
317 + return ((int)p - (int)buf);
318 +#endif
319 +}
320 +
321 +/**
322 + * generic function to put data into flash.
323 + * @return data length writing into flash.
324 + */
325 +static int _ra_nand_push_data(char *buf, int len, int use_gdma)
326 +{
327 +#ifdef RW_DATA_BY_BYTE
328 + char *p = buf;
329 +#else
330 + __u32 *p = (__u32 *)buf;
331 +#endif
332 + int retry, int_st;
333 + unsigned int tx_data = 0;
334 + int tx_size, iter = 0;
335 +
336 + // receive data by use_gdma
337 + if (use_gdma) {
338 + //if (_ra_nand_dma_push((unsigned long)p, len))
339 + if (1)
340 + len = 0;
341 + printk("%s: fail \n", __func__);
342 + return len;
343 + }
344 +
345 + // no gdma
346 + retry = READ_STATUS_RETRY;
347 + while (len > 0) {
348 + int_st = ra_inl(NFC_INT_ST);
349 + if (int_st & INT_ST_TX_BUF_RDY) {
350 +#ifdef RW_DATA_BY_BYTE
351 + tx_size = min(len, (int)sizeof(unsigned long));
352 + for (iter = 0; iter < tx_size; iter++) {
353 + tx_data |= (*p++ << (8*iter));
354 + }
355 +#else
356 + tx_size = min(len, 4);
357 + if (tx_size == 4)
358 + tx_data = (*p++);
359 + else {
360 + __u8 *q = (__u8 *)p;
361 + for (iter = 0; iter < tx_size; iter++)
362 + tx_data |= (*q++ << (8*iter));
363 + p = (__u32 *)q;
364 + }
365 +#endif
366 + ra_outl(NFC_INT_ST, INT_ST_TX_BUF_RDY);
367 + ra_outl(NFC_DATA, tx_data);
368 + len -= tx_size;
369 + retry = READ_STATUS_RETRY;
370 + }
371 + else if (int_st & INT_ST_ND_DONE) {
372 + break;
373 + }
374 + else {
375 + udelay(1);
376 + if (retry-- < 0) {
377 + ra_dbg("%s p:%p buf:%p \n", __func__, p, buf);
378 + break;
379 + }
380 + }
381 + }
382 +
383 +
384 +#ifdef RW_DATA_BY_BYTE
385 + return (int)(p - buf);
386 +#else
387 + return ((int)p - (int)buf);
388 +#endif
389 +
390 +}
391 +
392 +static int nfc_select_chip(struct ra_nand_chip *ra, int chipnr)
393 +{
394 +#if (CONFIG_NUMCHIPS == 1)
395 + if (!(chipnr < CONFIG_NUMCHIPS))
396 + return -1;
397 + return 0;
398 +#else
399 + BUG();
400 +#endif
401 +}
402 +
403 +/** @return -1: chip_select fail
404 + * 0 : both CE and WP==0 are OK
405 + * 1 : CE OK and WP==1
406 + */
407 +static int nfc_enable_chip(struct ra_nand_chip *ra, unsigned int offs, int read_only)
408 +{
409 + int chipnr = offs >> ra->chip_shift;
410 +
411 + ra_dbg("%s: offs:%x read_only:%x \n", __func__, offs, read_only);
412 +
413 + chipnr = nfc_select_chip(ra, chipnr);
414 + if (chipnr < 0) {
415 + printk("%s: chip select error, offs(%x)\n", __func__, offs);
416 + return -1;
417 + }
418 +
419 + if (!read_only)
420 + return nfc_check_wp();
421 +
422 + return 0;
423 +}
424 +
425 +/** wait nand chip becomeing ready and return queried status.
426 + * @param snooze: sleep time in ms unit before polling device ready.
427 + * @return status of nand chip
428 + * @return NAN_STATUS_FAIL if something unexpected.
429 + */
430 +static int nfc_wait_ready(int snooze_ms)
431 +{
432 + int retry;
433 + char status;
434 +
435 + // wait nfc idle,
436 + if (snooze_ms == 0)
437 + snooze_ms = 1;
438 + else
439 + schedule_timeout(snooze_ms * HZ / 1000);
440 +
441 + snooze_ms = retry = snooze_ms *1000000 / 100 ; // ndelay(100)
442 +
443 + while (!NFC_TRANS_DONE() && retry--) {
444 + if (!cond_resched())
445 + ndelay(100);
446 + }
447 +
448 + if (!NFC_TRANS_DONE()) {
449 + printk("nfc_wait_ready: no transaction done \n");
450 + return NAND_STATUS_FAIL;
451 + }
452 +
453 +#if !defined (CONFIG_NOT_SUPPORT_RB)
454 + //fixme
455 + while(!(status = nfc_device_ready()) && retry--) {
456 + ndelay(100);
457 + }
458 +
459 + if (status == 0) {
460 + printk("nfc_wait_ready: no device ready. \n");
461 + return NAND_STATUS_FAIL;
462 + }
463 +
464 + _nfc_read_status(&status);
465 + return status;
466 +#else
467 +
468 + while(retry--) {
469 + _nfc_read_status(&status);
470 + if (status & NAND_STATUS_READY)
471 + break;
472 + ndelay(100);
473 + }
474 + if (retry<0)
475 + printk("nfc_wait_ready 2: no device ready, status(%x). \n", status);
476 +
477 + return status;
478 +#endif
479 +}
480 +
481 +/**
482 + * return 0: erase OK
483 + * return -EIO: fail
484 + */
485 +int nfc_erase_block(struct ra_nand_chip *ra, int row_addr)
486 +{
487 + unsigned long cmd1, cmd2, bus_addr, conf;
488 + char status;
489 +
490 + cmd1 = 0x60;
491 + cmd2 = 0xd0;
492 + bus_addr = row_addr;
493 + conf = 0x00511 | ((CFG_ROW_ADDR_CYCLE)<<16);
494 +
495 + // set NFC
496 + ra_dbg("%s: cmd1: %lx, cmd2:%lx bus_addr: %lx, conf: %lx \n",
497 + __func__, cmd1, cmd2, bus_addr, conf);
498 +
499 + //fixme, should we check nfc status?
500 + CLEAR_INT_STATUS();
501 +
502 + ra_outl(NFC_CMD1, cmd1);
503 + ra_outl(NFC_CMD2, cmd2);
504 + ra_outl(NFC_ADDR, bus_addr);
505 + ra_outl(NFC_CONF, conf);
506 +
507 + status = nfc_wait_ready(3); //erase wait 3ms
508 + if (status & NAND_STATUS_FAIL) {
509 + printk("%s: fail \n", __func__);
510 + return -EIO;
511 + }
512 +
513 + return 0;
514 +
515 +}
516 +
517 +static inline int _nfc_read_raw_data(int cmd1, int cmd2, int bus_addr, int bus_addr2, int conf, char *buf, int len, int flags)
518 +{
519 + int ret;
520 +
521 + CLEAR_INT_STATUS();
522 + ra_outl(NFC_CMD1, cmd1);
523 + ra_outl(NFC_CMD2, cmd2);
524 + ra_outl(NFC_ADDR, bus_addr);
525 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
526 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
527 + ra_outl(NFC_ADDR2, bus_addr2);
528 +#endif
529 + ra_outl(NFC_CONF, conf);
530 +
531 + ret = _ra_nand_pull_data(buf, len, 0);
532 + if (ret != len) {
533 + ra_dbg("%s: ret:%x (%x) \n", __func__, ret, len);
534 + return NAND_STATUS_FAIL;
535 + }
536 +
537 + //FIXME, this section is not necessary
538 + ret = nfc_wait_ready(0); //wait ready
539 + /* to prevent the DATA FIFO 's old data from next operation */
540 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
541 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
542 +
543 + if (ret & NAND_STATUS_FAIL) {
544 + printk("%s: fail \n", __func__);
545 + return NAND_STATUS_FAIL;
546 + }
547 +
548 + return 0;
549 +}
550 +
551 +static inline int _nfc_write_raw_data(int cmd1, int cmd3, int bus_addr, int bus_addr2, int conf, char *buf, int len, int flags)
552 +{
553 + int ret;
554 +
555 + CLEAR_INT_STATUS();
556 + ra_outl(NFC_CMD1, cmd1);
557 + ra_outl(NFC_CMD3, cmd3);
558 + ra_outl(NFC_ADDR, bus_addr);
559 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
560 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
561 + ra_outl(NFC_ADDR2, bus_addr2);
562 +#endif
563 + ra_outl(NFC_CONF, conf);
564 +
565 + ret = _ra_nand_push_data(buf, len, 0);
566 + if (ret != len) {
567 + ra_dbg("%s: ret:%x (%x) \n", __func__, ret, len);
568 + return NAND_STATUS_FAIL;
569 + }
570 +
571 + ret = nfc_wait_ready(1); //write wait 1ms
572 + /* to prevent the DATA FIFO 's old data from next operation */
573 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
574 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
575 +
576 + if (ret & NAND_STATUS_FAIL) {
577 + printk("%s: fail \n", __func__);
578 + return NAND_STATUS_FAIL;
579 + }
580 +
581 + return 0;
582 +}
583 +
584 +/**
585 + * @return !0: fail
586 + * @return 0: OK
587 + */
588 +int nfc_read_oob(struct ra_nand_chip *ra, int page, unsigned int offs, char *buf, int len, int flags)
589 +{
590 + unsigned int cmd1 = 0, cmd2 = 0, conf = 0;
591 + unsigned int bus_addr = 0, bus_addr2 = 0;
592 + unsigned int ecc_en;
593 + int use_gdma;
594 + int status;
595 +
596 + int pages_perblock = 1<<(ra->erase_shift - ra->page_shift);
597 + // constrain of nfc read function
598 +
599 +#if defined (WORKAROUND_RX_BUF_OV)
600 + BUG_ON (len > 60); //problem of rx-buffer overrun
601 +#endif
602 + BUG_ON (offs >> ra->oob_shift); //page boundry
603 + BUG_ON ((unsigned int)(((offs + len) >> ra->oob_shift) + page) >
604 + ((page + pages_perblock) & ~(pages_perblock-1))); //block boundry
605 +
606 + use_gdma = flags & FLAG_USE_GDMA;
607 + ecc_en = flags & FLAG_ECC_EN;
608 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8) - 1));
609 +
610 + if (is_nand_page_2048) {
611 + bus_addr += CFG_PAGESIZE;
612 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
613 + cmd1 = 0x0;
614 + cmd2 = 0x30;
615 + conf = 0x000511| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
616 + }
617 + else {
618 + cmd1 = 0x50;
619 + conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
620 + }
621 + if (ecc_en)
622 + conf |= (1<<3);
623 + if (use_gdma)
624 + conf |= (1<<2);
625 +
626 + ra_dbg("%s: cmd1:%x, bus_addr:%x, conf:%x, len:%x, flag:%x\n",
627 + __func__, cmd1, bus_addr, conf, len, flags);
628 +
629 + status = _nfc_read_raw_data(cmd1, cmd2, bus_addr, bus_addr2, conf, buf, len, flags);
630 + if (status & NAND_STATUS_FAIL) {
631 + printk("%s: fail\n", __func__);
632 + return -EIO;
633 + }
634 +
635 + return 0;
636 +}
637 +
638 +/**
639 + * @return !0: fail
640 + * @return 0: OK
641 + */
642 +int nfc_write_oob(struct ra_nand_chip *ra, int page, unsigned int offs, char *buf, int len, int flags)
643 +{
644 + unsigned int cmd1 = 0, cmd3=0, conf = 0;
645 + unsigned int bus_addr = 0, bus_addr2 = 0;
646 + int use_gdma;
647 + int status;
648 +
649 + int pages_perblock = 1<<(ra->erase_shift - ra->page_shift);
650 + // constrain of nfc read function
651 +
652 + BUG_ON (offs >> ra->oob_shift); //page boundry
653 + BUG_ON ((unsigned int)(((offs + len) >> ra->oob_shift) + page) >
654 + ((page + pages_perblock) & ~(pages_perblock-1))); //block boundry
655 +
656 + use_gdma = flags & FLAG_USE_GDMA;
657 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8) - 1));
658 +
659 + if (is_nand_page_2048) {
660 + cmd1 = 0x80;
661 + cmd3 = 0x10;
662 + bus_addr += CFG_PAGESIZE;
663 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
664 + conf = 0x001123 | ((CFG_ADDR_CYCLE)<<16) | ((len) << 20);
665 + }
666 + else {
667 + cmd1 = 0x08050;
668 + cmd3 = 0x10;
669 + conf = 0x001223 | ((CFG_ADDR_CYCLE)<<16) | ((len) << 20);
670 + }
671 + if (use_gdma)
672 + conf |= (1<<2);
673 +
674 + // set NFC
675 + ra_dbg("%s: cmd1: %x, cmd3: %x bus_addr: %x, conf: %x, len:%x\n",
676 + __func__, cmd1, cmd3, bus_addr, conf, len);
677 +
678 + status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, len, flags);
679 + if (status & NAND_STATUS_FAIL) {
680 + printk("%s: fail \n", __func__);
681 + return -EIO;
682 + }
683 +
684 + return 0;
685 +}
686 +
687 +
688 +int nfc_read_page(struct ra_nand_chip *ra, char *buf, int page, int flags);
689 +int nfc_write_page(struct ra_nand_chip *ra, char *buf, int page, int flags);
690 +
691 +
692 +#if !defined (WORKAROUND_RX_BUF_OV)
693 +static int one_bit_correction(char *ecc, char *expected, int *bytes, int *bits);
694 +int nfc_ecc_verify(struct ra_nand_chip *ra, char *buf, int page, int mode)
695 +{
696 + int ret, i;
697 + char *p, *e;
698 + int ecc;
699 +
700 + //ra_dbg("%s, page:%x mode:%d\n", __func__, page, mode);
701 +
702 + if (mode == FL_WRITING) {
703 + int len = CFG_PAGESIZE + CFG_PAGE_OOBSIZE;
704 + int conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
705 + conf |= (1<<3); //(ecc_en)
706 + //conf |= (1<<2); // (use_gdma)
707 +
708 + p = ra->readback_buffers;
709 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_ECC_EN);
710 + if (ret == 0)
711 + goto ecc_check;
712 +
713 + //FIXME, double comfirm
714 + printk("%s: read back fail, try again \n",__func__);
715 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_ECC_EN);
716 + if (ret != 0) {
717 + printk("\t%s: read back fail agian \n",__func__);
718 + goto bad_block;
719 + }
720 + }
721 + else if (mode == FL_READING) {
722 + p = buf;
723 + }
724 + else
725 + return -2;
726 +
727 +ecc_check:
728 + p += CFG_PAGESIZE;
729 + if (!is_nand_page_2048) {
730 + ecc = ra_inl(NFC_ECC);
731 + if (ecc == 0) //clean page.
732 + return 0;
733 + e = (char*)&ecc;
734 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
735 + int eccpos = CONFIG_ECC_OFFSET + i;
736 + if (*(p + eccpos) != (char)0xff)
737 + break;
738 + if (i == CONFIG_ECC_BYTES - 1) {
739 + printk("skip ecc 0xff at page %x\n", page);
740 + return 0;
741 + }
742 + }
743 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
744 + int eccpos = CONFIG_ECC_OFFSET + i;
745 + if (*(p + eccpos) != *(e + i)) {
746 + printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, ecc:%x \n",
747 + __func__, (mode == FL_READING)?"read":"write", page,
748 + *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
749 + return -1;
750 + }
751 + }
752 + }
753 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
754 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
755 + else {
756 + int ecc2, ecc3, ecc4, qsz;
757 + char *e2, *e3, *e4;
758 + int correction_flag = 0;
759 + ecc = ra_inl(NFC_ECC_P1);
760 + ecc2 = ra_inl(NFC_ECC_P2);
761 + ecc3 = ra_inl(NFC_ECC_P3);
762 + ecc4 = ra_inl(NFC_ECC_P4);
763 + e = (char*)&ecc;
764 + e2 = (char*)&ecc2;
765 + e3 = (char*)&ecc3;
766 + e4 = (char*)&ecc4;
767 + qsz = CFG_PAGE_OOBSIZE / 4;
768 + if (ecc == 0 && ecc2 == 0 && ecc3 == 0 && ecc4 == 0)
769 + return 0;
770 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
771 + int eccpos = CONFIG_ECC_OFFSET + i;
772 + if (*(p + eccpos) != (char)0xff)
773 + break;
774 + else if (*(p + eccpos + qsz) != (char)0xff)
775 + break;
776 + else if (*(p + eccpos + qsz*2) != (char)0xff)
777 + break;
778 + else if (*(p + eccpos + qsz*3) != (char)0xff)
779 + break;
780 + if (i == CONFIG_ECC_BYTES - 1) {
781 + printk("skip ecc 0xff at page %x\n", page);
782 + return 0;
783 + }
784 + }
785 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
786 + int eccpos = CONFIG_ECC_OFFSET + i;
787 + if (*(p + eccpos) != *(e + i)) {
788 + printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, ecc:%x \n",
789 + __func__, (mode == FL_READING)?"read":"write", page,
790 + *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
791 + correction_flag |= 0x1;
792 + }
793 + if (*(p + eccpos + qsz) != *(e2 + i)) {
794 + printk("%s mode:%s, invalid ecc2, page: %x read:%x %x %x, ecc2:%x \n",
795 + __func__, (mode == FL_READING)?"read":"write", page,
796 + *(p+CONFIG_ECC_OFFSET+qsz), *(p+ CONFIG_ECC_OFFSET+1+qsz), *(p+ CONFIG_ECC_OFFSET+2+qsz), ecc2);
797 + correction_flag |= 0x2;
798 + }
799 + if (*(p + eccpos + qsz*2) != *(e3 + i)) {
800 + printk("%s mode:%s, invalid ecc3, page: %x read:%x %x %x, ecc3:%x \n",
801 + __func__, (mode == FL_READING)?"read":"write", page,
802 + *(p+CONFIG_ECC_OFFSET+qsz*2), *(p+ CONFIG_ECC_OFFSET+1+qsz*2), *(p+ CONFIG_ECC_OFFSET+2+qsz*2), ecc3);
803 + correction_flag |= 0x4;
804 + }
805 + if (*(p + eccpos + qsz*3) != *(e4 + i)) {
806 + printk("%s mode:%s, invalid ecc4, page: %x read:%x %x %x, ecc4:%x \n",
807 + __func__, (mode == FL_READING)?"read":"write", page,
808 + *(p+CONFIG_ECC_OFFSET+qsz*3), *(p+ CONFIG_ECC_OFFSET+1+qsz*3), *(p+ CONFIG_ECC_OFFSET+2+qsz*3), ecc4);
809 + correction_flag |= 0x8;
810 + }
811 + }
812 +
813 + if (correction_flag)
814 + {
815 + printk("trying to do correction!\n");
816 + if (correction_flag & 0x1)
817 + {
818 + int bytes, bits;
819 + char *pBuf = p - CFG_PAGESIZE;
820 +
821 + if (one_bit_correction(p + CONFIG_ECC_OFFSET, e, &bytes, &bits) == 0)
822 + {
823 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
824 + printk("1. correct byte %d, bit %d!\n", bytes, bits);
825 + }
826 + else
827 + {
828 + printk("failed to correct!\n");
829 + return -1;
830 + }
831 + }
832 +
833 + if (correction_flag & 0x2)
834 + {
835 + int bytes, bits;
836 + char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE/4;
837 +
838 + if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz), e2, &bytes, &bits) == 0)
839 + {
840 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
841 + printk("2. correct byte %d, bit %d!\n", bytes, bits);
842 + }
843 + else
844 + {
845 + printk("failed to correct!\n");
846 + return -1;
847 + }
848 + }
849 + if (correction_flag & 0x4)
850 + {
851 + int bytes, bits;
852 + char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE/2;
853 +
854 + if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz * 2), e3, &bytes, &bits) == 0)
855 + {
856 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
857 + printk("3. correct byte %d, bit %d!\n", bytes, bits);
858 + }
859 + else
860 + {
861 + printk("failed to correct!\n");
862 + return -1;
863 + }
864 + }
865 + if (correction_flag & 0x8)
866 + {
867 + int bytes, bits;
868 + char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE*3/4;
869 +
870 + if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz * 3), e4, &bytes, &bits) == 0)
871 + {
872 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
873 + printk("4. correct byte %d, bit %d!\n", bytes, bits);
874 + }
875 + else
876 + {
877 + printk("failed to correct!\n");
878 + return -1;
879 + }
880 + }
881 + }
882 +
883 + }
884 +#endif
885 + return 0;
886 +
887 +bad_block:
888 + return -1;
889 +}
890 +
891 +#else
892 +
893 +void ranfc_dump(void)
894 +{
895 + int i;
896 + for (i=0; i<11; i++) {
897 + if (i==6)
898 + continue;
899 + printk("%x: %x \n", NFC_BASE + i*4, ra_inl(NFC_BASE + i*4));
900 + }
901 +}
902 +
903 +/**
904 + * @return 0, ecc OK or corrected.
905 + * @return NAND_STATUS_FAIL, ecc fail.
906 + */
907 +
908 +int nfc_ecc_verify(struct ra_nand_chip *ra, char *buf, int page, int mode)
909 +{
910 + int ret, i;
911 + char *p, *e;
912 + int ecc;
913 +
914 + if (ranfc_verify == 0)
915 + return 0;
916 +
917 + ra_dbg("%s, page:%x mode:%d\n", __func__, page, mode);
918 +
919 + if (mode == FL_WRITING) { // read back and memcmp
920 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_NONE);
921 + if (ret != 0) //double comfirm
922 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_NONE);
923 +
924 + if (ret != 0) {
925 + printk("%s: mode:%x read back fail \n", __func__, mode);
926 + return -1;
927 + }
928 + return memcmp(buf, ra->readback_buffers, 1<<ra->page_shift);
929 + }
930 +
931 + if (mode == FL_READING) {
932 +#if 0
933 + if (ra->sandbox_page == 0)
934 + return 0;
935 +
936 + ret = nfc_write_page(ra, buf, ra->sandbox_page, FLAG_USE_GDMA | FLAG_ECC_EN);
937 + if (ret != 0) {
938 + printk("%s, fail write sandbox_page \n", __func__);
939 + return -1;
940 + }
941 +#else
942 + /** @note:
943 + * The following command is actually not 'write' command to drive NFC to write flash.
944 + * However, it can make NFC to calculate ECC, that will be used to compare with original ones.
945 + * --YT
946 + */
947 + unsigned int conf = 0x001223| (CFG_ADDR_CYCLE<<16) | (0x200 << 20) | (1<<3) | (1<<2);
948 + _nfc_write_raw_data(0xff, 0xff, ra->sandbox_page<<ra->page_shift, conf, buf, 0x200, FLAG_USE_GDMA);
949 +#endif
950 +
951 + ecc = ra_inl(NFC_ECC);
952 + if (ecc == 0) //clean page.
953 + return 0;
954 + e = (char*)&ecc;
955 + p = buf + (1<<ra->page_shift);
956 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
957 + int eccpos = CONFIG_ECC_OFFSET + i;
958 + if (*(p + eccpos) != *(e + i)) {
959 + printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, write:%x \n",
960 + __func__, (mode == FL_READING)?"read":"write", page,
961 + *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
962 +
963 + for (i=0; i<528; i++)
964 + printk("%-2x \n", *(buf + i));
965 + return -1;
966 + }
967 + }
968 + return 0;
969 + }
970 +
971 + return -1;
972 +
973 +}
974 +
975 +#endif
976 +
977 +
978 +/**
979 + * @return -EIO, writing size is less than a page
980 + * @return 0, OK
981 + */
982 +int nfc_read_page(struct ra_nand_chip *ra, char *buf, int page, int flags)
983 +{
984 + unsigned int cmd1 = 0, cmd2 = 0, conf = 0;
985 + unsigned int bus_addr = 0, bus_addr2 = 0;
986 + unsigned int ecc_en;
987 + int use_gdma;
988 + int size, offs;
989 + int status = 0;
990 +
991 + use_gdma = flags & FLAG_USE_GDMA;
992 + ecc_en = flags & FLAG_ECC_EN;
993 +
994 + page = page & (CFG_CHIPSIZE - 1); // chip boundary
995 + size = CFG_PAGESIZE + CFG_PAGE_OOBSIZE; //add oobsize
996 + offs = 0;
997 +
998 + while (size > 0) {
999 + int len;
1000 +#if defined (WORKAROUND_RX_BUF_OV)
1001 + len = min(60, size);
1002 +#else
1003 + len = size;
1004 +#endif
1005 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8)-1));
1006 + if (is_nand_page_2048) {
1007 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
1008 + cmd1 = 0x0;
1009 + cmd2 = 0x30;
1010 + conf = 0x000511| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
1011 + }
1012 + else {
1013 + if (offs & ~(CFG_PAGESIZE-1))
1014 + cmd1 = 0x50;
1015 + else if (offs & ~((1<<CFG_COLUMN_ADDR_CYCLE*8)-1))
1016 + cmd1 = 0x01;
1017 + else
1018 + cmd1 = 0;
1019 +
1020 + conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
1021 + }
1022 +#if !defined (WORKAROUND_RX_BUF_OV)
1023 + if (ecc_en)
1024 + conf |= (1<<3);
1025 +#endif
1026 + if (use_gdma)
1027 + conf |= (1<<2);
1028 +
1029 + status = _nfc_read_raw_data(cmd1, cmd2, bus_addr, bus_addr2, conf, buf+offs, len, flags);
1030 + if (status & NAND_STATUS_FAIL) {
1031 + printk("%s: fail \n", __func__);
1032 + return -EIO;
1033 + }
1034 +
1035 + offs += len;
1036 + size -= len;
1037 + }
1038 +
1039 + // verify and correct ecc
1040 + if ((flags & (FLAG_VERIFY | FLAG_ECC_EN)) == (FLAG_VERIFY | FLAG_ECC_EN)) {
1041 + status = nfc_ecc_verify(ra, buf, page, FL_READING);
1042 + if (status != 0) {
1043 + printk("%s: fail, buf:%x, page:%x, flag:%x\n",
1044 + __func__, (unsigned int)buf, page, flags);
1045 + return -EBADMSG;
1046 + }
1047 + }
1048 + else {
1049 + // fix,e not yet support
1050 + ra->buffers_page = -1; //cached
1051 + }
1052 +
1053 + return 0;
1054 +}
1055 +
1056 +
1057 +/**
1058 + * @return -EIO, fail to write
1059 + * @return 0, OK
1060 + */
1061 +int nfc_write_page(struct ra_nand_chip *ra, char *buf, int page, int flags)
1062 +{
1063 + unsigned int cmd1 = 0, cmd3, conf = 0;
1064 + unsigned int bus_addr = 0, bus_addr2 = 0;
1065 + unsigned int ecc_en;
1066 + int use_gdma;
1067 + int size;
1068 + char status;
1069 + uint8_t *oob = buf + (1<<ra->page_shift);
1070 +
1071 + use_gdma = flags & FLAG_USE_GDMA;
1072 + ecc_en = flags & FLAG_ECC_EN;
1073 +
1074 + oob[ra->badblockpos] = 0xff; //tag as good block.
1075 + ra->buffers_page = -1; //cached
1076 +
1077 + page = page & (CFG_CHIPSIZE-1); //chip boundary
1078 + size = CFG_PAGESIZE + CFG_PAGE_OOBSIZE; //add oobsize
1079 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)); //write_page always write from offset 0.
1080 +
1081 + if (is_nand_page_2048) {
1082 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
1083 + cmd1 = 0x80;
1084 + cmd3 = 0x10;
1085 + conf = 0x001123| ((CFG_ADDR_CYCLE)<<16) | (size << 20);
1086 + }
1087 + else {
1088 + cmd1 = 0x8000;
1089 + cmd3 = 0x10;
1090 + conf = 0x001223| ((CFG_ADDR_CYCLE)<<16) | (size << 20);
1091 +}
1092 + if (ecc_en)
1093 + conf |= (1<<3); //enable ecc
1094 + if (use_gdma)
1095 + conf |= (1<<2);
1096 +
1097 + // set NFC
1098 + ra_dbg("nfc_write_page: cmd1: %x, cmd3: %x bus_addr: %x, conf: %x, len:%x\n",
1099 + cmd1, cmd3, bus_addr, conf, size);
1100 +
1101 + status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, size, flags);
1102 + if (status & NAND_STATUS_FAIL) {
1103 + printk("%s: fail \n", __func__);
1104 + return -EIO;
1105 + }
1106 +
1107 +
1108 + if (flags & FLAG_VERIFY) { // verify and correct ecc
1109 + status = nfc_ecc_verify(ra, buf, page, FL_WRITING);
1110 +
1111 +#ifdef RANDOM_GEN_BAD_BLOCK
1112 + if (((random32() & 0x1ff) == 0x0) && (page >= 0x100)) // randomly create bad block
1113 + {
1114 + printk("hmm... create a bad block at page %x\n", (bus_addr >> 16));
1115 + status = -1;
1116 + }
1117 +#endif
1118 +
1119 + if (status != 0) {
1120 + printk("%s: ecc_verify fail: ret:%x \n", __func__, status);
1121 + oob[ra->badblockpos] = 0x33;
1122 + page -= page % (CFG_BLOCKSIZE/CFG_PAGESIZE);
1123 + printk("create a bad block at page %x\n", page);
1124 + if (!is_nand_page_2048)
1125 + status = nfc_write_oob(ra, page, ra->badblockpos, oob+ra->badblockpos, 1, flags);
1126 + else
1127 + {
1128 + status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, size, flags);
1129 + nfc_write_oob(ra, page, 0, oob, 16, FLAG_NONE);
1130 + }
1131 + return -EBADMSG;
1132 + }
1133 + }
1134 +
1135 +
1136 + ra->buffers_page = page; //cached
1137 + return 0;
1138 +}
1139 +
1140 +
1141 +
1142 +/*************************************************************
1143 + * nand internal process
1144 + *************************************************************/
1145 +
1146 +/**
1147 + * nand_release_device - [GENERIC] release chip
1148 + * @mtd: MTD device structure
1149 + *
1150 + * Deselect, release chip lock and wake up anyone waiting on the device
1151 + */
1152 +static void nand_release_device(struct ra_nand_chip *ra)
1153 +{
1154 + /* De-select the NAND device */
1155 + nfc_select_chip(ra, -1);
1156 +
1157 + /* Release the controller and the chip */
1158 + ra->state = FL_READY;
1159 +
1160 + mutex_unlock(ra->controller);
1161 +}
1162 +
1163 +/**
1164 + * nand_get_device - [GENERIC] Get chip for selected access
1165 + * @chip: the nand chip descriptor
1166 + * @mtd: MTD device structure
1167 + * @new_state: the state which is requested
1168 + *
1169 + * Get the device and lock it for exclusive access
1170 + */
1171 +static int
1172 +nand_get_device(struct ra_nand_chip *ra, int new_state)
1173 +{
1174 + int ret = 0;
1175 +
1176 + ret = mutex_lock_interruptible(ra->controller);
1177 + if (!ret)
1178 + ra->state = new_state;
1179 +
1180 + return ret;
1181 +
1182 +}
1183 +
1184 +
1185 +
1186 +/*************************************************************
1187 + * nand internal process
1188 + *************************************************************/
1189 +
1190 +int nand_bbt_get(struct ra_nand_chip *ra, int block)
1191 +{
1192 + int byte, bits;
1193 + bits = block * BBTTAG_BITS;
1194 +
1195 + byte = bits / 8;
1196 + bits = bits % 8;
1197 +
1198 + return (ra->bbt[byte] >> bits) & BBTTAG_BITS_MASK;
1199 +}
1200 +
1201 +int nand_bbt_set(struct ra_nand_chip *ra, int block, int tag)
1202 +{
1203 + int byte, bits;
1204 + bits = block * BBTTAG_BITS;
1205 +
1206 + byte = bits / 8;
1207 + bits = bits % 8;
1208 +
1209 + // If previous tag is bad, dont overwrite it
1210 + if (((ra->bbt[byte] >> bits) & BBTTAG_BITS_MASK) == BBT_TAG_BAD)
1211 + {
1212 + return BBT_TAG_BAD;
1213 + }
1214 +
1215 + ra->bbt[byte] = (ra->bbt[byte] & ~(BBTTAG_BITS_MASK << bits)) | ((tag & BBTTAG_BITS_MASK) << bits);
1216 +
1217 + return tag;
1218 +}
1219 +
1220 +/**
1221 + * nand_block_checkbad - [GENERIC] Check if a block is marked bad
1222 + * @mtd: MTD device structure
1223 + * @ofs: offset from device start
1224 + *
1225 + * Check, if the block is bad. Either by reading the bad block table or
1226 + * calling of the scan function.
1227 + */
1228 +int nand_block_checkbad(struct ra_nand_chip *ra, loff_t offs)
1229 +{
1230 + int page, block;
1231 + int ret = 4;
1232 + unsigned int tag;
1233 + char *str[]= {"UNK", "RES", "BAD", "GOOD"};
1234 +
1235 + if (ranfc_bbt == 0)
1236 + return 0;
1237 +
1238 + {
1239 + // align with chip
1240 +
1241 + offs = offs & ((1<<ra->chip_shift) -1);
1242 +
1243 + page = offs >> ra->page_shift;
1244 + block = offs >> ra->erase_shift;
1245 + }
1246 +
1247 + tag = nand_bbt_get(ra, block);
1248 +
1249 + if (tag == BBT_TAG_UNKNOWN) {
1250 + ret = nfc_read_oob(ra, page, ra->badblockpos, (char*)&tag, 1, FLAG_NONE);
1251 + if (ret == 0)
1252 + tag = ((le32_to_cpu(tag) & 0x0ff) == 0x0ff) ? BBT_TAG_GOOD : BBT_TAG_BAD;
1253 + else
1254 + tag = BBT_TAG_BAD;
1255 +
1256 + nand_bbt_set(ra, block, tag);
1257 + }
1258 +
1259 + if (tag != BBT_TAG_GOOD) {
1260 + printk("%s: offs:%x tag: %s \n", __func__, (unsigned int)offs, str[tag]);
1261 + return 1;
1262 + }
1263 + else
1264 + return 0;
1265 +
1266 +}
1267 +
1268 +
1269 +
1270 +/**
1271 + * nand_block_markbad -
1272 + */
1273 +int nand_block_markbad(struct ra_nand_chip *ra, loff_t offs)
1274 +{
1275 + int page, block;
1276 + int ret = 4;
1277 + unsigned int tag;
1278 + char *ecc;
1279 +
1280 + // align with chip
1281 + ra_dbg("%s offs: %x \n", __func__, (int)offs);
1282 +
1283 + offs = offs & ((1<<ra->chip_shift) -1);
1284 +
1285 + page = offs >> ra->page_shift;
1286 + block = offs >> ra->erase_shift;
1287 +
1288 + tag = nand_bbt_get(ra, block);
1289 +
1290 + if (tag == BBT_TAG_BAD) {
1291 + printk("%s: mark repeatedly \n", __func__);
1292 + return 0;
1293 + }
1294 +
1295 + // new tag as bad
1296 + tag =BBT_TAG_BAD;
1297 + ret = nfc_read_page(ra, ra->buffers, page, FLAG_NONE);
1298 + if (ret != 0) {
1299 + printk("%s: fail to read bad block tag \n", __func__);
1300 + goto tag_bbt;
1301 + }
1302 +
1303 + ecc = &ra->buffers[(1<<ra->page_shift)+ra->badblockpos];
1304 + if (*ecc == (char)0x0ff) {
1305 + //tag into flash
1306 + *ecc = (char)tag;
1307 + ret = nfc_write_page(ra, ra->buffers, page, FLAG_USE_GDMA);
1308 + if (ret)
1309 + printk("%s: fail to write bad block tag \n", __func__);
1310 +
1311 + }
1312 +
1313 +tag_bbt:
1314 + //update bbt
1315 + nand_bbt_set(ra, block, tag);
1316 +
1317 + return 0;
1318 +}
1319 +
1320 +
1321 +#if defined (WORKAROUND_RX_BUF_OV)
1322 +/**
1323 + * to find a bad block for ecc verify of read_page
1324 + */
1325 +unsigned int nand_bbt_find_sandbox(struct ra_nand_chip *ra)
1326 +{
1327 + loff_t offs = 0;
1328 + int chipsize = 1 << ra->chip_shift;
1329 + int blocksize = 1 << ra->erase_shift;
1330 +
1331 +
1332 + while (offs < chipsize) {
1333 + if (nand_block_checkbad(ra, offs)) //scan and verify the unknown tag
1334 + break;
1335 + offs += blocksize;
1336 + }
1337 +
1338 + if (offs >= chipsize) {
1339 + offs = chipsize - blocksize;
1340 + }
1341 +
1342 + nand_bbt_set(ra, (unsigned int)offs>>ra->erase_shift, BBT_TAG_RES); // tag bbt only, instead of update badblockpos of flash.
1343 + return (offs >> ra->page_shift);
1344 +}
1345 +#endif
1346 +
1347 +
1348 +
1349 +/**
1350 + * nand_erase_nand - [Internal] erase block(s)
1351 + * @mtd: MTD device structure
1352 + * @instr: erase instruction
1353 + * @allowbbt: allow erasing the bbt area
1354 + *
1355 + * Erase one ore more blocks
1356 + */
1357 +int _nand_erase_nand(struct ra_nand_chip *ra, struct erase_info *instr)
1358 +{
1359 + int page, len, status, ret;
1360 + unsigned int addr, blocksize = 1<<ra->erase_shift;
1361 +
1362 + ra_dbg("%s: start:%x, len:%x \n", __func__,
1363 + (unsigned int)instr->addr, (unsigned int)instr->len);
1364 +
1365 +//#define BLOCK_ALIGNED(a) ((a) & (blocksize - 1)) // already defined
1366 +
1367 + if (BLOCK_ALIGNED(instr->addr) || BLOCK_ALIGNED(instr->len)) {
1368 + ra_dbg("%s: erase block not aligned, addr:%x len:%x\n", __func__, instr->addr, instr->len);
1369 + return -EINVAL;
1370 + }
1371 +
1372 + instr->fail_addr = 0xffffffff;
1373 +
1374 + len = instr->len;
1375 + addr = instr->addr;
1376 + instr->state = MTD_ERASING;
1377 +
1378 + while (len) {
1379 +
1380 + page = (int)(addr >> ra->page_shift);
1381 +
1382 + /* select device and check wp */
1383 + if (nfc_enable_chip(ra, addr, 0)) {
1384 + printk("%s: nand is write protected \n", __func__);
1385 + instr->state = MTD_ERASE_FAILED;
1386 + goto erase_exit;
1387 + }
1388 +
1389 + /* if we have a bad block, we do not erase bad blocks */
1390 + if (nand_block_checkbad(ra, addr)) {
1391 + printk(KERN_WARNING "nand_erase: attempt to erase a "
1392 + "bad block at 0x%08x\n", addr);
1393 + instr->state = MTD_ERASE_FAILED;
1394 + goto erase_exit;
1395 + }
1396 +
1397 + /*
1398 + * Invalidate the page cache, if we erase the block which
1399 + * contains the current cached page
1400 + */
1401 + if (BLOCK_ALIGNED(addr) == BLOCK_ALIGNED(ra->buffers_page << ra->page_shift))
1402 + ra->buffers_page = -1;
1403 +
1404 + status = nfc_erase_block(ra, page);
1405 + /* See if block erase succeeded */
1406 + if (status) {
1407 + printk("%s: failed erase, page 0x%08x\n", __func__, page);
1408 + instr->state = MTD_ERASE_FAILED;
1409 + instr->fail_addr = (page << ra->page_shift);
1410 + goto erase_exit;
1411 + }
1412 +
1413 +
1414 + /* Increment page address and decrement length */
1415 + len -= blocksize;
1416 + addr += blocksize;
1417 +
1418 + }
1419 + instr->state = MTD_ERASE_DONE;
1420 +
1421 +erase_exit:
1422 +
1423 + ret = ((instr->state == MTD_ERASE_DONE) ? 0 : -EIO);
1424 + /* Do call back function */
1425 + if (!ret)
1426 + mtd_erase_callback(instr);
1427 +
1428 + if (ret) {
1429 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
1430 + }
1431 +
1432 + /* Return more or less happy */
1433 + return ret;
1434 +}
1435 +
1436 +static int
1437 +nand_write_oob_buf(struct ra_nand_chip *ra, uint8_t *buf, uint8_t *oob, size_t size,
1438 + int mode, int ooboffs)
1439 +{
1440 + size_t oobsize = 1<<ra->oob_shift;
1441 + struct nand_oobfree *free;
1442 + uint32_t woffs = ooboffs;
1443 + int retsize = 0;
1444 +
1445 + ra_dbg("%s: size:%x, mode:%x, offs:%x \n", __func__, size, mode, ooboffs);
1446 +
1447 + switch(mode) {
1448 + case MTD_OPS_PLACE_OOB:
1449 + case MTD_OPS_RAW:
1450 + if (ooboffs > oobsize)
1451 + return -1;
1452 +
1453 + size = min(size, oobsize - ooboffs);
1454 + memcpy(buf + ooboffs, oob, size);
1455 + retsize = size;
1456 + break;
1457 +
1458 + case MTD_OPS_AUTO_OOB:
1459 + if (ooboffs > ra->oob->oobavail)
1460 + return -1;
1461 +
1462 + while (size) {
1463 + for(free = ra->oob->oobfree; free->length && size; free++) {
1464 + int wlen = free->length - woffs;
1465 + int bytes = 0;
1466 +
1467 + /* Write request not from offset 0 ? */
1468 + if (wlen <= 0) {
1469 + woffs = -wlen;
1470 + continue;
1471 + }
1472 +
1473 + bytes = min_t(size_t, size, wlen);
1474 + memcpy (buf + free->offset + woffs, oob, bytes);
1475 + woffs = 0;
1476 + oob += bytes;
1477 + size -= bytes;
1478 + retsize += bytes;
1479 + }
1480 + buf += oobsize;
1481 + }
1482 + break;
1483 +
1484 + default:
1485 + BUG();
1486 + }
1487 +
1488 + return retsize;
1489 +}
1490 +
1491 +static int nand_read_oob_buf(struct ra_nand_chip *ra, uint8_t *oob, size_t size,
1492 + int mode, int ooboffs)
1493 +{
1494 + size_t oobsize = 1<<ra->oob_shift;
1495 + uint8_t *buf = ra->buffers + (1<<ra->page_shift);
1496 + int retsize=0;
1497 +
1498 + ra_dbg("%s: size:%x, mode:%x, offs:%x \n", __func__, size, mode, ooboffs);
1499 +
1500 + switch(mode) {
1501 + case MTD_OPS_PLACE_OOB:
1502 + case MTD_OPS_RAW:
1503 + if (ooboffs > oobsize)
1504 + return -1;
1505 +
1506 + size = min(size, oobsize - ooboffs);
1507 + memcpy(oob, buf + ooboffs, size);
1508 + return size;
1509 +
1510 + case MTD_OPS_AUTO_OOB: {
1511 + struct nand_oobfree *free;
1512 + uint32_t woffs = ooboffs;
1513 +
1514 + if (ooboffs > ra->oob->oobavail)
1515 + return -1;
1516 +
1517 + size = min(size, ra->oob->oobavail - ooboffs);
1518 + for(free = ra->oob->oobfree; free->length && size; free++) {
1519 + int wlen = free->length - woffs;
1520 + int bytes = 0;
1521 +
1522 + /* Write request not from offset 0 ? */
1523 + if (wlen <= 0) {
1524 + woffs = -wlen;
1525 + continue;
1526 + }
1527 +
1528 + bytes = min_t(size_t, size, wlen);
1529 + memcpy (oob, buf + free->offset + woffs, bytes);
1530 + woffs = 0;
1531 + oob += bytes;
1532 + size -= bytes;
1533 + retsize += bytes;
1534 + }
1535 + return retsize;
1536 + }
1537 + default:
1538 + BUG();
1539 + }
1540 +
1541 + return -1;
1542 +}
1543 +
1544 +/**
1545 + * nand_do_write_ops - [Internal] NAND write with ECC
1546 + * @mtd: MTD device structure
1547 + * @to: offset to write to
1548 + * @ops: oob operations description structure
1549 + *
1550 + * NAND write with ECC
1551 + */
1552 +static int nand_do_write_ops(struct ra_nand_chip *ra, loff_t to,
1553 + struct mtd_oob_ops *ops)
1554 +{
1555 + int page;
1556 + uint32_t datalen = ops->len;
1557 + uint32_t ooblen = ops->ooblen;
1558 + uint8_t *oob = ops->oobbuf;
1559 + uint8_t *data = ops->datbuf;
1560 + int pagesize = (1<<ra->page_shift);
1561 + int pagemask = (pagesize -1);
1562 + int oobsize = 1<<ra->oob_shift;
1563 + loff_t addr = to;
1564 + //int i = 0; //for ra_dbg only
1565 +
1566 + ra_dbg("%s: to:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x oobmode:%x \n",
1567 + __func__, (unsigned int)to, data, oob, datalen, ooblen, ops->ooboffs, ops->mode);
1568 +
1569 + ops->retlen = 0;
1570 + ops->oobretlen = 0;
1571 +
1572 +
1573 + /* Invalidate the page cache, when we write to the cached page */
1574 + ra->buffers_page = -1;
1575 +
1576 +
1577 + if (data ==0)
1578 + datalen = 0;
1579 +
1580 + // oob sequential (burst) write
1581 + if (datalen == 0 && ooblen) {
1582 + int len = ((ooblen + ops->ooboffs) + (ra->oob->oobavail - 1)) / ra->oob->oobavail * oobsize;
1583 +
1584 + /* select chip, and check if it is write protected */
1585 + if (nfc_enable_chip(ra, addr, 0))
1586 + return -EIO;
1587 +
1588 + //FIXME, need sanity check of block boundary
1589 + page = (int)((to & ((1<<ra->chip_shift)-1)) >> ra->page_shift); //chip boundary
1590 + memset(ra->buffers, 0x0ff, pagesize);
1591 + //fixme, should we reserve the original content?
1592 + if (ops->mode == MTD_OPS_AUTO_OOB) {
1593 + nfc_read_oob(ra, page, 0, ra->buffers, len, FLAG_NONE);
1594 + }
1595 + //prepare buffers
1596 + if (ooblen != 8)
1597 + {
1598 + nand_write_oob_buf(ra, ra->buffers, oob, ooblen, ops->mode, ops->ooboffs);
1599 + // write out buffer to chip
1600 + nfc_write_oob(ra, page, 0, ra->buffers, len, FLAG_USE_GDMA);
1601 + }
1602 +
1603 + ops->oobretlen = ooblen;
1604 + ooblen = 0;
1605 + }
1606 +
1607 + // data sequential (burst) write
1608 + if (datalen && ooblen == 0) {
1609 + // ranfc can not support write_data_burst, since hw-ecc and fifo constraints..
1610 + }
1611 +
1612 + // page write
1613 + while(datalen || ooblen) {
1614 + int len;
1615 + int ret;
1616 + int offs;
1617 + int ecc_en = 0;
1618 +
1619 + ra_dbg("%s (%d): addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
1620 + __func__, i++, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
1621 +
1622 + page = (int)((addr & ((1<<ra->chip_shift)-1)) >> ra->page_shift); //chip boundary
1623 +
1624 + /* select chip, and check if it is write protected */
1625 + if (nfc_enable_chip(ra, addr, 0))
1626 + return -EIO;
1627 +
1628 + // oob write
1629 + if (ops->mode == MTD_OPS_AUTO_OOB) {
1630 + //fixme, this path is not yet varified
1631 + nfc_read_oob(ra, page, 0, ra->buffers + pagesize, oobsize, FLAG_NONE);
1632 + }
1633 + if (oob && ooblen > 0) {
1634 + len = nand_write_oob_buf(ra, ra->buffers + pagesize, oob, ooblen, ops->mode, ops->ooboffs);
1635 + if (len < 0)
1636 + return -EINVAL;
1637 +
1638 + oob += len;
1639 + ops->oobretlen += len;
1640 + ooblen -= len;
1641 + }
1642 +
1643 + // data write
1644 + offs = addr & pagemask;
1645 + len = min_t(size_t, datalen, pagesize - offs);
1646 + if (data && len > 0) {
1647 + memcpy(ra->buffers + offs, data, len); // we can not sure ops->buf wether is DMA-able.
1648 +
1649 + data += len;
1650 + datalen -= len;
1651 + ops->retlen += len;
1652 +
1653 + ecc_en = FLAG_ECC_EN;
1654 + }
1655 + ret = nfc_write_page(ra, ra->buffers, page, FLAG_USE_GDMA | FLAG_VERIFY |
1656 + ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0 : ecc_en ));
1657 + if (ret) {
1658 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
1659 + return ret;
1660 + }
1661 +
1662 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_GOOD);
1663 +
1664 + addr = (page+1) << ra->page_shift;
1665 +
1666 + }
1667 + return 0;
1668 +}
1669 +
1670 +/**
1671 + * nand_do_read_ops - [Internal] Read data with ECC
1672 + *
1673 + * @mtd: MTD device structure
1674 + * @from: offset to read from
1675 + * @ops: oob ops structure
1676 + *
1677 + * Internal function. Called with chip held.
1678 + */
1679 +static int nand_do_read_ops(struct ra_nand_chip *ra, loff_t from,
1680 + struct mtd_oob_ops *ops)
1681 +{
1682 + int page;
1683 + uint32_t datalen = ops->len;
1684 + uint32_t ooblen = ops->ooblen;
1685 + uint8_t *oob = ops->oobbuf;
1686 + uint8_t *data = ops->datbuf;
1687 + int pagesize = (1<<ra->page_shift);
1688 + int pagemask = (pagesize -1);
1689 + loff_t addr = from;
1690 + //int i = 0; //for ra_dbg only
1691 +
1692 + ra_dbg("%s: addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
1693 + __func__, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
1694 +
1695 + ops->retlen = 0;
1696 + ops->oobretlen = 0;
1697 + if (data == 0)
1698 + datalen = 0;
1699 +
1700 +
1701 + while(datalen || ooblen) {
1702 + int len;
1703 + int ret;
1704 + int offs;
1705 +
1706 + ra_dbg("%s (%d): addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
1707 + __func__, i++, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
1708 + /* select chip */
1709 + if (nfc_enable_chip(ra, addr, 1) < 0)
1710 + return -EIO;
1711 +
1712 + page = (int)((addr & ((1<<ra->chip_shift)-1)) >> ra->page_shift);
1713 +
1714 + ret = nfc_read_page(ra, ra->buffers, page, FLAG_VERIFY |
1715 + ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0: FLAG_ECC_EN ));
1716 + //FIXME, something strange here, some page needs 2 more tries to guarantee read success.
1717 + if (ret) {
1718 + printk("read again:\n");
1719 + ret = nfc_read_page(ra, ra->buffers, page, FLAG_VERIFY |
1720 + ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0: FLAG_ECC_EN ));
1721 +
1722 + if (ret) {
1723 + printk("read again fail \n");
1724 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
1725 + if ((ret != -EUCLEAN) && (ret != -EBADMSG)) {
1726 + return ret;
1727 + }
1728 + else {
1729 + /* ecc verification fail, but data need to be returned. */
1730 + }
1731 + }
1732 + else {
1733 + printk(" read agian susccess \n");
1734 + }
1735 + }
1736 +
1737 + // oob read
1738 + if (oob && ooblen > 0) {
1739 + len = nand_read_oob_buf(ra, oob, ooblen, ops->mode, ops->ooboffs);
1740 + if (len < 0) {
1741 + printk("nand_read_oob_buf: fail return %x \n", len);
1742 + return -EINVAL;
1743 + }
1744 +
1745 + oob += len;
1746 + ops->oobretlen += len;
1747 + ooblen -= len;
1748 + }
1749 +
1750 + // data read
1751 + offs = addr & pagemask;
1752 + len = min_t(size_t, datalen, pagesize - offs);
1753 + if (data && len > 0) {
1754 + memcpy(data, ra->buffers + offs, len); // we can not sure ops->buf wether is DMA-able.
1755 +
1756 + data += len;
1757 + datalen -= len;
1758 + ops->retlen += len;
1759 + if (ret)
1760 + return ret;
1761 + }
1762 +
1763 +
1764 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_GOOD);
1765 + // address go further to next page, instead of increasing of length of write. This avoids some special cases wrong.
1766 + addr = (page+1) << ra->page_shift;
1767 + }
1768 + return 0;
1769 +}
1770 +
1771 +static int
1772 +ramtd_nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1773 +{
1774 + struct ra_nand_chip *ra = (struct ra_nand_chip *)mtd->priv;
1775 + int ret;
1776 +
1777 + ra_dbg("%s: start:%x, len:%x \n", __func__,
1778 + (unsigned int)instr->addr, (unsigned int)instr->len);
1779 +
1780 + nand_get_device(ra, FL_ERASING);
1781 + ret = _nand_erase_nand((struct ra_nand_chip *)mtd->priv, instr);
1782 + nand_release_device(ra);
1783 +
1784 + return ret;
1785 +}
1786 +
1787 +static int
1788 +ramtd_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1789 + size_t *retlen, const uint8_t *buf)
1790 +{
1791 + struct ra_nand_chip *ra = mtd->priv;
1792 + struct mtd_oob_ops ops;
1793 + int ret;
1794 +
1795 + ra_dbg("%s: to 0x%x len=0x%x\n", __func__, to, len);
1796 +
1797 + if ((to + len) > mtd->size)
1798 + return -EINVAL;
1799 +
1800 + if (!len)
1801 + return 0;
1802 +
1803 + nand_get_device(ra, FL_WRITING);
1804 +
1805 + memset(&ops, 0, sizeof(ops));
1806 + ops.len = len;
1807 + ops.datbuf = (uint8_t *)buf;
1808 + ops.oobbuf = NULL;
1809 + ops.mode = MTD_OPS_AUTO_OOB;
1810 +
1811 + ret = nand_do_write_ops(ra, to, &ops);
1812 +
1813 + *retlen = ops.retlen;
1814 +
1815 + nand_release_device(ra);
1816 +
1817 + return ret;
1818 +}
1819 +
1820 +static int
1821 +ramtd_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1822 + size_t *retlen, uint8_t *buf)
1823 +{
1824 +
1825 + struct ra_nand_chip *ra = mtd->priv;
1826 + int ret;
1827 + struct mtd_oob_ops ops;
1828 +
1829 + ra_dbg("%s: mtd:%p from:%x, len:%x, buf:%p \n", __func__, mtd, (unsigned int)from, len, buf);
1830 +
1831 + /* Do not allow reads past end of device */
1832 + if ((from + len) > mtd->size)
1833 + return -EINVAL;
1834 + if (!len)
1835 + return 0;
1836 +
1837 + nand_get_device(ra, FL_READING);
1838 +
1839 + memset(&ops, 0, sizeof(ops));
1840 + ops.len = len;
1841 + ops.datbuf = buf;
1842 + ops.oobbuf = NULL;
1843 + ops.mode = MTD_OPS_AUTO_OOB;
1844 +
1845 + ret = nand_do_read_ops(ra, from, &ops);
1846 +
1847 + *retlen = ops.retlen;
1848 +
1849 + nand_release_device(ra);
1850 +
1851 + return ret;
1852 +
1853 +}
1854 +
1855 +static int
1856 +ramtd_nand_readoob(struct mtd_info *mtd, loff_t from,
1857 + struct mtd_oob_ops *ops)
1858 +{
1859 + struct ra_nand_chip *ra = mtd->priv;
1860 + int ret;
1861 +
1862 + ra_dbg("%s: \n", __func__);
1863 +
1864 + nand_get_device(ra, FL_READING);
1865 +
1866 + ret = nand_do_read_ops(ra, from, ops);
1867 +
1868 + nand_release_device(ra);
1869 +
1870 + return ret;
1871 +}
1872 +
1873 +static int
1874 +ramtd_nand_writeoob(struct mtd_info *mtd, loff_t to,
1875 + struct mtd_oob_ops *ops)
1876 +{
1877 + struct ra_nand_chip *ra = mtd->priv;
1878 + int ret;
1879 +
1880 + nand_get_device(ra, FL_READING);
1881 + ret = nand_do_write_ops(ra, to, ops);
1882 + nand_release_device(ra);
1883 +
1884 + return ret;
1885 +}
1886 +
1887 +static int
1888 +ramtd_nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1889 +{
1890 + if (offs > mtd->size)
1891 + return -EINVAL;
1892 +
1893 + return nand_block_checkbad((struct ra_nand_chip *)mtd->priv, offs);
1894 +}
1895 +
1896 +static int
1897 +ramtd_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1898 +{
1899 + struct ra_nand_chip *ra = mtd->priv;
1900 + int ret;
1901 +
1902 + ra_dbg("%s: \n", __func__);
1903 + nand_get_device(ra, FL_WRITING);
1904 + ret = nand_block_markbad(ra, ofs);
1905 + nand_release_device(ra);
1906 +
1907 + return ret;
1908 +}
1909 +
1910 +// 1-bit error detection
1911 +static int one_bit_correction(char *ecc1, char *ecc2, int *bytes, int *bits)
1912 +{
1913 + // check if ecc and expected are all valid
1914 + char *p, nibble, crumb;
1915 + int i, xor, iecc1 = 0, iecc2 = 0;
1916 +
1917 + printk("correction : %x %x %x\n", ecc1[0], ecc1[1], ecc1[2]);
1918 + printk("correction : %x %x %x\n", ecc2[0], ecc2[1], ecc2[2]);
1919 +
1920 + p = (char *)ecc1;
1921 + for (i = 0; i < CONFIG_ECC_BYTES; i++)
1922 + {
1923 + nibble = *(p+i) & 0xf;
1924 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1925 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1926 + return -1;
1927 + nibble = ((*(p+i)) >> 4) & 0xf;
1928 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1929 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1930 + return -1;
1931 + }
1932 +
1933 + p = (char *)ecc2;
1934 + for (i = 0; i < CONFIG_ECC_BYTES; i++)
1935 + {
1936 + nibble = *(p+i) & 0xf;
1937 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1938 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1939 + return -1;
1940 + nibble = ((*(p+i)) >> 4) & 0xf;
1941 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1942 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1943 + return -1;
1944 + }
1945 +
1946 + memcpy(&iecc1, ecc1, 3);
1947 + memcpy(&iecc2, ecc2, 3);
1948 +
1949 + xor = iecc1 ^ iecc2;
1950 + printk("xor = %x (%x %x)\n", xor, iecc1, iecc2);
1951 +
1952 + *bytes = 0;
1953 + for (i = 0; i < 9; i++)
1954 + {
1955 + crumb = (xor >> (2*i)) & 0x3;
1956 + if ((crumb == 0x0) || (crumb == 0x3))
1957 + return -1;
1958 + if (crumb == 0x2)
1959 + *bytes += (1 << i);
1960 + }
1961 +
1962 + *bits = 0;
1963 + for (i = 0; i < 3; i++)
1964 + {
1965 + crumb = (xor >> (18 + 2*i)) & 0x3;
1966 + if ((crumb == 0x0) || (crumb == 0x3))
1967 + return -1;
1968 + if (crumb == 0x2)
1969 + *bits += (1 << i);
1970 + }
1971 +
1972 + return 0;
1973 +}
1974 +
1975 +
1976 +
1977 +/************************************************************
1978 + * the init/exit section.
1979 + */
1980 +
1981 +static struct nand_ecclayout ra_oob_layout = {
1982 + .eccbytes = CONFIG_ECC_BYTES,
1983 + .eccpos = {5, 6, 7},
1984 + .oobfree = {
1985 + {.offset = 0, .length = 4},
1986 + {.offset = 8, .length = 8},
1987 + {.offset = 0, .length = 0}
1988 + },
1989 +#define RA_CHIP_OOB_AVAIL (4+8)
1990 + .oobavail = RA_CHIP_OOB_AVAIL,
1991 + // 5th byte is bad-block flag.
1992 +};
1993 +
1994 +static int
1995 +mtk_nand_probe(struct platform_device *pdev)
1996 +{
1997 + struct mtd_part_parser_data ppdata;
1998 + struct ra_nand_chip *ra;
1999 + int alloc_size, bbt_size, buffers_size, reg, err;
2000 + unsigned char chip_mode = 12;
2001 +
2002 +/* if(ra_check_flash_type()!=BOOT_FROM_NAND) {
2003 + return 0;
2004 + }*/
2005 +
2006 + //FIXME: config 512 or 2048-byte page according to HWCONF
2007 +#if defined (CONFIG_RALINK_RT6855A)
2008 + reg = ra_inl(RALINK_SYSCTL_BASE+0x8c);
2009 + chip_mode = ((reg>>28) & 0x3)|(((reg>>22) & 0x3)<<2);
2010 + if (chip_mode == 1) {
2011 + printk("! nand 2048\n");
2012 + ra_or(NFC_CONF1, 1);
2013 + is_nand_page_2048 = 1;
2014 + nand_addrlen = 5;
2015 + }
2016 + else {
2017 + printk("! nand 512\n");
2018 + ra_and(NFC_CONF1, ~1);
2019 + is_nand_page_2048 = 0;
2020 + nand_addrlen = 4;
2021 + }
2022 +#elif (defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_RT6855))
2023 + ra_outl(RALINK_SYSCTL_BASE+0x60, ra_inl(RALINK_SYSCTL_BASE+0x60) & ~(0x3<<18));
2024 + reg = ra_inl(RALINK_SYSCTL_BASE+0x10);
2025 + chip_mode = (reg & 0x0F);
2026 + if((chip_mode==1)||(chip_mode==11)) {
2027 + ra_or(NFC_CONF1, 1);
2028 + is_nand_page_2048 = 1;
2029 + nand_addrlen = ((chip_mode!=11) ? 4 : 5);
2030 + printk("!!! nand page size = 2048, addr len=%d\n", nand_addrlen);
2031 + }
2032 + else {
2033 + ra_and(NFC_CONF1, ~1);
2034 + is_nand_page_2048 = 0;
2035 + nand_addrlen = ((chip_mode!=10) ? 3 : 4);
2036 + printk("!!! nand page size = 512, addr len=%d\n", nand_addrlen);
2037 + }
2038 +#else
2039 + is_nand_page_2048 = 0;
2040 + nand_addrlen = 3;
2041 + printk("!!! nand page size = 512, addr len=%d\n", nand_addrlen);
2042 +#endif
2043 +
2044 +#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_RT6855)
2045 + //config ECC location
2046 + ra_and(NFC_CONF1, 0xfff000ff);
2047 + ra_or(NFC_CONF1, ((CONFIG_ECC_OFFSET + 2) << 16) +
2048 + ((CONFIG_ECC_OFFSET + 1) << 12) +
2049 + (CONFIG_ECC_OFFSET << 8));
2050 +#endif
2051 +
2052 +#define ALIGNE_16(a) (((unsigned long)(a)+15) & ~15)
2053 + buffers_size = ALIGNE_16((1<<CONFIG_PAGE_SIZE_BIT) + (1<<CONFIG_OOBSIZE_PER_PAGE_BIT)); //ra->buffers
2054 + bbt_size = BBTTAG_BITS * (1<<(CONFIG_CHIP_SIZE_BIT - (CONFIG_PAGE_SIZE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT))) / 8; //ra->bbt
2055 + bbt_size = ALIGNE_16(bbt_size);
2056 +
2057 + alloc_size = buffers_size + bbt_size;
2058 + alloc_size += buffers_size; //for ra->readback_buffers
2059 + alloc_size += sizeof(*ra);
2060 + alloc_size += sizeof(*ranfc_mtd);
2061 +
2062 + //make sure gpio-0 is input
2063 + ra_outl(RALINK_PIO_BASE+0x24, ra_inl(RALINK_PIO_BASE+0x24) & ~0x01);
2064 +
2065 + ra = (struct ra_nand_chip *)kzalloc(alloc_size, GFP_KERNEL | GFP_DMA);
2066 + if (!ra) {
2067 + printk("%s: mem alloc fail \n", __func__);
2068 + return -ENOMEM;
2069 + }
2070 + memset(ra, 0, alloc_size);
2071 +
2072 + //dynamic
2073 + ra->buffers = (char *)((char *)ra + sizeof(*ra));
2074 + ra->readback_buffers = ra->buffers + buffers_size;
2075 + ra->bbt = ra->readback_buffers + buffers_size;
2076 + ranfc_mtd = (struct mtd_info *)(ra->bbt + bbt_size);
2077 +
2078 + //static
2079 + ra->numchips = CONFIG_NUMCHIPS;
2080 + ra->chip_shift = CONFIG_CHIP_SIZE_BIT;
2081 + ra->page_shift = CONFIG_PAGE_SIZE_BIT;
2082 + ra->oob_shift = CONFIG_OOBSIZE_PER_PAGE_BIT;
2083 + ra->erase_shift = (CONFIG_PAGE_SIZE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT);
2084 + ra->badblockpos = CONFIG_BAD_BLOCK_POS;
2085 + ra_oob_layout.eccpos[0] = CONFIG_ECC_OFFSET;
2086 + ra_oob_layout.eccpos[1] = CONFIG_ECC_OFFSET + 1;
2087 + ra_oob_layout.eccpos[2] = CONFIG_ECC_OFFSET + 2;
2088 + ra->oob = &ra_oob_layout;
2089 + ra->buffers_page = -1;
2090 +
2091 +#if defined (WORKAROUND_RX_BUF_OV)
2092 + if (ranfc_verify) {
2093 + ra->sandbox_page = nand_bbt_find_sandbox(ra);
2094 + }
2095 +#endif
2096 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x01); //set wp to high
2097 + nfc_all_reset();
2098 +
2099 + ranfc_mtd->type = MTD_NANDFLASH;
2100 + ranfc_mtd->flags = MTD_CAP_NANDFLASH;
2101 + ranfc_mtd->size = CONFIG_NUMCHIPS * CFG_CHIPSIZE;
2102 + ranfc_mtd->erasesize = CFG_BLOCKSIZE;
2103 + ranfc_mtd->writesize = CFG_PAGESIZE;
2104 + ranfc_mtd->oobsize = CFG_PAGE_OOBSIZE;
2105 + ranfc_mtd->oobavail = RA_CHIP_OOB_AVAIL;
2106 + ranfc_mtd->name = "ra_nfc";
2107 + //ranfc_mtd->index
2108 + ranfc_mtd->ecclayout = &ra_oob_layout;
2109 + //ranfc_mtd->numberaseregions
2110 + //ranfc_mtd->eraseregions
2111 + //ranfc_mtd->bansize
2112 + ranfc_mtd->_erase = ramtd_nand_erase;
2113 + //ranfc_mtd->point
2114 + //ranfc_mtd->unpoint
2115 + ranfc_mtd->_read = ramtd_nand_read;
2116 + ranfc_mtd->_write = ramtd_nand_write;
2117 + ranfc_mtd->_read_oob = ramtd_nand_readoob;
2118 + ranfc_mtd->_write_oob = ramtd_nand_writeoob;
2119 + //ranfc_mtd->get_fact_prot_info; ranfc_mtd->read_fact_prot_reg;
2120 + //ranfc_mtd->get_user_prot_info; ranfc_mtd->read_user_prot_reg;
2121 + //ranfc_mtd->write_user_prot_reg; ranfc_mtd->lock_user_prot_reg;
2122 + //ranfc_mtd->writev; ranfc_mtd->sync; ranfc_mtd->lock; ranfc_mtd->unlock; ranfc_mtd->suspend; ranfc_mtd->resume;
2123 + ranfc_mtd->_block_isbad = ramtd_nand_block_isbad;
2124 + ranfc_mtd->_block_markbad = ramtd_nand_block_markbad;
2125 + //ranfc_mtd->reboot_notifier
2126 + //ranfc_mtd->ecc_stats;
2127 + // subpage_sht;
2128 +
2129 + //ranfc_mtd->get_device; ranfc_mtd->put_device
2130 + ranfc_mtd->priv = ra;
2131 +
2132 + ranfc_mtd->owner = THIS_MODULE;
2133 + ra->controller = &ra->hwcontrol;
2134 + mutex_init(ra->controller);
2135 +
2136 + printk("%s: alloc %x, at %p , btt(%p, %x), ranfc_mtd:%p\n",
2137 + __func__ , alloc_size, ra, ra->bbt, bbt_size, ranfc_mtd);
2138 +
2139 + ppdata.of_node = pdev->dev.of_node;
2140 + err = mtd_device_parse_register(ranfc_mtd, mtk_probe_types,
2141 + &ppdata, NULL, 0);
2142 +
2143 + return err;
2144 +}
2145 +
2146 +static int
2147 +mtk_nand_remove(struct platform_device *pdev)
2148 +{
2149 + struct ra_nand_chip *ra;
2150 +
2151 + if (ranfc_mtd) {
2152 + ra = (struct ra_nand_chip *)ranfc_mtd->priv;
2153 +
2154 + /* Deregister partitions */
2155 + //del_mtd_partitions(ranfc_mtd);
2156 + kfree(ra);
2157 + }
2158 + return 0;
2159 +}
2160 +
2161 +static const struct of_device_id mtk_nand_match[] = {
2162 + { .compatible = "mtk,mt7620-nand" },
2163 + {},
2164 +};
2165 +MODULE_DEVICE_TABLE(of, mtk_nand_match);
2166 +
2167 +static struct platform_driver mtk_nand_driver = {
2168 + .probe = mtk_nand_probe,
2169 + .remove = mtk_nand_remove,
2170 + .driver = {
2171 + .name = "mt7620_nand",
2172 + .owner = THIS_MODULE,
2173 + .of_match_table = mtk_nand_match,
2174 + },
2175 +};
2176 +
2177 +module_platform_driver(mtk_nand_driver);
2178 +
2179 +
2180 +MODULE_LICENSE("GPL");
2181 diff --git a/drivers/mtd/maps/ralink_nand.h b/drivers/mtd/maps/ralink_nand.h
2182 new file mode 100644
2183 index 0000000..a408ae9
2184 --- /dev/null
2185 +++ b/drivers/mtd/maps/ralink_nand.h
2186 @@ -0,0 +1,232 @@
2187 +#ifndef RT2880_NAND_H
2188 +#define RT2880_NAND_H
2189 +
2190 +#include <linux/mtd/mtd.h>
2191 +
2192 +//#include "gdma.h"
2193 +
2194 +#define RALINK_SYSCTL_BASE 0xB0000000
2195 +#define RALINK_PIO_BASE 0xB0000600
2196 +#define RALINK_NAND_CTRL_BASE 0xB0000810
2197 +#define CONFIG_RALINK_MT7620
2198 +
2199 +#define SKIP_BAD_BLOCK
2200 +//#define RANDOM_GEN_BAD_BLOCK
2201 +
2202 +#define ra_inl(addr) (*(volatile unsigned int *)(addr))
2203 +#define ra_outl(addr, value) (*(volatile unsigned int *)(addr) = (value))
2204 +#define ra_aor(addr, a_mask, o_value) ra_outl(addr, (ra_inl(addr) & (a_mask)) | (o_value))
2205 +#define ra_and(addr, a_mask) ra_aor(addr, a_mask, 0)
2206 +#define ra_or(addr, o_value) ra_aor(addr, -1, o_value)
2207 +
2208 +
2209 +#define CONFIG_NUMCHIPS 1
2210 +#define CONFIG_NOT_SUPPORT_WP //rt3052 has no WP signal for chip.
2211 +//#define CONFIG_NOT_SUPPORT_RB
2212 +
2213 +extern int is_nand_page_2048;
2214 +extern const unsigned int nand_size_map[2][3];
2215 +
2216 +//chip
2217 +// chip geometry: SAMSUNG small size 32MB.
2218 +#define CONFIG_CHIP_SIZE_BIT (nand_size_map[is_nand_page_2048][nand_addrlen-3]) //! (1<<NAND_SIZE_BYTE) MB
2219 +//#define CONFIG_CHIP_SIZE_BIT (is_nand_page_2048? 29 : 25) //! (1<<NAND_SIZE_BYTE) MB
2220 +#define CONFIG_PAGE_SIZE_BIT (is_nand_page_2048? 11 : 9) //! (1<<PAGE_SIZE) MB
2221 +//#define CONFIG_SUBPAGE_BIT 1 //! these bits will be compensate by command cycle
2222 +#define CONFIG_NUMPAGE_PER_BLOCK_BIT (is_nand_page_2048? 6 : 5) //! order of number of pages a block.
2223 +#define CONFIG_OOBSIZE_PER_PAGE_BIT (is_nand_page_2048? 6 : 4) //! byte number of oob a page.
2224 +#define CONFIG_BAD_BLOCK_POS (is_nand_page_2048? 0 : 4) //! offset of byte to denote bad block.
2225 +#define CONFIG_ECC_BYTES 3 //! ecc has 3 bytes
2226 +#define CONFIG_ECC_OFFSET (is_nand_page_2048? 6 : 5) //! ecc starts from offset 5.
2227 +
2228 +//this section should not be modified.
2229 +//#define CFG_COLUMN_ADDR_MASK ((1 << (CONFIG_PAGE_SIZE_BIT - CONFIG_SUBPAGE_BIT)) - 1)
2230 +//#define CFG_COLUMN_ADDR_CYCLE (((CONFIG_PAGE_SIZE_BIT - CONFIG_SUBPAGE_BIT) + 7)/8)
2231 +//#define CFG_ROW_ADDR_CYCLE ((CONFIG_CHIP_SIZE_BIT - CONFIG_PAGE_SIZE_BIT + 7)/8)
2232 +//#define CFG_ADDR_CYCLE (CFG_COLUMN_ADDR_CYCLE + CFG_ROW_ADDR_CYCLE)
2233 +
2234 +#define CFG_COLUMN_ADDR_CYCLE (is_nand_page_2048? 2 : 1)
2235 +#define CFG_ROW_ADDR_CYCLE (nand_addrlen - CFG_COLUMN_ADDR_CYCLE)
2236 +#define CFG_ADDR_CYCLE (CFG_COLUMN_ADDR_CYCLE + CFG_ROW_ADDR_CYCLE)
2237 +
2238 +#define CFG_CHIPSIZE (1 << ((CONFIG_CHIP_SIZE_BIT>=32)? 31 : CONFIG_CHIP_SIZE_BIT))
2239 +//#define CFG_CHIPSIZE (1 << CONFIG_CHIP_SIZE_BIT)
2240 +#define CFG_PAGESIZE (1 << CONFIG_PAGE_SIZE_BIT)
2241 +#define CFG_BLOCKSIZE (CFG_PAGESIZE << CONFIG_NUMPAGE_PER_BLOCK_BIT)
2242 +#define CFG_NUMPAGE (1 << (CONFIG_CHIP_SIZE_BIT - CONFIG_PAGE_SIZE_BIT))
2243 +#define CFG_NUMBLOCK (CFG_NUMPAGE >> CONFIG_NUMPAGE_PER_BLOCK_BIT)
2244 +#define CFG_BLOCK_OOBSIZE (1 << (CONFIG_OOBSIZE_PER_PAGE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT))
2245 +#define CFG_PAGE_OOBSIZE (1 << CONFIG_OOBSIZE_PER_PAGE_BIT)
2246 +
2247 +#define NAND_BLOCK_ALIGN(addr) ((addr) & (CFG_BLOCKSIZE-1))
2248 +#define NAND_PAGE_ALIGN(addr) ((addr) & (CFG_PAGESIZE-1))
2249 +
2250 +
2251 +#define NFC_BASE RALINK_NAND_CTRL_BASE
2252 +#define NFC_CTRL (NFC_BASE + 0x0)
2253 +#define NFC_CONF (NFC_BASE + 0x4)
2254 +#define NFC_CMD1 (NFC_BASE + 0x8)
2255 +#define NFC_CMD2 (NFC_BASE + 0xc)
2256 +#define NFC_CMD3 (NFC_BASE + 0x10)
2257 +#define NFC_ADDR (NFC_BASE + 0x14)
2258 +#define NFC_DATA (NFC_BASE + 0x18)
2259 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
2260 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
2261 +#define NFC_ECC (NFC_BASE + 0x30)
2262 +#else
2263 +#define NFC_ECC (NFC_BASE + 0x1c)
2264 +#endif
2265 +#define NFC_STATUS (NFC_BASE + 0x20)
2266 +#define NFC_INT_EN (NFC_BASE + 0x24)
2267 +#define NFC_INT_ST (NFC_BASE + 0x28)
2268 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
2269 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
2270 +#define NFC_CONF1 (NFC_BASE + 0x2c)
2271 +#define NFC_ECC_P1 (NFC_BASE + 0x30)
2272 +#define NFC_ECC_P2 (NFC_BASE + 0x34)
2273 +#define NFC_ECC_P3 (NFC_BASE + 0x38)
2274 +#define NFC_ECC_P4 (NFC_BASE + 0x3c)
2275 +#define NFC_ECC_ERR1 (NFC_BASE + 0x40)
2276 +#define NFC_ECC_ERR2 (NFC_BASE + 0x44)
2277 +#define NFC_ECC_ERR3 (NFC_BASE + 0x48)
2278 +#define NFC_ECC_ERR4 (NFC_BASE + 0x4c)
2279 +#define NFC_ADDR2 (NFC_BASE + 0x50)
2280 +#endif
2281 +
2282 +enum _int_stat {
2283 + INT_ST_ND_DONE = 1<<0,
2284 + INT_ST_TX_BUF_RDY = 1<<1,
2285 + INT_ST_RX_BUF_RDY = 1<<2,
2286 + INT_ST_ECC_ERR = 1<<3,
2287 + INT_ST_TX_TRAS_ERR = 1<<4,
2288 + INT_ST_RX_TRAS_ERR = 1<<5,
2289 + INT_ST_TX_KICK_ERR = 1<<6,
2290 + INT_ST_RX_KICK_ERR = 1<<7
2291 +};
2292 +
2293 +
2294 +//#define WORKAROUND_RX_BUF_OV 1
2295 +
2296 +
2297 +/*************************************************************
2298 + * stolen from nand.h
2299 + *************************************************************/
2300 +
2301 +/*
2302 + * Standard NAND flash commands
2303 + */
2304 +#define NAND_CMD_READ0 0
2305 +#define NAND_CMD_READ1 1
2306 +#define NAND_CMD_RNDOUT 5
2307 +#define NAND_CMD_PAGEPROG 0x10
2308 +#define NAND_CMD_READOOB 0x50
2309 +#define NAND_CMD_ERASE1 0x60
2310 +#define NAND_CMD_STATUS 0x70
2311 +#define NAND_CMD_STATUS_MULTI 0x71
2312 +#define NAND_CMD_SEQIN 0x80
2313 +#define NAND_CMD_RNDIN 0x85
2314 +#define NAND_CMD_READID 0x90
2315 +#define NAND_CMD_ERASE2 0xd0
2316 +#define NAND_CMD_RESET 0xff
2317 +
2318 +/* Extended commands for large page devices */
2319 +#define NAND_CMD_READSTART 0x30
2320 +#define NAND_CMD_RNDOUTSTART 0xE0
2321 +#define NAND_CMD_CACHEDPROG 0x15
2322 +
2323 +/* Extended commands for AG-AND device */
2324 +/*
2325 + * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
2326 + * there is no way to distinguish that from NAND_CMD_READ0
2327 + * until the remaining sequence of commands has been completed
2328 + * so add a high order bit and mask it off in the command.
2329 + */
2330 +#define NAND_CMD_DEPLETE1 0x100
2331 +#define NAND_CMD_DEPLETE2 0x38
2332 +#define NAND_CMD_STATUS_MULTI 0x71
2333 +#define NAND_CMD_STATUS_ERROR 0x72
2334 +/* multi-bank error status (banks 0-3) */
2335 +#define NAND_CMD_STATUS_ERROR0 0x73
2336 +#define NAND_CMD_STATUS_ERROR1 0x74
2337 +#define NAND_CMD_STATUS_ERROR2 0x75
2338 +#define NAND_CMD_STATUS_ERROR3 0x76
2339 +#define NAND_CMD_STATUS_RESET 0x7f
2340 +#define NAND_CMD_STATUS_CLEAR 0xff
2341 +
2342 +#define NAND_CMD_NONE -1
2343 +
2344 +/* Status bits */
2345 +#define NAND_STATUS_FAIL 0x01
2346 +#define NAND_STATUS_FAIL_N1 0x02
2347 +#define NAND_STATUS_TRUE_READY 0x20
2348 +#define NAND_STATUS_READY 0x40
2349 +#define NAND_STATUS_WP 0x80
2350 +
2351 +typedef enum {
2352 + FL_READY,
2353 + FL_READING,
2354 + FL_WRITING,
2355 + FL_ERASING,
2356 + FL_SYNCING,
2357 + FL_CACHEDPRG,
2358 + FL_PM_SUSPENDED,
2359 +} nand_state_t;
2360 +
2361 +/*************************************************************/
2362 +
2363 +
2364 +
2365 +typedef enum _ra_flags {
2366 + FLAG_NONE = 0,
2367 + FLAG_ECC_EN = (1<<0),
2368 + FLAG_USE_GDMA = (1<<1),
2369 + FLAG_VERIFY = (1<<2),
2370 +} RA_FLAGS;
2371 +
2372 +
2373 +#define BBTTAG_BITS 2
2374 +#define BBTTAG_BITS_MASK ((1<<BBTTAG_BITS) -1)
2375 +enum BBT_TAG {
2376 + BBT_TAG_UNKNOWN = 0, //2'b01
2377 + BBT_TAG_GOOD = 3, //2'b11
2378 + BBT_TAG_BAD = 2, //2'b10
2379 + BBT_TAG_RES = 1, //2'b01
2380 +};
2381 +
2382 +struct ra_nand_chip {
2383 + int numchips;
2384 + int chip_shift;
2385 + int page_shift;
2386 + int erase_shift;
2387 + int oob_shift;
2388 + int badblockpos;
2389 +#if !defined (__UBOOT__)
2390 + struct mutex hwcontrol;
2391 + struct mutex *controller;
2392 +#endif
2393 + struct nand_ecclayout *oob;
2394 + int state;
2395 + unsigned int buffers_page;
2396 + char *buffers; //[CFG_PAGESIZE + CFG_PAGE_OOBSIZE];
2397 + char *readback_buffers;
2398 + unsigned char *bbt;
2399 +#if defined (WORKAROUND_RX_BUF_OV)
2400 + unsigned int sandbox_page; // steal a page (block) for read ECC verification
2401 +#endif
2402 +
2403 +};
2404 +
2405 +
2406 +
2407 +//fixme, gdma api
2408 +int nand_dma_sync(void);
2409 +void release_dma_buf(void);
2410 +int set_gdma_ch(unsigned long dst,
2411 + unsigned long src, unsigned int len, int burst_size,
2412 + int soft_mode, int src_req_type, int dst_req_type,
2413 + int src_burst_mode, int dst_burst_mode);
2414 +
2415 +
2416 +
2417 +
2418 +#endif
2419 --
2420 1.7.10.4
2421
OpenWrt Source Repository