ramips: backport series of patches that ensure GCRs of other CPUs are accessed properly
[openwrt/openwrt.git] / target / linux / ramips / patches-4.3 / 0044-i2c-MIPS-adds-ralink-I2C-driver.patch
1 From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:52:56 +0100
4 Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
9 drivers/i2c/busses/Kconfig | 4 +
10 drivers/i2c/busses/Makefile | 1 +
11 drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++
12 4 files changed, 359 insertions(+)
13 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
14 create mode 100644 drivers/i2c/busses/i2c-ralink.c
15
16 diff --git a/Documentation/devicetree/bindings/i2c/i2c-ralink.txt b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
17 new file mode 100644
18 index 0000000..8fa8ac3
19 --- /dev/null
20 +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
21 @@ -0,0 +1,27 @@
22 +I2C for Ralink platforms
23 +
24 +Required properties :
25 +- compatible : Must be "link,rt3052-i2c"
26 +- reg: physical base address of the controller and length of memory mapped
27 + region.
28 +- #address-cells = <1>;
29 +- #size-cells = <0>;
30 +
31 +Optional properties:
32 +- Child nodes conforming to i2c bus binding
33 +
34 +Example :
35 +
36 +palmbus@10000000 {
37 + i2c@900 {
38 + compatible = "link,rt3052-i2c";
39 + reg = <0x900 0x100>;
40 + #address-cells = <1>;
41 + #size-cells = <0>;
42 +
43 + hwmon@4b {
44 + compatible = "national,lm92";
45 + reg = <0x4b>;
46 + };
47 + };
48 +};
49 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
50 index 08b8617..53d565b 100644
51 --- a/drivers/i2c/busses/Kconfig
52 +++ b/drivers/i2c/busses/Kconfig
53 @@ -803,6 +803,10 @@ config I2C_RK3X
54 This driver can also be built as a module. If so, the module will
55 be called i2c-rk3x.
56
57 +config I2C_RALINK
58 + tristate "Ralink I2C Controller"
59 + select OF_I2C
60 +
61 config HAVE_S3C2410_I2C
62 bool
63 help
64 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
65 index 6df3b30..2edd32c 100644
66 --- a/drivers/i2c/busses/Makefile
67 +++ b/drivers/i2c/busses/Makefile
68 @@ -75,6 +75,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
69 obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
70 obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
71 obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
72 +obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
73 obj-$(CONFIG_I2C_QUP) += i2c-qup.o
74 obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
75 obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
76 diff --git a/drivers/i2c/busses/i2c-ralink.c b/drivers/i2c/busses/i2c-ralink.c
77 new file mode 100644
78 index 0000000..debfb18
79 --- /dev/null
80 +++ b/drivers/i2c/busses/i2c-ralink.c
81 @@ -0,0 +1,327 @@
82 +/*
83 + * drivers/i2c/busses/i2c-ralink.c
84 + *
85 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
86 + *
87 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
88 + * (C) 2014 Sittisak <sittisaks@hotmail.com>
89 + *
90 + * This software is licensed under the terms of the GNU General Public
91 + * License version 2, as published by the Free Software Foundation, and
92 + * may be copied, distributed, and modified under those terms.
93 + *
94 + * This program is distributed in the hope that it will be useful,
95 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
96 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
97 + * GNU General Public License for more details.
98 + *
99 + */
100 +
101 +#include <linux/interrupt.h>
102 +#include <linux/kernel.h>
103 +#include <linux/module.h>
104 +#include <linux/reset.h>
105 +#include <linux/delay.h>
106 +#include <linux/slab.h>
107 +#include <linux/init.h>
108 +#include <linux/errno.h>
109 +#include <linux/platform_device.h>
110 +#include <linux/of_platform.h>
111 +#include <linux/i2c.h>
112 +#include <linux/io.h>
113 +#include <linux/err.h>
114 +
115 +#include <asm/mach-ralink/ralink_regs.h>
116 +
117 +#define REG_CONFIG_REG 0x00
118 +#define REG_CLKDIV_REG 0x04
119 +#define REG_DEVADDR_REG 0x08
120 +#define REG_ADDR_REG 0x0C
121 +#define REG_DATAOUT_REG 0x10
122 +#define REG_DATAIN_REG 0x14
123 +#define REG_STATUS_REG 0x18
124 +#define REG_STARTXFR_REG 0x1C
125 +#define REG_BYTECNT_REG 0x20
126 +#define REG_SM0CFG2 0x28
127 +#define REG_SM0CTL0 0x40
128 +
129 +#define I2C_STARTERR BIT(4)
130 +#define I2C_ACKERR BIT(3)
131 +#define I2C_DATARDY BIT(2)
132 +#define I2C_SDOEMPTY BIT(1)
133 +#define I2C_BUSY BIT(0)
134 +
135 +#define I2C_DEVADLEN_7 (6 << 2)
136 +#define I2C_ADDRDIS BIT(1)
137 +
138 +#define CLKDIV_VALUE 200 // clock rate is 40M, 40M / (200*2) = 100k (standard i2c bus rate).
139 +//#define CLKDIV_VALUE 50 // clock rate is 40M, 40M / (50*2) = 400k (fast i2c bus rate).
140 +
141 +#define READ_CMD 0x01
142 +#define WRITE_CMD 0x00
143 +#define READ_BLOCK 64
144 +
145 +#define SM0CTL0_OD BIT(31)
146 +#define SM0CTL0_VTRIG BIT(28)
147 +#define SM0CTL0_OUTHI BIT(6)
148 +#define SM0CTL0_STRETCH BIT(1)
149 +#define SM0CTL0_DEFAULT (SM0CTL0_OD | SM0CTL0_VTRIG | SM0CTL0_OUTHI | SM0CTL0_STRETCH)
150 +
151 +/* timeout waiting for I2C devices to respond (clock streching) */
152 +#define RT_I2C_TIMEOUT (msecs_to_jiffies(1000))
153 +
154 +enum {
155 + I2C_TYPE_RALINK,
156 + I2C_TYPE_MEDIATEK,
157 +};
158 +
159 +static void __iomem *membase;
160 +static struct i2c_adapter *adapter;
161 +static int hw_type;
162 +
163 +static void rt_i2c_w32(u32 val, unsigned reg)
164 +{
165 + iowrite32(val, membase + reg);
166 +}
167 +
168 +static u32 rt_i2c_r32(unsigned reg)
169 +{
170 + return ioread32(membase + reg);
171 +}
172 +
173 +static inline int rt_i2c_get_ack(void)
174 +{
175 + return (rt_i2c_r32(REG_STATUS_REG) & I2C_ACKERR) ? -EIO : 0;
176 +}
177 +
178 +static inline int rt_i2c_wait_rx_done(void)
179 +{
180 + unsigned long timeout;
181 +
182 + timeout = jiffies + RT_I2C_TIMEOUT;
183 +
184 + do {
185 + if (time_after(jiffies, timeout))
186 + return (-ETIMEDOUT);
187 +
188 + } while (!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY));
189 +
190 + return 0;
191 +}
192 +
193 +static inline int rt_i2c_wait_idle(void)
194 +{
195 + unsigned long timeout;
196 +
197 + timeout = jiffies + RT_I2C_TIMEOUT;
198 +
199 + do {
200 + if (time_after(jiffies, timeout)) {
201 + printk("i2c-read line busy\n");
202 + return 1;
203 + }
204 + } while (rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY);
205 +
206 + return 0;
207 +}
208 +
209 +static inline int rt_i2c_wait_tx_done(void)
210 +{
211 + unsigned long timeout;
212 +
213 + timeout = jiffies + RT_I2C_TIMEOUT;
214 +
215 + do {
216 + if (time_after(jiffies, timeout))
217 + return (-ETIMEDOUT);
218 +
219 + } while (!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY));
220 +
221 + return 0;
222 +}
223 +
224 +static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
225 +{
226 + int i = 0, j = 0, pos = 0;
227 + int nblock = msg->len / READ_BLOCK;
228 + int rem = msg->len % READ_BLOCK;
229 + int ret = 0;
230 +
231 + if (msg->flags & I2C_M_TEN) {
232 + printk("10 bits addr not supported\n");
233 + return -EINVAL;
234 + }
235 +
236 + if (msg->flags & I2C_M_RD) {
237 + for (i = 0; i < nblock; i++) {
238 + if (rt_i2c_wait_idle())
239 + return -ETIMEDOUT;
240 + rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
241 + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
242 + for (j = 0; j < READ_BLOCK; j++) {
243 + if (rt_i2c_wait_rx_done() < 0)
244 + ret = rt_i2c_wait_rx_done();
245 + if (rt_i2c_get_ack() < 0)
246 + ret = rt_i2c_get_ack();
247 + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
248 + }
249 + }
250 +
251 + if (rt_i2c_wait_idle())
252 + return -ETIMEDOUT;
253 + if (rem) {
254 + rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
255 + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
256 + }
257 + for (i = 0; i < rem; i++) {
258 + if (rt_i2c_wait_rx_done() < 0)
259 + ret = rt_i2c_wait_rx_done();
260 + if (rt_i2c_get_ack() < 0)
261 + ret = rt_i2c_get_ack();
262 +
263 + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
264 + }
265 + } else {
266 + if (rt_i2c_wait_idle())
267 + return -ETIMEDOUT;
268 + rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
269 + for (i = 0; i < msg->len; i++) {
270 + rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
271 + rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
272 +
273 + if (rt_i2c_wait_tx_done() < 0)
274 + ret = rt_i2c_wait_tx_done();
275 + if (rt_i2c_get_ack() < 0)
276 + ret = rt_i2c_get_ack();
277 + }
278 + }
279 +
280 + return ret;
281 +}
282 +
283 +static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
284 +{
285 + int i = 0;
286 + int ret = 0;
287 +
288 + if (rt_i2c_wait_idle())
289 + return -ETIMEDOUT;
290 +
291 + device_reset(a->dev.parent);
292 +
293 + rt_i2c_w32(m->addr, REG_DEVADDR_REG);
294 + rt_i2c_w32(I2C_DEVADLEN_7 | I2C_ADDRDIS, REG_CONFIG_REG);
295 + if (hw_type == I2C_TYPE_RALINK) {
296 + rt_i2c_w32(CLKDIV_VALUE, REG_CLKDIV_REG);
297 + } else {
298 + rt_i2c_w32((CLKDIV_VALUE << 16) | SM0CTL0_DEFAULT, REG_SM0CTL0);
299 + rt_i2c_w32(1, REG_SM0CFG2);
300 + }
301 +
302 + for (i = 0; i < n && !ret; i++) {
303 + ret = rt_i2c_handle_msg(a, &m[i]);
304 +
305 + if (ret < 0) {
306 + return ret;
307 + }
308 + }
309 +
310 + return n;
311 +}
312 +
313 +static u32 rt_i2c_func(struct i2c_adapter *a)
314 +{
315 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
316 +}
317 +
318 +static const struct i2c_algorithm rt_i2c_algo = {
319 + .master_xfer = rt_i2c_master_xfer,
320 + .functionality = rt_i2c_func,
321 +};
322 +
323 +static const struct of_device_id i2c_rt_dt_ids[] = {
324 + { .compatible = "ralink,rt2880-i2c", .data = (void *) I2C_TYPE_RALINK },
325 + { .compatible = "mediatek,mt7628-i2c", .data = (void *) I2C_TYPE_MEDIATEK },
326 + { /* sentinel */ }
327 +};
328 +
329 +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
330 +
331 +static int rt_i2c_probe(struct platform_device *pdev)
332 +{
333 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
334 + const struct of_device_id *match;
335 + int ret;
336 +
337 + match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
338 + hw_type = (int) match->data;
339 +
340 + if (!res) {
341 + dev_err(&pdev->dev, "no memory resource found\n");
342 + return -ENODEV;
343 + }
344 +
345 + adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), GFP_KERNEL);
346 + if (!adapter) {
347 + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
348 + return -ENOMEM;
349 + }
350 +
351 + membase = devm_ioremap_resource(&pdev->dev, res);
352 + if (IS_ERR(membase))
353 + return PTR_ERR(membase);
354 +
355 + strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
356 + adapter->owner = THIS_MODULE;
357 + adapter->nr = pdev->id;
358 + adapter->timeout = HZ;
359 + adapter->algo = &rt_i2c_algo;
360 + adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
361 + adapter->dev.parent = &pdev->dev;
362 + adapter->dev.of_node = pdev->dev.of_node;
363 +
364 + ret = i2c_add_numbered_adapter(adapter);
365 + if (ret)
366 + return ret;
367 +
368 + platform_set_drvdata(pdev, adapter);
369 +
370 + dev_info(&pdev->dev, "loaded\n");
371 +
372 + return 0;
373 +}
374 +
375 +static int rt_i2c_remove(struct platform_device *pdev)
376 +{
377 + platform_set_drvdata(pdev, NULL);
378 +
379 + return 0;
380 +}
381 +
382 +static struct platform_driver rt_i2c_driver = {
383 + .probe = rt_i2c_probe,
384 + .remove = rt_i2c_remove,
385 + .driver = {
386 + .owner = THIS_MODULE,
387 + .name = "i2c-ralink",
388 + .of_match_table = i2c_rt_dt_ids,
389 + },
390 +};
391 +
392 +static int __init i2c_rt_init (void)
393 +{
394 + return platform_driver_register(&rt_i2c_driver);
395 +}
396 +subsys_initcall(i2c_rt_init);
397 +
398 +static void __exit i2c_rt_exit (void)
399 +{
400 + platform_driver_unregister(&rt_i2c_driver);
401 +}
402 +
403 +module_exit (i2c_rt_exit);
404 +
405 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
406 +MODULE_DESCRIPTION("Ralink I2c host driver");
407 +MODULE_LICENSE("GPL");
408 +MODULE_ALIAS("platform:Ralink-I2C");
409 --
410 1.7.10.4
411