target/linux/ramips/patches-4.4/0001-arch-mips-ralink-add-mt7621-support.patch

   1 From 450b6e8257e22708173d0c1c86d34394fba0c5eb Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:08:31 +0100
   4 Subject: [PATCH 01/53] arch: mips: ralink: add mt7621 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-ralink/irq.h    |    9 +
   9  arch/mips/include/asm/mach-ralink/mt7621.h |   39 ++++
  10  arch/mips/kernel/mips-cm.c                 |    4 +-
  11  arch/mips/kernel/vmlinux.lds.S             |    1 +
  12  arch/mips/ralink/Kconfig                   |   18 ++
  13  arch/mips/ralink/Makefile                  |    7 +-
  14  arch/mips/ralink/Platform                  |    5 +
  15  arch/mips/ralink/irq-gic.c                 |  268 ++++++++++++++++++++++++++++
  16  arch/mips/ralink/malta-amon.c              |   81 +++++++++
  17  arch/mips/ralink/mt7621.c                  |  209 ++++++++++++++++++++++
  18  10 files changed, 638 insertions(+), 3 deletions(-)
  19  create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
  20  create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
  21  create mode 100644 arch/mips/ralink/irq-gic.c
  22  create mode 100644 arch/mips/ralink/malta-amon.c
  23  create mode 100644 arch/mips/ralink/mt7621.c
  24
  25 --- /dev/null
  26 +++ b/arch/mips/include/asm/mach-ralink/irq.h
  27 @@ -0,0 +1,9 @@
  28 +#ifndef __ASM_MACH_RALINK_IRQ_H
  29 +#define __ASM_MACH_RALINK_IRQ_H
  30 +
  31 +#define GIC_NUM_INTRS  64
  32 +#define NR_IRQS 256
  33 +
  34 +#include_next <irq.h>
  35 +
  36 +#endif
  37 --- /dev/null
  38 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
  39 @@ -0,0 +1,42 @@
  40 +/*
  41 + * This program is free software; you can redistribute it and/or modify it
  42 + * under the terms of the GNU General Public License version 2 as published
  43 + * by the Free Software Foundation.
  44 + *
  45 + * Parts of this file are based on Ralink's 2.6.21 BSP
  46 + *
  47 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  48 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  49 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  50 + */
  51 +
  52 +#ifndef _MT7621_REGS_H_
  53 +#define _MT7621_REGS_H_
  54 +
  55 +#define MT7621_PALMBUS_BASE            0x1C000000
  56 +#define MT7621_PALMBUS_SIZE            0x03FFFFFF
  57 +
  58 +#define MT7621_SYSC_BASE               0x1E000000
  59 +
  60 +#define SYSC_REG_CHIP_NAME0            0x00
  61 +#define SYSC_REG_CHIP_NAME1            0x04
  62 +#define SYSC_REG_CHIP_REV              0x0c
  63 +#define SYSC_REG_SYSTEM_CONFIG0                0x10
  64 +#define SYSC_REG_SYSTEM_CONFIG1                0x14
  65 +
  66 +#define CHIP_REV_PKG_MASK              0x1
  67 +#define CHIP_REV_PKG_SHIFT             16
  68 +#define CHIP_REV_VER_MASK              0xf
  69 +#define CHIP_REV_VER_SHIFT             8
  70 +#define CHIP_REV_ECO_MASK              0xf
  71 +
  72 +#define MT7621_DRAM_BASE                0x0
  73 +#define MT7621_DDR2_SIZE_MIN           32
  74 +#define MT7621_DDR2_SIZE_MAX           256
  75 +
  76 +#define MT7621_CHIP_NAME0              0x3637544D
  77 +#define MT7621_CHIP_NAME1              0x20203132
  78 +
  79 +#define MIPS_GIC_IRQ_BASE           (MIPS_CPU_IRQ_BASE + 8)
  80 +
  81 +#endif
  82 --- a/arch/mips/kernel/vmlinux.lds.S
  83 +++ b/arch/mips/kernel/vmlinux.lds.S
  84 @@ -53,6 +53,7 @@ SECTIONS
  85         /* read-only */
  86         _text = .;      /* Text and read-only data */
  87         .text : {
  88 +               /*. = . + 0x8000; */
  89                 TEXT_TEXT
  90                 SCHED_TEXT
  91                 LOCK_TEXT
  92 --- a/arch/mips/ralink/Kconfig
  93 +++ b/arch/mips/ralink/Kconfig
  94 @@ -12,6 +12,11 @@ config RALINK_ILL_ACC
  95         depends on SOC_RT305X
  96         default y
  97
  98 +config IRQ_INTC
  99 +       bool
 100 +       default y
 101 +       depends on !SOC_MT7621
 102 +
 103  choice
 104         prompt "Ralink SoC selection"
 105         default SOC_RT305X
 106 @@ -34,6 +39,16 @@ choice
 107         config SOC_MT7620
 108                 bool "MT7620/8"
 109
 110 +       config SOC_MT7621
 111 +               bool "MT7621"
 112 +               select MIPS_CPU_SCACHE
 113 +               select SYS_SUPPORTS_MULTITHREADING
 114 +               select SYS_SUPPORTS_SMP
 115 +               select SYS_SUPPORTS_MIPS_CPS
 116 +               select MIPS_GIC
 117 +               select COMMON_CLK
 118 +               select CLKSRC_MIPS_GIC
 119 +               select HW_HAS_PCI
 120  endchoice
 121
 122  choice
 123 @@ -65,6 +80,10 @@ choice
 124                 depends on SOC_MT7620
 125                 select BUILTIN_DTB
 126
 127 +       config DTB_MT7621_EVAL
 128 +               bool "MT7621 eval kit"
 129 +               depends on SOC_MT7621
 130 +
 131  endchoice
 132
 133  endif
 134 --- a/arch/mips/ralink/Makefile
 135 +++ b/arch/mips/ralink/Makefile
 136 @@ -6,16 +6,24 @@
 137  # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 138  # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 139
 140 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
 141 +obj-y := prom.o of.o reset.o
 142 +
 143 +ifndef CONFIG_MIPS_GIC
 144 +       obj-y += clk.o timer.o
 145 +endif
 146
 147  obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
 148
 149  obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
 150
 151 +obj-$(CONFIG_IRQ_INTC) += irq.o
 152 +obj-$(CONFIG_MIPS_GIC) += irq-gic.o timer-gic.o
 153 +
 154  obj-$(CONFIG_SOC_RT288X) += rt288x.o
 155  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 156  obj-$(CONFIG_SOC_RT3883) += rt3883.o
 157  obj-$(CONFIG_SOC_MT7620) += mt7620.o
 158 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
 159
 160  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 161
 162 --- a/arch/mips/ralink/Platform
 163 +++ b/arch/mips/ralink/Platform
 164 @@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883)   += -I$(srctr
 165  #
 166  load-$(CONFIG_SOC_MT7620)      += 0xffffffff80000000
 167  cflags-$(CONFIG_SOC_MT7620)    += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
 168 +
 169 +# Ralink MT7621
 170 +#
 171 +load-$(CONFIG_SOC_MT7621)      += 0xffffffff80001000
 172 +cflags-$(CONFIG_SOC_MT7621)    += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
 173 --- /dev/null
 174 +++ b/arch/mips/ralink/irq-gic.c
 175 @@ -0,0 +1,18 @@
 176 +#include <linux/init.h>
 177 +
 178 +#include <linux/of.h>
 179 +#include <linux/irqchip.h>
 180 +#include <linux/irqchip/mips-gic.h>
 181 +
 182 +int get_c0_perfcount_int(void)
 183 +{
 184 +       return gic_get_c0_perfcount_int();
 185 +}
 186 +EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
 187 +
 188 +void __init
 189 +arch_init_irq(void)
 190 +{
 191 +       irqchip_init();
 192 +}
 193 +
 194 --- /dev/null
 195 +++ b/arch/mips/ralink/mt7621.c
 196 @@ -0,0 +1,223 @@
 197 +/*
 198 + * This program is free software; you can redistribute it and/or modify it
 199 + * under the terms of the GNU General Public License version 2 as published
 200 + * by the Free Software Foundation.
 201 + *
 202 + * Parts of this file are based on Ralink's 2.6.21 BSP
 203 + *
 204 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 205 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 206 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 207 + */
 208 +
 209 +#include <linux/kernel.h>
 210 +#include <linux/init.h>
 211 +#include <linux/module.h>
 212 +
 213 +#include <asm/mipsregs.h>
 214 +#include <asm/smp-ops.h>
 215 +#include <asm/mips-cm.h>
 216 +#include <asm/mips-cpc.h>
 217 +#include <asm/mach-ralink/ralink_regs.h>
 218 +#include <asm/mach-ralink/mt7621.h>
 219 +
 220 +#include <pinmux.h>
 221 +
 222 +#include "common.h"
 223 +
 224 +#define SYSC_REG_SYSCFG                0x10
 225 +#define SYSC_REG_CPLL_CLKCFG0  0x2c
 226 +#define SYSC_REG_CUR_CLK_STS   0x44
 227 +#define CPU_CLK_SEL            (BIT(30) | BIT(31))
 228 +
 229 +#define MT7621_GPIO_MODE_UART1         1
 230 +#define MT7621_GPIO_MODE_I2C           2
 231 +#define MT7621_GPIO_MODE_UART3_MASK    0x3
 232 +#define MT7621_GPIO_MODE_UART3_SHIFT   3
 233 +#define MT7621_GPIO_MODE_UART3_GPIO    1
 234 +#define MT7621_GPIO_MODE_UART2_MASK    0x3
 235 +#define MT7621_GPIO_MODE_UART2_SHIFT   5
 236 +#define MT7621_GPIO_MODE_UART2_GPIO    1
 237 +#define MT7621_GPIO_MODE_JTAG          7
 238 +#define MT7621_GPIO_MODE_WDT_MASK      0x3
 239 +#define MT7621_GPIO_MODE_WDT_SHIFT     8
 240 +#define MT7621_GPIO_MODE_WDT_GPIO      1
 241 +#define MT7621_GPIO_MODE_PCIE_RST      0
 242 +#define MT7621_GPIO_MODE_PCIE_REF      2
 243 +#define MT7621_GPIO_MODE_PCIE_MASK     0x3
 244 +#define MT7621_GPIO_MODE_PCIE_SHIFT    10
 245 +#define MT7621_GPIO_MODE_PCIE_GPIO     1
 246 +#define MT7621_GPIO_MODE_MDIO_MASK     0x3
 247 +#define MT7621_GPIO_MODE_MDIO_SHIFT    12
 248 +#define MT7621_GPIO_MODE_MDIO_GPIO     1
 249 +#define MT7621_GPIO_MODE_RGMII1                14
 250 +#define MT7621_GPIO_MODE_RGMII2                15
 251 +#define MT7621_GPIO_MODE_SPI_MASK      0x3
 252 +#define MT7621_GPIO_MODE_SPI_SHIFT     16
 253 +#define MT7621_GPIO_MODE_SPI_GPIO      1
 254 +#define MT7621_GPIO_MODE_SDHCI_MASK    0x3
 255 +#define MT7621_GPIO_MODE_SDHCI_SHIFT   18
 256 +#define MT7621_GPIO_MODE_SDHCI_GPIO    1
 257 +
 258 +static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
 259 +static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
 260 +static struct rt2880_pmx_func uart3_grp[] = {
 261 +       FUNC("uart3", 0, 5, 4),
 262 +       FUNC("i2s", 2, 5, 4),
 263 +       FUNC("spdif3", 3, 5, 4),
 264 +};
 265 +static struct rt2880_pmx_func uart2_grp[] = {
 266 +       FUNC("uart2", 0, 9, 4),
 267 +       FUNC("pcm", 2, 9, 4),
 268 +       FUNC("spdif2", 3, 9, 4),
 269 +};
 270 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
 271 +static struct rt2880_pmx_func wdt_grp[] = {
 272 +       FUNC("wdt rst", 0, 18, 1),
 273 +       FUNC("wdt refclk", 2, 18, 1),
 274 +};
 275 +static struct rt2880_pmx_func pcie_rst_grp[] = {
 276 +       FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
 277 +       FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
 278 +};
 279 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
 280 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
 281 +static struct rt2880_pmx_func spi_grp[] = {
 282 +       FUNC("spi", 0, 34, 7),
 283 +       FUNC("nand1", 2, 34, 7),
 284 +};
 285 +static struct rt2880_pmx_func sdhci_grp[] = {
 286 +       FUNC("sdhci", 0, 41, 8),
 287 +       FUNC("nand2", 2, 41, 8),
 288 +};
 289 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
 290 +
 291 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
 292 +       GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
 293 +       GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
 294 +       GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
 295 +               MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
 296 +       GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
 297 +               MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
 298 +       GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
 299 +       GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
 300 +               MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
 301 +       GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
 302 +               MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
 303 +       GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
 304 +               MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
 305 +       GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
 306 +       GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
 307 +               MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
 308 +       GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
 309 +               MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
 310 +       GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
 311 +       { 0 }
 312 +};
 313 +
 314 +phys_addr_t mips_cpc_default_phys_base() {
 315 +       panic("Cannot detect cpc address");
 316 +}
 317 +
 318 +void __init ralink_clk_init(void)
 319 +{
 320 +       int cpu_fdiv = 0;
 321 +       int cpu_ffrac = 0;
 322 +       int fbdiv = 0;
 323 +       u32 clk_sts, syscfg;
 324 +       u8 clk_sel = 0, xtal_mode;
 325 +       u32 cpu_clk;
 326 +
 327 +       if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
 328 +               clk_sel = 1;
 329 +
 330 +       switch (clk_sel) {
 331 +       case 0:
 332 +               clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
 333 +               cpu_fdiv = ((clk_sts >> 8) & 0x1F);
 334 +               cpu_ffrac = (clk_sts & 0x1F);
 335 +               cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
 336 +               break;
 337 +
 338 +       case 1:
 339 +               fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
 340 +               syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
 341 +               xtal_mode = (syscfg >> 6) & 0x7;
 342 +               if(xtal_mode >= 6) { //25Mhz Xtal
 343 +                       cpu_clk = 25 * fbdiv * 1000 * 1000;
 344 +               } else if(xtal_mode >=3) { //40Mhz Xtal
 345 +                       cpu_clk = 40 * fbdiv * 1000 * 1000;
 346 +               } else { // 20Mhz Xtal
 347 +                       cpu_clk = 20 * fbdiv * 1000 * 1000;
 348 +               }
 349 +               break;
 350 +       }
 351 +}
 352 +
 353 +void __init ralink_of_remap(void)
 354 +{
 355 +       rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
 356 +       rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
 357 +
 358 +       if (!rt_sysc_membase || !rt_memc_membase)
 359 +               panic("Failed to remap core resources");
 360 +}
 361 +
 362 +void prom_soc_init(struct ralink_soc_info *soc_info)
 363 +{
 364 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
 365 +       unsigned char *name = NULL;
 366 +       u32 n0;
 367 +       u32 n1;
 368 +       u32 rev;
 369 +
 370 +       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 371 +       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 372 +
 373 +       if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
 374 +               name = "MT7621";
 375 +               soc_info->compatible = "mtk,mt7621-soc";
 376 +       } else {
 377 +               panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 378 +       }
 379 +
 380 +       rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 381 +
 382 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 383 +               "MediaTek %s ver:%u eco:%u",
 384 +               name,
 385 +               (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
 386 +               (rev & CHIP_REV_ECO_MASK));
 387 +
 388 +       soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
 389 +       soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
 390 +       soc_info->mem_base = MT7621_DRAM_BASE;
 391 +
 392 +       rt2880_pinmux_data = mt7621_pinmux_data;
 393 +
 394 +       /* Early detection of CMP support */
 395 +       mips_cm_probe();
 396 +       mips_cpc_probe();
 397 +
 398 +       if (mips_cm_numiocu()) {
 399 +               /* mips_cm_probe() wipes out bootloader
 400 +                  config for CM regions and we have to configure them
 401 +                  again. This SoC cannot talk to pamlbus devices
 402 +                  witout proper iocu region set up.
 403 +
 404 +                  FIXME: it would be better to do this with values
 405 +                  from DT, but we need this very early because
 406 +                  without this we cannot talk to pretty much anything
 407 +                  including serial.
 408 +               */
 409 +               write_gcr_reg0_base(MT7621_PALMBUS_BASE);
 410 +               write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | CM_GCR_REGn_MASK_CMTGT_IOCU0);
 411 +       }
 412 +
 413 +       if (!register_cps_smp_ops())
 414 +               return;
 415 +       if (!register_cmp_smp_ops())
 416 +               return;
 417 +       if (!register_vsmp_smp_ops())
 418 +               return;
 419 +}
 420 --- /dev/null
 421 +++ b/arch/mips/ralink/timer-gic.c
 422 @@ -0,0 +1,15 @@
 423 +#include <linux/init.h>
 424 +
 425 +#include <linux/of.h>
 426 +#include <linux/clk-provider.h>
 427 +#include <linux/clocksource.h>
 428 +
 429 +#include "common.h"
 430 +
 431 +void __init plat_time_init(void)
 432 +{
 433 +       ralink_of_remap();
 434 +
 435 +       of_clk_init(NULL);
 436 +       clocksource_probe();
 437 +}