target/linux/ramips/patches-4.4/0009-PCI-MIPS-adds-mt7620a-pcie-driver.patch

   1 From 41aa7fc236fdb1f4c9b8b10df9b71f0d248cb36b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:11:12 +0100
   4 Subject: [PATCH 09/53] PCI: MIPS: adds mt7620a pcie driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-ralink/mt7620.h |    1 +
   9  arch/mips/pci/Makefile                     |    1 +
  10  arch/mips/pci/pci-mt7620.c                 |  396 ++++++++++++++++++++++++++++
  11  arch/mips/ralink/Kconfig                   |    1 +
  12  4 files changed, 399 insertions(+)
  13  create mode 100644 arch/mips/pci/pci-mt7620.c
  14
  15 --- a/arch/mips/pci/Makefile
  16 +++ b/arch/mips/pci/Makefile
  17 @@ -43,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)  += pci-bcm1
  18  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
  19  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  20  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  21 +obj-$(CONFIG_SOC_MT7620)       += pci-mt7620.o
  22  obj-$(CONFIG_SOC_MT7621)       += pci-mt7621.o
  23  obj-$(CONFIG_SOC_RT288X)       += pci-rt2880.o
  24  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  25 --- /dev/null
  26 +++ b/arch/mips/pci/pci-mt7620.c
  27 @@ -0,0 +1,396 @@
  28 +/*
  29 + *  Ralink MT7620A SoC PCI support
  30 + *
  31 + *  Copyright (C) 2007-2013 Bruce Chang
  32 + *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  33 + *
  34 + *  This program is free software; you can redistribute it and/or modify it
  35 + *  under the terms of the GNU General Public License version 2 as published
  36 + *  by the Free Software Foundation.
  37 + */
  38 +
  39 +#include <linux/types.h>
  40 +#include <linux/pci.h>
  41 +#include <linux/io.h>
  42 +#include <linux/init.h>
  43 +#include <linux/delay.h>
  44 +#include <linux/interrupt.h>
  45 +#include <linux/module.h>
  46 +#include <linux/of.h>
  47 +#include <linux/of_irq.h>
  48 +#include <linux/of_pci.h>
  49 +#include <linux/reset.h>
  50 +#include <linux/platform_device.h>
  51 +
  52 +#include <asm/mach-ralink/ralink_regs.h>
  53 +#include <asm/mach-ralink/mt7620.h>
  54 +
  55 +#define RALINK_PCI_MM_MAP_BASE         0x20000000
  56 +#define RALINK_PCI_IO_MAP_BASE         0x10160000
  57 +
  58 +#define RALINK_INT_PCIE0               4
  59 +#define RALINK_SYSCFG1                 0x14
  60 +#define RALINK_CLKCFG1                 0x30
  61 +#define RALINK_GPIOMODE                        0x60
  62 +#define RALINK_PCIE_CLK_GEN            0x7c
  63 +#define RALINK_PCIE_CLK_GEN1           0x80
  64 +#define PCIEPHY0_CFG                   0x90
  65 +#define PPLL_CFG1                      0x9c
  66 +#define PPLL_DRV                       0xa0
  67 +#define PDRV_SW_SET                    (1<<31)
  68 +#define LC_CKDRVPD_                    (1<<19)
  69 +
  70 +#define RALINK_PCI_CONFIG_ADDR         0x20
  71 +#define RALINK_PCI_CONFIG_DATA_VIRT_REG        0x24
  72 +#define MEMORY_BASE                    0x0
  73 +#define RALINK_PCIE0_RST               (1<<26)
  74 +#define RALINK_PCI_BASE                        0xB0140000
  75 +#define RALINK_PCI_MEMBASE             0x28
  76 +#define RALINK_PCI_IOBASE              0x2C
  77 +
  78 +#define RT6855_PCIE0_OFFSET            0x2000
  79 +
  80 +#define RALINK_PCI_PCICFG_ADDR         0x00
  81 +#define RALINK_PCI0_BAR0SETUP_ADDR     0x10
  82 +#define RALINK_PCI0_IMBASEBAR0_ADDR    0x18
  83 +#define RALINK_PCI0_ID                 0x30
  84 +#define RALINK_PCI0_CLASS              0x34
  85 +#define RALINK_PCI0_SUBID              0x38
  86 +#define RALINK_PCI0_STATUS             0x50
  87 +#define RALINK_PCI_PCIMSK_ADDR         0x0C
  88 +
  89 +#define RALINK_PCIEPHY_P0_CTL_OFFSET   0x7498
  90 +#define RALINK_PCIE0_CLK_EN            (1 << 26)
  91 +
  92 +#define BUSY                           0x80000000
  93 +#define WAITRETRY_MAX                  10
  94 +#define WRITE_MODE                     (1UL << 23)
  95 +#define DATA_SHIFT                     0
  96 +#define ADDR_SHIFT                     8
  97 +
  98 +static void __iomem *bridge_base;
  99 +static void __iomem *pcie_base;
 100 +
 101 +static struct reset_control *rstpcie0;
 102 +
 103 +static inline void bridge_w32(u32 val, unsigned reg)
 104 +{
 105 +       iowrite32(val, bridge_base + reg);
 106 +}
 107 +
 108 +static inline u32 bridge_r32(unsigned reg)
 109 +{
 110 +       return ioread32(bridge_base + reg);
 111 +}
 112 +
 113 +static inline void pcie_w32(u32 val, unsigned reg)
 114 +{
 115 +       iowrite32(val, pcie_base + reg);
 116 +}
 117 +
 118 +static inline u32 pcie_r32(unsigned reg)
 119 +{
 120 +       return ioread32(pcie_base + reg);
 121 +}
 122 +
 123 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
 124 +{
 125 +       u32 val = pcie_r32(reg);
 126 +
 127 +       val &= ~clr;
 128 +       val |= set;
 129 +       pcie_w32(val, reg);
 130 +}
 131 +
 132 +static int wait_pciephy_busy(void)
 133 +{
 134 +       unsigned long reg_value = 0x0, retry = 0;
 135 +
 136 +       while (1) {
 137 +               reg_value = pcie_r32(PCIEPHY0_CFG);
 138 +
 139 +               if (reg_value & BUSY)
 140 +                       mdelay(100);
 141 +               else
 142 +                       break;
 143 +               if (retry++ > WAITRETRY_MAX){
 144 +                       printk("PCIE-PHY retry failed.\n");
 145 +                       return -1;
 146 +               }
 147 +       }
 148 +       return 0;
 149 +}
 150 +
 151 +static void pcie_phy(unsigned long addr, unsigned long val)
 152 +{
 153 +       wait_pciephy_busy();
 154 +       pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
 155 +       mdelay(1);
 156 +       wait_pciephy_busy();
 157 +}
 158 +
 159 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 160 +{
 161 +       unsigned int slot = PCI_SLOT(devfn);
 162 +       u8 func = PCI_FUNC(devfn);
 163 +       u32 address;
 164 +       u32 data;
 165 +       u32 num = 0;
 166 +
 167 +       if (bus)
 168 +               num = bus->number;
 169 +
 170 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 171 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 172 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 173 +
 174 +       switch (size) {
 175 +       case 1:
 176 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 177 +               break;
 178 +       case 2:
 179 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 180 +               break;
 181 +       case 4:
 182 +               *val = data;
 183 +               break;
 184 +       }
 185 +
 186 +       return PCIBIOS_SUCCESSFUL;
 187 +}
 188 +
 189 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 190 +{
 191 +       unsigned int slot = PCI_SLOT(devfn);
 192 +       u8 func = PCI_FUNC(devfn);
 193 +       u32 address;
 194 +       u32 data;
 195 +       u32 num = 0;
 196 +
 197 +       if (bus)
 198 +               num = bus->number;
 199 +
 200 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 201 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 202 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 203 +
 204 +       switch (size) {
 205 +       case 1:
 206 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 207 +                       (val << ((where & 3) << 3));
 208 +               break;
 209 +       case 2:
 210 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 211 +                       (val << ((where & 3) << 3));
 212 +               break;
 213 +       case 4:
 214 +               data = val;
 215 +               break;
 216 +       }
 217 +
 218 +       bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
 219 +
 220 +       return PCIBIOS_SUCCESSFUL;
 221 +}
 222 +
 223 +struct pci_ops mt7620_pci_ops= {
 224 +       .read   = pci_config_read,
 225 +       .write  = pci_config_write,
 226 +};
 227 +
 228 +static struct resource mt7620_res_pci_mem1;
 229 +static struct resource mt7620_res_pci_io1;
 230 +struct pci_controller mt7620_controller = {
 231 +       .pci_ops        = &mt7620_pci_ops,
 232 +       .mem_resource   = &mt7620_res_pci_mem1,
 233 +       .mem_offset     = 0x00000000UL,
 234 +       .io_resource    = &mt7620_res_pci_io1,
 235 +       .io_offset      = 0x00000000UL,
 236 +       .io_map_base    = 0xa0000000,
 237 +};
 238 +
 239 +static int mt7620_pci_hw_init(struct platform_device *pdev) {
 240 +       /* PCIE: bypass PCIe DLL */
 241 +       pcie_phy(0x0, 0x80);
 242 +       pcie_phy(0x1, 0x04);
 243 +
 244 +       /* PCIE: Elastic buffer control */
 245 +       pcie_phy(0x68, 0xB4);
 246 +
 247 +       pcie_m32(0, BIT(1), RALINK_PCI_PCICFG_ADDR);
 248 +
 249 +       reset_control_assert(rstpcie0);
 250 +
 251 +       rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 252 +       rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
 253 +
 254 +       reset_control_deassert(rstpcie0);
 255 +       rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 256 +
 257 +       mdelay(100);
 258 +
 259 +       if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
 260 +               dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
 261 +               reset_control_assert(rstpcie0);
 262 +               rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 263 +               return -1;
 264 +       }
 265 +       rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
 266 +
 267 +       return 0;
 268 +}
 269 +
 270 +static int mt7628_pci_hw_init(struct platform_device *pdev) {
 271 +       u32 val = 0;
 272 +
 273 +       rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
 274 +       reset_control_deassert(rstpcie0);
 275 +       rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 276 +       mdelay(100);
 277 +
 278 +       pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
 279 +
 280 +       pci_config_read(NULL, 0, 0x70c, 4, &val);
 281 +       val &= ~(0xff) << 8;
 282 +       val |= 0x50 << 8;
 283 +       pci_config_write(NULL, 0, 0x70c, 4, val);
 284 +
 285 +       pci_config_read(NULL, 0, 0x70c, 4, &val);
 286 +       dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
 287 +
 288 +       return 0;
 289 +}
 290 +
 291 +static int mt7620_pci_probe(struct platform_device *pdev)
 292 +{
 293 +       struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 294 +       struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 295 +       u32 val = 0;
 296 +
 297 +       rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
 298 +       if (IS_ERR(rstpcie0))
 299 +               return PTR_ERR(rstpcie0);
 300 +
 301 +       bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
 302 +        if (!bridge_base)
 303 +               return -ENOMEM;
 304 +
 305 +       pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
 306 +        if (!pcie_base)
 307 +               return -ENOMEM;
 308 +
 309 +       iomem_resource.start = 0;
 310 +       iomem_resource.end = ~0;
 311 +       ioport_resource.start = 0;
 312 +       ioport_resource.end = ~0;
 313 +
 314 +       /* bring up the pci core */
 315 +       switch (ralink_soc) {
 316 +       case MT762X_SOC_MT7620A:
 317 +               if (mt7620_pci_hw_init(pdev))
 318 +                       return -1;
 319 +               break;
 320 +
 321 +       case MT762X_SOC_MT7628AN:
 322 +               if (mt7628_pci_hw_init(pdev))
 323 +                       return -1;
 324 +               break;
 325 +
 326 +       default:
 327 +               dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
 328 +               return -1;
 329 +       }
 330 +       mdelay(50);
 331 +
 332 +       /* enable write access */
 333 +       pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
 334 +       mdelay(100);
 335 +
 336 +       /* check if there is a card present */
 337 +       if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
 338 +               reset_control_assert(rstpcie0);
 339 +               rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 340 +               if (ralink_soc == MT762X_SOC_MT7620A)
 341 +                       rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
 342 +               dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
 343 +               return -1;
 344 +       }
 345 +
 346 +       /* setup ranges */
 347 +       bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
 348 +       bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 349 +
 350 +       pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
 351 +       pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
 352 +       pcie_w32(0x06040001, RALINK_PCI0_CLASS);
 353 +
 354 +       /* enable interrupts */
 355 +       pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
 356 +
 357 +       /* voodoo from the SDK driver */
 358 +       pci_config_read(NULL, 0, 4, 4, &val);
 359 +       pci_config_write(NULL, 0, 4, 4, val | 0x7);
 360 +
 361 +       pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
 362 +       register_pci_controller(&mt7620_controller);
 363 +
 364 +       return 0;
 365 +}
 366 +
 367 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 368 +{
 369 +       u16 cmd;
 370 +       u32 val;
 371 +       int irq = 0;
 372 +
 373 +       if ((dev->bus->number == 0) && (slot == 0)) {
 374 +               pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
 375 +               pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
 376 +               pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
 377 +       } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 378 +               irq = RALINK_INT_PCIE0;
 379 +       } else {
 380 +               dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
 381 +               return 0;
 382 +       }
 383 +       dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
 384 +
 385 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 386 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 387 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 388 +
 389 +       // FIXME
 390 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 391 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 392 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 393 +       //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
 394 +
 395 +       return irq;
 396 +}
 397 +
 398 +int pcibios_plat_dev_init(struct pci_dev *dev)
 399 +{
 400 +       return 0;
 401 +}
 402 +
 403 +static const struct of_device_id mt7620_pci_ids[] = {
 404 +       { .compatible = "mediatek,mt7620-pci" },
 405 +       {},
 406 +};
 407 +MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
 408 +
 409 +static struct platform_driver mt7620_pci_driver = {
 410 +       .probe = mt7620_pci_probe,
 411 +       .driver = {
 412 +               .name = "mt7620-pci",
 413 +               .owner = THIS_MODULE,
 414 +               .of_match_table = of_match_ptr(mt7620_pci_ids),
 415 +       },
 416 +};
 417 +
 418 +static int __init mt7620_pci_init(void)
 419 +{
 420 +       return platform_driver_register(&mt7620_pci_driver);
 421 +}
 422 +
 423 +arch_initcall(mt7620_pci_init);
 424 --- a/arch/mips/ralink/Kconfig
 425 +++ b/arch/mips/ralink/Kconfig
 426 @@ -43,6 +43,7 @@ choice
 427
 428         config SOC_MT7620
 429                 bool "MT7620/8"
 430 +               select HW_HAS_PCI
 431
 432         config SOC_MT7621
 433                 bool "MT7621"