target/linux/ramips/patches-4.4/0033-xhci-mediatek-support-MTK-xHCI-host-controller.patch

   1 From: Chunfeng Yun <chunfeng.yun@mediatek.com>
   2 Date: Tue, 24 Nov 2015 13:09:55 +0200
   3 Subject: [PATCH] xhci: mediatek: support MTK xHCI host controller
   4
   5 There some vendor quirks for MTK xhci host controller:
   6 1. It defines some extra SW scheduling parameters for HW
   7   to minimize the scheduling effort for synchronous and
   8   interrupt endpoints. The parameters are put into reseved
   9   DWs of slot context and endpoint context.
  10 2. Its IMODI unit for Interrupter Moderation register is
  11   8 times as much as that defined in xHCI spec.
  12 3. Its TDS in  Normal TRB defines a number of packets that
  13   remains to be transferred for a TD after processing all
  14   Max packets in all previous TRBs.
  15
  16 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  17 Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
  18 Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  19 Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
  20 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  21 ---
  22  create mode 100644 drivers/usb/host/xhci-mtk-sch.c
  23  create mode 100644 drivers/usb/host/xhci-mtk.c
  24  create mode 100644 drivers/usb/host/xhci-mtk.h
  25
  26 --- a/drivers/usb/host/Kconfig
  27 +++ b/drivers/usb/host/Kconfig
  28 @@ -41,6 +41,15 @@ config USB_XHCI_PLATFORM
  29
  30           If unsure, say N.
  31
  32 +config USB_XHCI_MTK
  33 +       tristate "xHCI support for Mediatek MT65xx"
  34 +       select MFD_SYSCON
  35 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  36 +       ---help---
  37 +         Say 'Y' to enable the support for the xHCI host controller
  38 +         found in Mediatek MT65xx SoCs.
  39 +         If unsure, say N.
  40 +
  41  config USB_XHCI_MVEBU
  42         tristate "xHCI support for Marvell Armada 375/38x"
  43         select USB_XHCI_PLATFORM
  44 --- a/drivers/usb/host/Makefile
  45 +++ b/drivers/usb/host/Makefile
  46 @@ -13,6 +13,9 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
  47  xhci-hcd-y := xhci.o xhci-mem.o
  48  xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
  49  xhci-hcd-y += xhci-trace.o
  50 +ifneq ($(CONFIG_USB_XHCI_MTK), )
  51 +       xhci-hcd-y += xhci-mtk-sch.o
  52 +endif
  53
  54  xhci-plat-hcd-y := xhci-plat.o
  55  ifneq ($(CONFIG_USB_XHCI_MVEBU), )
  56 @@ -64,6 +67,7 @@ obj-$(CONFIG_USB_FHCI_HCD)    += fhci.o
  57  obj-$(CONFIG_USB_XHCI_HCD)     += xhci-hcd.o
  58  obj-$(CONFIG_USB_XHCI_PCI)     += xhci-pci.o
  59  obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
  60 +obj-$(CONFIG_USB_XHCI_MTK)     += xhci-mtk.o
  61  obj-$(CONFIG_USB_SL811_HCD)    += sl811-hcd.o
  62  obj-$(CONFIG_USB_SL811_CS)     += sl811_cs.o
  63  obj-$(CONFIG_USB_U132_HCD)     += u132-hcd.o
  64 --- /dev/null
  65 +++ b/drivers/usb/host/xhci-mtk-sch.c
  66 @@ -0,0 +1,415 @@
  67 +/*
  68 + * Copyright (c) 2015 MediaTek Inc.
  69 + * Author:
  70 + *  Zhigang.Wei <zhigang.wei@mediatek.com>
  71 + *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
  72 + *
  73 + * This software is licensed under the terms of the GNU General Public
  74 + * License version 2, as published by the Free Software Foundation, and
  75 + * may be copied, distributed, and modified under those terms.
  76 + *
  77 + * This program is distributed in the hope that it will be useful,
  78 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  79 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  80 + * GNU General Public License for more details.
  81 + *
  82 + */
  83 +
  84 +#include <linux/kernel.h>
  85 +#include <linux/module.h>
  86 +#include <linux/slab.h>
  87 +
  88 +#include "xhci.h"
  89 +#include "xhci-mtk.h"
  90 +
  91 +#define SS_BW_BOUNDARY 51000
  92 +/* table 5-5. High-speed Isoc Transaction Limits in usb_20 spec */
  93 +#define HS_BW_BOUNDARY 6144
  94 +/* usb2 spec section11.18.1: at most 188 FS bytes per microframe */
  95 +#define FS_PAYLOAD_MAX 188
  96 +
  97 +/* mtk scheduler bitmasks */
  98 +#define EP_BPKTS(p)    ((p) & 0x3f)
  99 +#define EP_BCSCOUNT(p) (((p) & 0x7) << 8)
 100 +#define EP_BBM(p)      ((p) << 11)
 101 +#define EP_BOFFSET(p)  ((p) & 0x3fff)
 102 +#define EP_BREPEAT(p)  (((p) & 0x7fff) << 16)
 103 +
 104 +static int is_fs_or_ls(enum usb_device_speed speed)
 105 +{
 106 +       return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
 107 +}
 108 +
 109 +/*
 110 +* get the index of bandwidth domains array which @ep belongs to.
 111 +*
 112 +* the bandwidth domain array is saved to @sch_array of struct xhci_hcd_mtk,
 113 +* each HS root port is treated as a single bandwidth domain,
 114 +* but each SS root port is treated as two bandwidth domains, one for IN eps,
 115 +* one for OUT eps.
 116 +* @real_port value is defined as follow according to xHCI spec:
 117 +* 1 for SSport0, ..., N+1 for SSportN, N+2 for HSport0, N+3 for HSport1, etc
 118 +* so the bandwidth domain array is organized as follow for simplification:
 119 +* SSport0-OUT, SSport0-IN, ..., SSportX-OUT, SSportX-IN, HSport0, ..., HSportY
 120 +*/
 121 +static int get_bw_index(struct xhci_hcd *xhci, struct usb_device *udev,
 122 +       struct usb_host_endpoint *ep)
 123 +{
 124 +       struct xhci_virt_device *virt_dev;
 125 +       int bw_index;
 126 +
 127 +       virt_dev = xhci->devs[udev->slot_id];
 128 +
 129 +       if (udev->speed == USB_SPEED_SUPER) {
 130 +               if (usb_endpoint_dir_out(&ep->desc))
 131 +                       bw_index = (virt_dev->real_port - 1) * 2;
 132 +               else
 133 +                       bw_index = (virt_dev->real_port - 1) * 2 + 1;
 134 +       } else {
 135 +               /* add one more for each SS port */
 136 +               bw_index = virt_dev->real_port + xhci->num_usb3_ports - 1;
 137 +       }
 138 +
 139 +       return bw_index;
 140 +}
 141 +
 142 +static void setup_sch_info(struct usb_device *udev,
 143 +               struct xhci_ep_ctx *ep_ctx, struct mu3h_sch_ep_info *sch_ep)
 144 +{
 145 +       u32 ep_type;
 146 +       u32 ep_interval;
 147 +       u32 max_packet_size;
 148 +       u32 max_burst;
 149 +       u32 mult;
 150 +       u32 esit_pkts;
 151 +
 152 +       ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
 153 +       ep_interval = CTX_TO_EP_INTERVAL(le32_to_cpu(ep_ctx->ep_info));
 154 +       max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
 155 +       max_burst = CTX_TO_MAX_BURST(le32_to_cpu(ep_ctx->ep_info2));
 156 +       mult = CTX_TO_EP_MULT(le32_to_cpu(ep_ctx->ep_info));
 157 +
 158 +       sch_ep->esit = 1 << ep_interval;
 159 +       sch_ep->offset = 0;
 160 +       sch_ep->burst_mode = 0;
 161 +
 162 +       if (udev->speed == USB_SPEED_HIGH) {
 163 +               sch_ep->cs_count = 0;
 164 +
 165 +               /*
 166 +                * usb_20 spec section5.9
 167 +                * a single microframe is enough for HS synchromous endpoints
 168 +                * in a interval
 169 +                */
 170 +               sch_ep->num_budget_microframes = 1;
 171 +               sch_ep->repeat = 0;
 172 +
 173 +               /*
 174 +                * xHCI spec section6.2.3.4
 175 +                * @max_burst is the number of additional transactions
 176 +                * opportunities per microframe
 177 +                */
 178 +               sch_ep->pkts = max_burst + 1;
 179 +               sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
 180 +       } else if (udev->speed == USB_SPEED_SUPER) {
 181 +               /* usb3_r1 spec section4.4.7 & 4.4.8 */
 182 +               sch_ep->cs_count = 0;
 183 +               esit_pkts = (mult + 1) * (max_burst + 1);
 184 +               if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
 185 +                       sch_ep->pkts = esit_pkts;
 186 +                       sch_ep->num_budget_microframes = 1;
 187 +                       sch_ep->repeat = 0;
 188 +               }
 189 +
 190 +               if (ep_type == ISOC_IN_EP || ep_type == ISOC_OUT_EP) {
 191 +                       if (esit_pkts <= sch_ep->esit)
 192 +                               sch_ep->pkts = 1;
 193 +                       else
 194 +                               sch_ep->pkts = roundup_pow_of_two(esit_pkts)
 195 +                                       / sch_ep->esit;
 196 +
 197 +                       sch_ep->num_budget_microframes =
 198 +                               DIV_ROUND_UP(esit_pkts, sch_ep->pkts);
 199 +
 200 +                       if (sch_ep->num_budget_microframes > 1)
 201 +                               sch_ep->repeat = 1;
 202 +                       else
 203 +                               sch_ep->repeat = 0;
 204 +               }
 205 +               sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
 206 +       } else if (is_fs_or_ls(udev->speed)) {
 207 +
 208 +               /*
 209 +                * usb_20 spec section11.18.4
 210 +                * assume worst cases
 211 +                */
 212 +               sch_ep->repeat = 0;
 213 +               sch_ep->pkts = 1; /* at most one packet for each microframe */
 214 +               if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
 215 +                       sch_ep->cs_count = 3; /* at most need 3 CS*/
 216 +                       /* one for SS and one for budgeted transaction */
 217 +                       sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
 218 +                       sch_ep->bw_cost_per_microframe = max_packet_size;
 219 +               }
 220 +               if (ep_type == ISOC_OUT_EP) {
 221 +
 222 +                       /*
 223 +                        * the best case FS budget assumes that 188 FS bytes
 224 +                        * occur in each microframe
 225 +                        */
 226 +                       sch_ep->num_budget_microframes = DIV_ROUND_UP(
 227 +                               max_packet_size, FS_PAYLOAD_MAX);
 228 +                       sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
 229 +                       sch_ep->cs_count = sch_ep->num_budget_microframes;
 230 +               }
 231 +               if (ep_type == ISOC_IN_EP) {
 232 +                       /* at most need additional two CS. */
 233 +                       sch_ep->cs_count = DIV_ROUND_UP(
 234 +                               max_packet_size, FS_PAYLOAD_MAX) + 2;
 235 +                       sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
 236 +                       sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
 237 +               }
 238 +       }
 239 +}
 240 +
 241 +/* Get maximum bandwidth when we schedule at offset slot. */
 242 +static u32 get_max_bw(struct mu3h_sch_bw_info *sch_bw,
 243 +       struct mu3h_sch_ep_info *sch_ep, u32 offset)
 244 +{
 245 +       u32 num_esit;
 246 +       u32 max_bw = 0;
 247 +       int i;
 248 +       int j;
 249 +
 250 +       num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
 251 +       for (i = 0; i < num_esit; i++) {
 252 +               u32 base = offset + i * sch_ep->esit;
 253 +
 254 +               for (j = 0; j < sch_ep->num_budget_microframes; j++) {
 255 +                       if (sch_bw->bus_bw[base + j] > max_bw)
 256 +                               max_bw = sch_bw->bus_bw[base + j];
 257 +               }
 258 +       }
 259 +       return max_bw;
 260 +}
 261 +
 262 +static void update_bus_bw(struct mu3h_sch_bw_info *sch_bw,
 263 +       struct mu3h_sch_ep_info *sch_ep, int bw_cost)
 264 +{
 265 +       u32 num_esit;
 266 +       u32 base;
 267 +       int i;
 268 +       int j;
 269 +
 270 +       num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
 271 +       for (i = 0; i < num_esit; i++) {
 272 +               base = sch_ep->offset + i * sch_ep->esit;
 273 +               for (j = 0; j < sch_ep->num_budget_microframes; j++)
 274 +                       sch_bw->bus_bw[base + j] += bw_cost;
 275 +       }
 276 +}
 277 +
 278 +static int check_sch_bw(struct usb_device *udev,
 279 +       struct mu3h_sch_bw_info *sch_bw, struct mu3h_sch_ep_info *sch_ep)
 280 +{
 281 +       u32 offset;
 282 +       u32 esit;
 283 +       u32 num_budget_microframes;
 284 +       u32 min_bw;
 285 +       u32 min_index;
 286 +       u32 worst_bw;
 287 +       u32 bw_boundary;
 288 +
 289 +       if (sch_ep->esit > XHCI_MTK_MAX_ESIT)
 290 +               sch_ep->esit = XHCI_MTK_MAX_ESIT;
 291 +
 292 +       esit = sch_ep->esit;
 293 +       num_budget_microframes = sch_ep->num_budget_microframes;
 294 +
 295 +       /*
 296 +        * Search through all possible schedule microframes.
 297 +        * and find a microframe where its worst bandwidth is minimum.
 298 +        */
 299 +       min_bw = ~0;
 300 +       min_index = 0;
 301 +       for (offset = 0; offset < esit; offset++) {
 302 +               if ((offset + num_budget_microframes) > sch_ep->esit)
 303 +                       break;
 304 +
 305 +               /*
 306 +                * usb_20 spec section11.18:
 307 +                * must never schedule Start-Split in Y6
 308 +                */
 309 +               if (is_fs_or_ls(udev->speed) && (offset % 8 == 6))
 310 +                       continue;
 311 +
 312 +               worst_bw = get_max_bw(sch_bw, sch_ep, offset);
 313 +               if (min_bw > worst_bw) {
 314 +                       min_bw = worst_bw;
 315 +                       min_index = offset;
 316 +               }
 317 +               if (min_bw == 0)
 318 +                       break;
 319 +       }
 320 +       sch_ep->offset = min_index;
 321 +
 322 +       bw_boundary = (udev->speed == USB_SPEED_SUPER)
 323 +                               ? SS_BW_BOUNDARY : HS_BW_BOUNDARY;
 324 +
 325 +       /* check bandwidth */
 326 +       if (min_bw + sch_ep->bw_cost_per_microframe > bw_boundary)
 327 +               return -ERANGE;
 328 +
 329 +       /* update bus bandwidth info */
 330 +       update_bus_bw(sch_bw, sch_ep, sch_ep->bw_cost_per_microframe);
 331 +
 332 +       return 0;
 333 +}
 334 +
 335 +static bool need_bw_sch(struct usb_host_endpoint *ep,
 336 +       enum usb_device_speed speed, int has_tt)
 337 +{
 338 +       /* only for periodic endpoints */
 339 +       if (usb_endpoint_xfer_control(&ep->desc)
 340 +               || usb_endpoint_xfer_bulk(&ep->desc))
 341 +               return false;
 342 +
 343 +       /*
 344 +        * for LS & FS periodic endpoints which its device don't attach
 345 +        * to TT are also ignored, root-hub will schedule them directly
 346 +        */
 347 +       if (is_fs_or_ls(speed) && !has_tt)
 348 +               return false;
 349 +
 350 +       return true;
 351 +}
 352 +
 353 +int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk)
 354 +{
 355 +       struct mu3h_sch_bw_info *sch_array;
 356 +       int num_usb_bus;
 357 +       int i;
 358 +
 359 +       /* ss IN and OUT are separated */
 360 +       num_usb_bus = mtk->num_u3_ports * 2 + mtk->num_u2_ports;
 361 +
 362 +       sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL);
 363 +       if (sch_array == NULL)
 364 +               return -ENOMEM;
 365 +
 366 +       for (i = 0; i < num_usb_bus; i++)
 367 +               INIT_LIST_HEAD(&sch_array[i].bw_ep_list);
 368 +
 369 +       mtk->sch_array = sch_array;
 370 +
 371 +       return 0;
 372 +}
 373 +EXPORT_SYMBOL_GPL(xhci_mtk_sch_init);
 374 +
 375 +void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk)
 376 +{
 377 +       kfree(mtk->sch_array);
 378 +}
 379 +EXPORT_SYMBOL_GPL(xhci_mtk_sch_exit);
 380 +
 381 +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
 382 +               struct usb_host_endpoint *ep)
 383 +{
 384 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 385 +       struct xhci_hcd *xhci;
 386 +       struct xhci_ep_ctx *ep_ctx;
 387 +       struct xhci_slot_ctx *slot_ctx;
 388 +       struct xhci_virt_device *virt_dev;
 389 +       struct mu3h_sch_bw_info *sch_bw;
 390 +       struct mu3h_sch_ep_info *sch_ep;
 391 +       struct mu3h_sch_bw_info *sch_array;
 392 +       unsigned int ep_index;
 393 +       int bw_index;
 394 +       int ret = 0;
 395 +
 396 +       xhci = hcd_to_xhci(hcd);
 397 +       virt_dev = xhci->devs[udev->slot_id];
 398 +       ep_index = xhci_get_endpoint_index(&ep->desc);
 399 +       slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
 400 +       ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
 401 +       sch_array = mtk->sch_array;
 402 +
 403 +       xhci_dbg(xhci, "%s() type:%d, speed:%d, mpkt:%d, dir:%d, ep:%p\n",
 404 +               __func__, usb_endpoint_type(&ep->desc), udev->speed,
 405 +               GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)),
 406 +               usb_endpoint_dir_in(&ep->desc), ep);
 407 +
 408 +       if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
 409 +               return 0;
 410 +
 411 +       bw_index = get_bw_index(xhci, udev, ep);
 412 +       sch_bw = &sch_array[bw_index];
 413 +
 414 +       sch_ep = kzalloc(sizeof(struct mu3h_sch_ep_info), GFP_NOIO);
 415 +       if (!sch_ep)
 416 +               return -ENOMEM;
 417 +
 418 +       setup_sch_info(udev, ep_ctx, sch_ep);
 419 +
 420 +       ret = check_sch_bw(udev, sch_bw, sch_ep);
 421 +       if (ret) {
 422 +               xhci_err(xhci, "Not enough bandwidth!\n");
 423 +               kfree(sch_ep);
 424 +               return -ENOSPC;
 425 +       }
 426 +
 427 +       list_add_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list);
 428 +       sch_ep->ep = ep;
 429 +
 430 +       ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts)
 431 +               | EP_BCSCOUNT(sch_ep->cs_count) | EP_BBM(sch_ep->burst_mode));
 432 +       ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset)
 433 +               | EP_BREPEAT(sch_ep->repeat));
 434 +
 435 +       xhci_dbg(xhci, " PKTS:%x, CSCOUNT:%x, BM:%x, OFFSET:%x, REPEAT:%x\n",
 436 +                       sch_ep->pkts, sch_ep->cs_count, sch_ep->burst_mode,
 437 +                       sch_ep->offset, sch_ep->repeat);
 438 +
 439 +       return 0;
 440 +}
 441 +EXPORT_SYMBOL_GPL(xhci_mtk_add_ep_quirk);
 442 +
 443 +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
 444 +               struct usb_host_endpoint *ep)
 445 +{
 446 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 447 +       struct xhci_hcd *xhci;
 448 +       struct xhci_slot_ctx *slot_ctx;
 449 +       struct xhci_virt_device *virt_dev;
 450 +       struct mu3h_sch_bw_info *sch_array;
 451 +       struct mu3h_sch_bw_info *sch_bw;
 452 +       struct mu3h_sch_ep_info *sch_ep;
 453 +       int bw_index;
 454 +
 455 +       xhci = hcd_to_xhci(hcd);
 456 +       virt_dev = xhci->devs[udev->slot_id];
 457 +       slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
 458 +       sch_array = mtk->sch_array;
 459 +
 460 +       xhci_dbg(xhci, "%s() type:%d, speed:%d, mpks:%d, dir:%d, ep:%p\n",
 461 +               __func__, usb_endpoint_type(&ep->desc), udev->speed,
 462 +               GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)),
 463 +               usb_endpoint_dir_in(&ep->desc), ep);
 464 +
 465 +       if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
 466 +               return;
 467 +
 468 +       bw_index = get_bw_index(xhci, udev, ep);
 469 +       sch_bw = &sch_array[bw_index];
 470 +
 471 +       list_for_each_entry(sch_ep, &sch_bw->bw_ep_list, endpoint) {
 472 +               if (sch_ep->ep == ep) {
 473 +                       update_bus_bw(sch_bw, sch_ep,
 474 +                               -sch_ep->bw_cost_per_microframe);
 475 +                       list_del(&sch_ep->endpoint);
 476 +                       kfree(sch_ep);
 477 +                       break;
 478 +               }
 479 +       }
 480 +}
 481 +EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
 482 --- /dev/null
 483 +++ b/drivers/usb/host/xhci-mtk.c
 484 @@ -0,0 +1,763 @@
 485 +/*
 486 + * MediaTek xHCI Host Controller Driver
 487 + *
 488 + * Copyright (c) 2015 MediaTek Inc.
 489 + * Author:
 490 + *  Chunfeng Yun <chunfeng.yun@mediatek.com>
 491 + *
 492 + * This software is licensed under the terms of the GNU General Public
 493 + * License version 2, as published by the Free Software Foundation, and
 494 + * may be copied, distributed, and modified under those terms.
 495 + *
 496 + * This program is distributed in the hope that it will be useful,
 497 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 498 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 499 + * GNU General Public License for more details.
 500 + *
 501 + */
 502 +
 503 +#include <linux/clk.h>
 504 +#include <linux/dma-mapping.h>
 505 +#include <linux/iopoll.h>
 506 +#include <linux/kernel.h>
 507 +#include <linux/mfd/syscon.h>
 508 +#include <linux/module.h>
 509 +#include <linux/of.h>
 510 +#include <linux/phy/phy.h>
 511 +#include <linux/platform_device.h>
 512 +#include <linux/pm_runtime.h>
 513 +#include <linux/regmap.h>
 514 +#include <linux/regulator/consumer.h>
 515 +
 516 +#include "xhci.h"
 517 +#include "xhci-mtk.h"
 518 +
 519 +/* ip_pw_ctrl0 register */
 520 +#define CTRL0_IP_SW_RST        BIT(0)
 521 +
 522 +/* ip_pw_ctrl1 register */
 523 +#define CTRL1_IP_HOST_PDN      BIT(0)
 524 +
 525 +/* ip_pw_ctrl2 register */
 526 +#define CTRL2_IP_DEV_PDN       BIT(0)
 527 +
 528 +/* ip_pw_sts1 register */
 529 +#define STS1_IP_SLEEP_STS      BIT(30)
 530 +#define STS1_XHCI_RST          BIT(11)
 531 +#define STS1_SYS125_RST        BIT(10)
 532 +#define STS1_REF_RST           BIT(8)
 533 +#define STS1_SYSPLL_STABLE     BIT(0)
 534 +
 535 +/* ip_xhci_cap register */
 536 +#define CAP_U3_PORT_NUM(p)     ((p) & 0xff)
 537 +#define CAP_U2_PORT_NUM(p)     (((p) >> 8) & 0xff)
 538 +
 539 +/* u3_ctrl_p register */
 540 +#define CTRL_U3_PORT_HOST_SEL  BIT(2)
 541 +#define CTRL_U3_PORT_PDN       BIT(1)
 542 +#define CTRL_U3_PORT_DIS       BIT(0)
 543 +
 544 +/* u2_ctrl_p register */
 545 +#define CTRL_U2_PORT_HOST_SEL  BIT(2)
 546 +#define CTRL_U2_PORT_PDN       BIT(1)
 547 +#define CTRL_U2_PORT_DIS       BIT(0)
 548 +
 549 +/* u2_phy_pll register */
 550 +#define CTRL_U2_FORCE_PLL_STB  BIT(28)
 551 +
 552 +#define PERI_WK_CTRL0          0x400
 553 +#define UWK_CTR0_0P_LS_PE      BIT(8)  /* posedge */
 554 +#define UWK_CTR0_0P_LS_NE      BIT(7)  /* negedge for 0p linestate*/
 555 +#define UWK_CTL1_1P_LS_C(x)    (((x) & 0xf) << 1)
 556 +#define UWK_CTL1_1P_LS_E       BIT(0)
 557 +
 558 +#define PERI_WK_CTRL1          0x404
 559 +#define UWK_CTL1_IS_C(x)       (((x) & 0xf) << 26)
 560 +#define UWK_CTL1_IS_E          BIT(25)
 561 +#define UWK_CTL1_0P_LS_C(x)    (((x) & 0xf) << 21)
 562 +#define UWK_CTL1_0P_LS_E       BIT(20)
 563 +#define UWK_CTL1_IDDIG_C(x)    (((x) & 0xf) << 11)  /* cycle debounce */
 564 +#define UWK_CTL1_IDDIG_E       BIT(10) /* enable debounce */
 565 +#define UWK_CTL1_IDDIG_P       BIT(9)  /* polarity */
 566 +#define UWK_CTL1_0P_LS_P       BIT(7)
 567 +#define UWK_CTL1_IS_P          BIT(6)  /* polarity for ip sleep */
 568 +
 569 +enum ssusb_wakeup_src {
 570 +       SSUSB_WK_IP_SLEEP = 1,
 571 +       SSUSB_WK_LINE_STATE = 2,
 572 +};
 573 +
 574 +static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
 575 +{
 576 +       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 577 +       u32 value, check_val;
 578 +       int ret;
 579 +       int i;
 580 +
 581 +       /* power on host ip */
 582 +       value = readl(&ippc->ip_pw_ctr1);
 583 +       value &= ~CTRL1_IP_HOST_PDN;
 584 +       writel(value, &ippc->ip_pw_ctr1);
 585 +
 586 +       /* power on and enable all u3 ports */
 587 +       for (i = 0; i < mtk->num_u3_ports; i++) {
 588 +               value = readl(&ippc->u3_ctrl_p[i]);
 589 +               value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
 590 +               value |= CTRL_U3_PORT_HOST_SEL;
 591 +               writel(value, &ippc->u3_ctrl_p[i]);
 592 +       }
 593 +
 594 +       /* power on and enable all u2 ports */
 595 +       for (i = 0; i < mtk->num_u2_ports; i++) {
 596 +               value = readl(&ippc->u2_ctrl_p[i]);
 597 +               value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
 598 +               value |= CTRL_U2_PORT_HOST_SEL;
 599 +               writel(value, &ippc->u2_ctrl_p[i]);
 600 +       }
 601 +
 602 +       /*
 603 +        * wait for clocks to be stable, and clock domains reset to
 604 +        * be inactive after power on and enable ports
 605 +        */
 606 +       check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
 607 +                       STS1_SYS125_RST | STS1_XHCI_RST;
 608 +
 609 +       ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
 610 +                         (check_val == (value & check_val)), 100, 20000);
 611 +       if (ret) {
 612 +               dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
 613 +               return ret;
 614 +       }
 615 +
 616 +       return 0;
 617 +}
 618 +
 619 +static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
 620 +{
 621 +       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 622 +       u32 value;
 623 +       int ret;
 624 +       int i;
 625 +
 626 +       /* power down all u3 ports */
 627 +       for (i = 0; i < mtk->num_u3_ports; i++) {
 628 +               value = readl(&ippc->u3_ctrl_p[i]);
 629 +               value |= CTRL_U3_PORT_PDN;
 630 +               writel(value, &ippc->u3_ctrl_p[i]);
 631 +       }
 632 +
 633 +       /* power down all u2 ports */
 634 +       for (i = 0; i < mtk->num_u2_ports; i++) {
 635 +               value = readl(&ippc->u2_ctrl_p[i]);
 636 +               value |= CTRL_U2_PORT_PDN;
 637 +               writel(value, &ippc->u2_ctrl_p[i]);
 638 +       }
 639 +
 640 +       /* power down host ip */
 641 +       value = readl(&ippc->ip_pw_ctr1);
 642 +       value |= CTRL1_IP_HOST_PDN;
 643 +       writel(value, &ippc->ip_pw_ctr1);
 644 +
 645 +       /* wait for host ip to sleep */
 646 +       ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
 647 +                         (value & STS1_IP_SLEEP_STS), 100, 100000);
 648 +       if (ret) {
 649 +               dev_err(mtk->dev, "ip sleep failed!!!\n");
 650 +               return ret;
 651 +       }
 652 +       return 0;
 653 +}
 654 +
 655 +static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
 656 +{
 657 +       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 658 +       u32 value;
 659 +
 660 +       /* reset whole ip */
 661 +       value = readl(&ippc->ip_pw_ctr0);
 662 +       value |= CTRL0_IP_SW_RST;
 663 +       writel(value, &ippc->ip_pw_ctr0);
 664 +       udelay(1);
 665 +       value = readl(&ippc->ip_pw_ctr0);
 666 +       value &= ~CTRL0_IP_SW_RST;
 667 +       writel(value, &ippc->ip_pw_ctr0);
 668 +
 669 +       /*
 670 +        * device ip is default power-on in fact
 671 +        * power down device ip, otherwise ip-sleep will fail
 672 +        */
 673 +       value = readl(&ippc->ip_pw_ctr2);
 674 +       value |= CTRL2_IP_DEV_PDN;
 675 +       writel(value, &ippc->ip_pw_ctr2);
 676 +
 677 +       value = readl(&ippc->ip_xhci_cap);
 678 +       mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
 679 +       mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
 680 +       dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
 681 +                       mtk->num_u2_ports, mtk->num_u3_ports);
 682 +
 683 +       return xhci_mtk_host_enable(mtk);
 684 +}
 685 +
 686 +static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
 687 +{
 688 +       int ret;
 689 +
 690 +       ret = clk_prepare_enable(mtk->sys_clk);
 691 +       if (ret) {
 692 +               dev_err(mtk->dev, "failed to enable sys_clk\n");
 693 +               goto sys_clk_err;
 694 +       }
 695 +
 696 +       if (mtk->wakeup_src) {
 697 +               ret = clk_prepare_enable(mtk->wk_deb_p0);
 698 +               if (ret) {
 699 +                       dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
 700 +                       goto usb_p0_err;
 701 +               }
 702 +
 703 +               ret = clk_prepare_enable(mtk->wk_deb_p1);
 704 +               if (ret) {
 705 +                       dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
 706 +                       goto usb_p1_err;
 707 +               }
 708 +       }
 709 +       return 0;
 710 +
 711 +usb_p1_err:
 712 +       clk_disable_unprepare(mtk->wk_deb_p0);
 713 +usb_p0_err:
 714 +       clk_disable_unprepare(mtk->sys_clk);
 715 +sys_clk_err:
 716 +       return -EINVAL;
 717 +}
 718 +
 719 +static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
 720 +{
 721 +       if (mtk->wakeup_src) {
 722 +               clk_disable_unprepare(mtk->wk_deb_p1);
 723 +               clk_disable_unprepare(mtk->wk_deb_p0);
 724 +       }
 725 +       clk_disable_unprepare(mtk->sys_clk);
 726 +}
 727 +
 728 +/* only clocks can be turn off for ip-sleep wakeup mode */
 729 +static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
 730 +{
 731 +       u32 tmp;
 732 +       struct regmap *pericfg = mtk->pericfg;
 733 +
 734 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 735 +       tmp &= ~UWK_CTL1_IS_P;
 736 +       tmp &= ~(UWK_CTL1_IS_C(0xf));
 737 +       tmp |= UWK_CTL1_IS_C(0x8);
 738 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 739 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
 740 +
 741 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 742 +       dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
 743 +               __func__, tmp);
 744 +}
 745 +
 746 +static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
 747 +{
 748 +       u32 tmp;
 749 +
 750 +       regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
 751 +       tmp &= ~UWK_CTL1_IS_E;
 752 +       regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
 753 +}
 754 +
 755 +/*
 756 +* for line-state wakeup mode, phy's power should not power-down
 757 +* and only support cable plug in/out
 758 +*/
 759 +static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
 760 +{
 761 +       u32 tmp;
 762 +       struct regmap *pericfg = mtk->pericfg;
 763 +
 764 +       /* line-state of u2-port0 */
 765 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 766 +       tmp &= ~UWK_CTL1_0P_LS_P;
 767 +       tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
 768 +       tmp |= UWK_CTL1_0P_LS_C(0x8);
 769 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 770 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 771 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
 772 +
 773 +       /* line-state of u2-port1 */
 774 +       regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
 775 +       tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
 776 +       tmp |= UWK_CTL1_1P_LS_C(0x8);
 777 +       regmap_write(pericfg, PERI_WK_CTRL0, tmp);
 778 +       regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
 779 +}
 780 +
 781 +static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
 782 +{
 783 +       u32 tmp;
 784 +       struct regmap *pericfg = mtk->pericfg;
 785 +
 786 +       /* line-state of u2-port0 */
 787 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 788 +       tmp &= ~UWK_CTL1_0P_LS_E;
 789 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 790 +
 791 +       /* line-state of u2-port1 */
 792 +       regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
 793 +       tmp &= ~UWK_CTL1_1P_LS_E;
 794 +       regmap_write(pericfg, PERI_WK_CTRL0, tmp);
 795 +}
 796 +
 797 +static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
 798 +{
 799 +       if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
 800 +               usb_wakeup_ip_sleep_en(mtk);
 801 +       else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
 802 +               usb_wakeup_line_state_en(mtk);
 803 +}
 804 +
 805 +static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
 806 +{
 807 +       if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
 808 +               usb_wakeup_ip_sleep_dis(mtk);
 809 +       else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
 810 +               usb_wakeup_line_state_dis(mtk);
 811 +}
 812 +
 813 +static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
 814 +                               struct device_node *dn)
 815 +{
 816 +       struct device *dev = mtk->dev;
 817 +
 818 +       /*
 819 +       * wakeup function is optional, so it is not an error if this property
 820 +       * does not exist, and in such case, no need to get relative
 821 +       * properties anymore.
 822 +       */
 823 +       of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
 824 +       if (!mtk->wakeup_src)
 825 +               return 0;
 826 +
 827 +       mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
 828 +       if (IS_ERR(mtk->wk_deb_p0)) {
 829 +               dev_err(dev, "fail to get wakeup_deb_p0\n");
 830 +               return PTR_ERR(mtk->wk_deb_p0);
 831 +       }
 832 +
 833 +       mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
 834 +       if (IS_ERR(mtk->wk_deb_p1)) {
 835 +               dev_err(dev, "fail to get wakeup_deb_p1\n");
 836 +               return PTR_ERR(mtk->wk_deb_p1);
 837 +       }
 838 +
 839 +       mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
 840 +                                               "mediatek,syscon-wakeup");
 841 +       if (IS_ERR(mtk->pericfg)) {
 842 +               dev_err(dev, "fail to get pericfg regs\n");
 843 +               return PTR_ERR(mtk->pericfg);
 844 +       }
 845 +
 846 +       return 0;
 847 +}
 848 +
 849 +static int xhci_mtk_setup(struct usb_hcd *hcd);
 850 +static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
 851 +       .extra_priv_size = sizeof(struct xhci_hcd),
 852 +       .reset = xhci_mtk_setup,
 853 +};
 854 +
 855 +static struct hc_driver __read_mostly xhci_mtk_hc_driver;
 856 +
 857 +static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
 858 +{
 859 +       int i;
 860 +       int ret;
 861 +
 862 +       for (i = 0; i < mtk->num_phys; i++) {
 863 +               ret = phy_init(mtk->phys[i]);
 864 +               if (ret)
 865 +                       goto exit_phy;
 866 +       }
 867 +       return 0;
 868 +
 869 +exit_phy:
 870 +       for (; i > 0; i--)
 871 +               phy_exit(mtk->phys[i - 1]);
 872 +
 873 +       return ret;
 874 +}
 875 +
 876 +static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
 877 +{
 878 +       int i;
 879 +
 880 +       for (i = 0; i < mtk->num_phys; i++)
 881 +               phy_exit(mtk->phys[i]);
 882 +
 883 +       return 0;
 884 +}
 885 +
 886 +static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
 887 +{
 888 +       int i;
 889 +       int ret;
 890 +
 891 +       for (i = 0; i < mtk->num_phys; i++) {
 892 +               ret = phy_power_on(mtk->phys[i]);
 893 +               if (ret)
 894 +                       goto power_off_phy;
 895 +       }
 896 +       return 0;
 897 +
 898 +power_off_phy:
 899 +       for (; i > 0; i--)
 900 +               phy_power_off(mtk->phys[i - 1]);
 901 +
 902 +       return ret;
 903 +}
 904 +
 905 +static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
 906 +{
 907 +       unsigned int i;
 908 +
 909 +       for (i = 0; i < mtk->num_phys; i++)
 910 +               phy_power_off(mtk->phys[i]);
 911 +}
 912 +
 913 +static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
 914 +{
 915 +       int ret;
 916 +
 917 +       ret = regulator_enable(mtk->vbus);
 918 +       if (ret) {
 919 +               dev_err(mtk->dev, "failed to enable vbus\n");
 920 +               return ret;
 921 +       }
 922 +
 923 +       ret = regulator_enable(mtk->vusb33);
 924 +       if (ret) {
 925 +               dev_err(mtk->dev, "failed to enable vusb33\n");
 926 +               regulator_disable(mtk->vbus);
 927 +               return ret;
 928 +       }
 929 +       return 0;
 930 +}
 931 +
 932 +static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
 933 +{
 934 +       regulator_disable(mtk->vbus);
 935 +       regulator_disable(mtk->vusb33);
 936 +}
 937 +
 938 +static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
 939 +{
 940 +       struct usb_hcd *hcd = xhci_to_hcd(xhci);
 941 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 942 +
 943 +       /*
 944 +        * As of now platform drivers don't provide MSI support so we ensure
 945 +        * here that the generic code does not try to make a pci_dev from our
 946 +        * dev struct in order to setup MSI
 947 +        */
 948 +       xhci->quirks |= XHCI_PLAT;
 949 +       xhci->quirks |= XHCI_MTK_HOST;
 950 +       /*
 951 +        * MTK host controller gives a spurious successful event after a
 952 +        * short transfer. Ignore it.
 953 +        */
 954 +       xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 955 +       if (mtk->lpm_support)
 956 +               xhci->quirks |= XHCI_LPM_SUPPORT;
 957 +}
 958 +
 959 +/* called during probe() after chip reset completes */
 960 +static int xhci_mtk_setup(struct usb_hcd *hcd)
 961 +{
 962 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 963 +       int ret;
 964 +
 965 +       if (usb_hcd_is_primary_hcd(hcd)) {
 966 +               ret = xhci_mtk_ssusb_config(mtk);
 967 +               if (ret)
 968 +                       return ret;
 969 +               ret = xhci_mtk_sch_init(mtk);
 970 +               if (ret)
 971 +                       return ret;
 972 +       }
 973 +
 974 +       return xhci_gen_setup(hcd, xhci_mtk_quirks);
 975 +}
 976 +
 977 +static int xhci_mtk_probe(struct platform_device *pdev)
 978 +{
 979 +       struct device *dev = &pdev->dev;
 980 +       struct device_node *node = dev->of_node;
 981 +       struct xhci_hcd_mtk *mtk;
 982 +       const struct hc_driver *driver;
 983 +       struct xhci_hcd *xhci;
 984 +       struct resource *res;
 985 +       struct usb_hcd *hcd;
 986 +       struct phy *phy;
 987 +       int phy_num;
 988 +       int ret = -ENODEV;
 989 +       int irq;
 990 +
 991 +       if (usb_disabled())
 992 +               return -ENODEV;
 993 +
 994 +       driver = &xhci_mtk_hc_driver;
 995 +       mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
 996 +       if (!mtk)
 997 +               return -ENOMEM;
 998 +
 999 +       mtk->dev = dev;
1000 +       mtk->vbus = devm_regulator_get(dev, "vbus");
1001 +       if (IS_ERR(mtk->vbus)) {
1002 +               dev_err(dev, "fail to get vbus\n");
1003 +               return PTR_ERR(mtk->vbus);
1004 +       }
1005 +
1006 +       mtk->vusb33 = devm_regulator_get(dev, "vusb33");
1007 +       if (IS_ERR(mtk->vusb33)) {
1008 +               dev_err(dev, "fail to get vusb33\n");
1009 +               return PTR_ERR(mtk->vusb33);
1010 +       }
1011 +
1012 +       mtk->sys_clk = devm_clk_get(dev, "sys_ck");
1013 +       if (IS_ERR(mtk->sys_clk)) {
1014 +               dev_err(dev, "fail to get sys_ck\n");
1015 +               return PTR_ERR(mtk->sys_clk);
1016 +       }
1017 +
1018 +       mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
1019 +
1020 +       ret = usb_wakeup_of_property_parse(mtk, node);
1021 +       if (ret)
1022 +               return ret;
1023 +
1024 +       mtk->num_phys = of_count_phandle_with_args(node,
1025 +                       "phys", "#phy-cells");
1026 +       if (mtk->num_phys > 0) {
1027 +               mtk->phys = devm_kcalloc(dev, mtk->num_phys,
1028 +                                       sizeof(*mtk->phys), GFP_KERNEL);
1029 +               if (!mtk->phys)
1030 +                       return -ENOMEM;
1031 +       } else {
1032 +               mtk->num_phys = 0;
1033 +       }
1034 +       pm_runtime_enable(dev);
1035 +       pm_runtime_get_sync(dev);
1036 +       device_enable_async_suspend(dev);
1037 +
1038 +       ret = xhci_mtk_ldos_enable(mtk);
1039 +       if (ret)
1040 +               goto disable_pm;
1041 +
1042 +       ret = xhci_mtk_clks_enable(mtk);
1043 +       if (ret)
1044 +               goto disable_ldos;
1045 +
1046 +       irq = platform_get_irq(pdev, 0);
1047 +       if (irq < 0)
1048 +               goto disable_clk;
1049 +
1050 +       /* Initialize dma_mask and coherent_dma_mask to 32-bits */
1051 +       ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
1052 +       if (ret)
1053 +               goto disable_clk;
1054 +
1055 +       if (!dev->dma_mask)
1056 +               dev->dma_mask = &dev->coherent_dma_mask;
1057 +       else
1058 +               dma_set_mask(dev, DMA_BIT_MASK(32));
1059 +
1060 +       hcd = usb_create_hcd(driver, dev, dev_name(dev));
1061 +       if (!hcd) {
1062 +               ret = -ENOMEM;
1063 +               goto disable_clk;
1064 +       }
1065 +
1066 +       /*
1067 +        * USB 2.0 roothub is stored in the platform_device.
1068 +        * Swap it with mtk HCD.
1069 +        */
1070 +       mtk->hcd = platform_get_drvdata(pdev);
1071 +       platform_set_drvdata(pdev, mtk);
1072 +
1073 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1074 +       hcd->regs = devm_ioremap_resource(dev, res);
1075 +       if (IS_ERR(hcd->regs)) {
1076 +               ret = PTR_ERR(hcd->regs);
1077 +               goto put_usb2_hcd;
1078 +       }
1079 +       hcd->rsrc_start = res->start;
1080 +       hcd->rsrc_len = resource_size(res);
1081 +
1082 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1083 +       mtk->ippc_regs = devm_ioremap_resource(dev, res);
1084 +       if (IS_ERR(mtk->ippc_regs)) {
1085 +               ret = PTR_ERR(mtk->ippc_regs);
1086 +               goto put_usb2_hcd;
1087 +       }
1088 +
1089 +       for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
1090 +               phy = devm_of_phy_get_by_index(dev, node, phy_num);
1091 +               if (IS_ERR(phy)) {
1092 +                       ret = PTR_ERR(phy);
1093 +                       goto put_usb2_hcd;
1094 +               }
1095 +               mtk->phys[phy_num] = phy;
1096 +       }
1097 +
1098 +       ret = xhci_mtk_phy_init(mtk);
1099 +       if (ret)
1100 +               goto put_usb2_hcd;
1101 +
1102 +       ret = xhci_mtk_phy_power_on(mtk);
1103 +       if (ret)
1104 +               goto exit_phys;
1105 +
1106 +       device_init_wakeup(dev, true);
1107 +
1108 +       xhci = hcd_to_xhci(hcd);
1109 +       xhci->main_hcd = hcd;
1110 +       xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
1111 +                       dev_name(dev), hcd);
1112 +       if (!xhci->shared_hcd) {
1113 +               ret = -ENOMEM;
1114 +               goto power_off_phys;
1115 +       }
1116 +
1117 +       if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
1118 +               xhci->shared_hcd->can_do_streams = 1;
1119 +
1120 +       ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
1121 +       if (ret)
1122 +               goto put_usb3_hcd;
1123 +
1124 +       ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
1125 +       if (ret)
1126 +               goto dealloc_usb2_hcd;
1127 +
1128 +       return 0;
1129 +
1130 +dealloc_usb2_hcd:
1131 +       usb_remove_hcd(hcd);
1132 +
1133 +put_usb3_hcd:
1134 +       xhci_mtk_sch_exit(mtk);
1135 +       usb_put_hcd(xhci->shared_hcd);
1136 +
1137 +power_off_phys:
1138 +       xhci_mtk_phy_power_off(mtk);
1139 +       device_init_wakeup(dev, false);
1140 +
1141 +exit_phys:
1142 +       xhci_mtk_phy_exit(mtk);
1143 +
1144 +put_usb2_hcd:
1145 +       usb_put_hcd(hcd);
1146 +
1147 +disable_clk:
1148 +       xhci_mtk_clks_disable(mtk);
1149 +
1150 +disable_ldos:
1151 +       xhci_mtk_ldos_disable(mtk);
1152 +
1153 +disable_pm:
1154 +       pm_runtime_put_sync(dev);
1155 +       pm_runtime_disable(dev);
1156 +       return ret;
1157 +}
1158 +
1159 +static int xhci_mtk_remove(struct platform_device *dev)
1160 +{
1161 +       struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
1162 +       struct usb_hcd  *hcd = mtk->hcd;
1163 +       struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1164 +
1165 +       usb_remove_hcd(xhci->shared_hcd);
1166 +       xhci_mtk_phy_power_off(mtk);
1167 +       xhci_mtk_phy_exit(mtk);
1168 +       device_init_wakeup(&dev->dev, false);
1169 +
1170 +       usb_remove_hcd(hcd);
1171 +       usb_put_hcd(xhci->shared_hcd);
1172 +       usb_put_hcd(hcd);
1173 +       xhci_mtk_sch_exit(mtk);
1174 +       xhci_mtk_clks_disable(mtk);
1175 +       xhci_mtk_ldos_disable(mtk);
1176 +       pm_runtime_put_sync(&dev->dev);
1177 +       pm_runtime_disable(&dev->dev);
1178 +
1179 +       return 0;
1180 +}
1181 +
1182 +#ifdef CONFIG_PM_SLEEP
1183 +static int xhci_mtk_suspend(struct device *dev)
1184 +{
1185 +       struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
1186 +
1187 +       xhci_mtk_host_disable(mtk);
1188 +       xhci_mtk_phy_power_off(mtk);
1189 +       xhci_mtk_clks_disable(mtk);
1190 +       usb_wakeup_enable(mtk);
1191 +       return 0;
1192 +}
1193 +
1194 +static int xhci_mtk_resume(struct device *dev)
1195 +{
1196 +       struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
1197 +
1198 +       usb_wakeup_disable(mtk);
1199 +       xhci_mtk_clks_enable(mtk);
1200 +       xhci_mtk_phy_power_on(mtk);
1201 +       xhci_mtk_host_enable(mtk);
1202 +       return 0;
1203 +}
1204 +
1205 +static const struct dev_pm_ops xhci_mtk_pm_ops = {
1206 +       SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
1207 +};
1208 +#define DEV_PM_OPS     (&xhci_mtk_pm_ops)
1209 +#else
1210 +#define DEV_PM_OPS     NULL
1211 +#endif /* CONFIG_PM */
1212 +
1213 +#ifdef CONFIG_OF
1214 +static const struct of_device_id mtk_xhci_of_match[] = {
1215 +       { .compatible = "mediatek,mt8173-xhci"},
1216 +       { },
1217 +};
1218 +MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
1219 +#endif
1220 +
1221 +static struct platform_driver mtk_xhci_driver = {
1222 +       .probe  = xhci_mtk_probe,
1223 +       .remove = xhci_mtk_remove,
1224 +       .driver = {
1225 +               .name = "xhci-mtk",
1226 +               .pm = DEV_PM_OPS,
1227 +               .of_match_table = of_match_ptr(mtk_xhci_of_match),
1228 +       },
1229 +};
1230 +MODULE_ALIAS("platform:xhci-mtk");
1231 +
1232 +static int __init xhci_mtk_init(void)
1233 +{
1234 +       xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
1235 +       return platform_driver_register(&mtk_xhci_driver);
1236 +}
1237 +module_init(xhci_mtk_init);
1238 +
1239 +static void __exit xhci_mtk_exit(void)
1240 +{
1241 +       platform_driver_unregister(&mtk_xhci_driver);
1242 +}
1243 +module_exit(xhci_mtk_exit);
1244 +
1245 +MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
1246 +MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
1247 +MODULE_LICENSE("GPL v2");
1248 --- /dev/null
1249 +++ b/drivers/usb/host/xhci-mtk.h
1250 @@ -0,0 +1,162 @@
1251 +/*
1252 + * Copyright (c) 2015 MediaTek Inc.
1253 + * Author:
1254 + *  Zhigang.Wei <zhigang.wei@mediatek.com>
1255 + *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
1256 + *
1257 + * This software is licensed under the terms of the GNU General Public
1258 + * License version 2, as published by the Free Software Foundation, and
1259 + * may be copied, distributed, and modified under those terms.
1260 + *
1261 + * This program is distributed in the hope that it will be useful,
1262 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1263 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1264 + * GNU General Public License for more details.
1265 + *
1266 + */
1267 +
1268 +#ifndef _XHCI_MTK_H_
1269 +#define _XHCI_MTK_H_
1270 +
1271 +#include "xhci.h"
1272 +
1273 +/**
1274 + * To simplify scheduler algorithm, set a upper limit for ESIT,
1275 + * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
1276 + * round down to the limit value, that means allocating more
1277 + * bandwidth to it.
1278 + */
1279 +#define XHCI_MTK_MAX_ESIT      64
1280 +
1281 +/**
1282 + * struct mu3h_sch_bw_info: schedule information for bandwidth domain
1283 + *
1284 + * @bus_bw: array to keep track of bandwidth already used at each uframes
1285 + * @bw_ep_list: eps in the bandwidth domain
1286 + *
1287 + * treat a HS root port as a bandwidth domain, but treat a SS root port as
1288 + * two bandwidth domains, one for IN eps and another for OUT eps.
1289 + */
1290 +struct mu3h_sch_bw_info {
1291 +       u32 bus_bw[XHCI_MTK_MAX_ESIT];
1292 +       struct list_head bw_ep_list;
1293 +};
1294 +
1295 +/**
1296 + * struct mu3h_sch_ep_info: schedule information for endpoint
1297 + *
1298 + * @esit: unit is 125us, equal to 2 << Interval field in ep-context
1299 + * @num_budget_microframes: number of continuous uframes
1300 + *             (@repeat==1) scheduled within the interval
1301 + * @bw_cost_per_microframe: bandwidth cost per microframe
1302 + * @endpoint: linked into bandwidth domain which it belongs to
1303 + * @ep: address of usb_host_endpoint struct
1304 + * @offset: which uframe of the interval that transfer should be
1305 + *             scheduled first time within the interval
1306 + * @repeat: the time gap between two uframes that transfers are
1307 + *             scheduled within a interval. in the simple algorithm, only
1308 + *             assign 0 or 1 to it; 0 means using only one uframe in a
1309 + *             interval, and 1 means using @num_budget_microframes
1310 + *             continuous uframes
1311 + * @pkts: number of packets to be transferred in the scheduled uframes
1312 + * @cs_count: number of CS that host will trigger
1313 + * @burst_mode: burst mode for scheduling. 0: normal burst mode,
1314 + *             distribute the bMaxBurst+1 packets for a single burst
1315 + *             according to @pkts and @repeat, repeate the burst multiple
1316 + *             times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
1317 + *             according to @pkts and @repeat. normal mode is used by
1318 + *             default
1319 + */
1320 +struct mu3h_sch_ep_info {
1321 +       u32 esit;
1322 +       u32 num_budget_microframes;
1323 +       u32 bw_cost_per_microframe;
1324 +       struct list_head endpoint;
1325 +       void *ep;
1326 +       /*
1327 +        * mtk xHCI scheduling information put into reserved DWs
1328 +        * in ep context
1329 +        */
1330 +       u32 offset;
1331 +       u32 repeat;
1332 +       u32 pkts;
1333 +       u32 cs_count;
1334 +       u32 burst_mode;
1335 +};
1336 +
1337 +#define MU3C_U3_PORT_MAX 4
1338 +#define MU3C_U2_PORT_MAX 5
1339 +
1340 +/**
1341 + * struct mu3c_ippc_regs: MTK ssusb ip port control registers
1342 + * @ip_pw_ctr0~3: ip power and clock control registers
1343 + * @ip_pw_sts1~2: ip power and clock status registers
1344 + * @ip_xhci_cap: ip xHCI capability register
1345 + * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
1346 + * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
1347 + * @u2_phy_pll: usb2 phy pll control register
1348 + */
1349 +struct mu3c_ippc_regs {
1350 +       __le32 ip_pw_ctr0;
1351 +       __le32 ip_pw_ctr1;
1352 +       __le32 ip_pw_ctr2;
1353 +       __le32 ip_pw_ctr3;
1354 +       __le32 ip_pw_sts1;
1355 +       __le32 ip_pw_sts2;
1356 +       __le32 reserved0[3];
1357 +       __le32 ip_xhci_cap;
1358 +       __le32 reserved1[2];
1359 +       __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
1360 +       __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
1361 +       __le32 reserved2;
1362 +       __le32 u2_phy_pll;
1363 +       __le32 reserved3[33]; /* 0x80 ~ 0xff */
1364 +};
1365 +
1366 +struct xhci_hcd_mtk {
1367 +       struct device *dev;
1368 +       struct usb_hcd *hcd;
1369 +       struct mu3h_sch_bw_info *sch_array;
1370 +       struct mu3c_ippc_regs __iomem *ippc_regs;
1371 +       int num_u2_ports;
1372 +       int num_u3_ports;
1373 +       struct regulator *vusb33;
1374 +       struct regulator *vbus;
1375 +       struct clk *sys_clk;    /* sys and mac clock */
1376 +       struct clk *wk_deb_p0;  /* port0's wakeup debounce clock */
1377 +       struct clk *wk_deb_p1;
1378 +       struct regmap *pericfg;
1379 +       struct phy **phys;
1380 +       int num_phys;
1381 +       int wakeup_src;
1382 +       bool lpm_support;
1383 +};
1384 +
1385 +static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
1386 +{
1387 +       return dev_get_drvdata(hcd->self.controller);
1388 +}
1389 +
1390 +#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
1391 +int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
1392 +void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
1393 +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
1394 +               struct usb_host_endpoint *ep);
1395 +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
1396 +               struct usb_host_endpoint *ep);
1397 +
1398 +#else
1399 +static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
1400 +       struct usb_device *udev, struct usb_host_endpoint *ep)
1401 +{
1402 +       return 0;
1403 +}
1404 +
1405 +static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
1406 +       struct usb_device *udev, struct usb_host_endpoint *ep)
1407 +{
1408 +}
1409 +
1410 +#endif
1411 +
1412 +#endif         /* _XHCI_MTK_H_ */
1413 --- a/drivers/usb/host/xhci-ring.c
1414 +++ b/drivers/usb/host/xhci-ring.c
1415 @@ -68,6 +68,7 @@
1416  #include <linux/slab.h>
1417  #include "xhci.h"
1418  #include "xhci-trace.h"
1419 +#include "xhci-mtk.h"
1420
1421  /*
1422   * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
1423 @@ -3084,17 +3085,22 @@ static u32 xhci_td_remainder(struct xhci
1424  {
1425         u32 maxp, total_packet_count;
1426
1427 -       if (xhci->hci_version < 0x100)
1428 +       /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */
1429 +       if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
1430                 return ((td_total_len - transferred) >> 10);
1431
1432 -       maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
1433 -       total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
1434 -
1435         /* One TRB with a zero-length data packet. */
1436         if (num_trbs_left == 0 || (transferred == 0 && trb_buff_len == 0) ||
1437             trb_buff_len == td_total_len)
1438                 return 0;
1439
1440 +       /* for MTK xHCI, TD size doesn't include this TRB */
1441 +       if (xhci->quirks & XHCI_MTK_HOST)
1442 +               trb_buff_len = 0;
1443 +
1444 +       maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
1445 +       total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
1446 +
1447         /* Queueing functions don't count the current TRB into transferred */
1448         return (total_packet_count - ((transferred + trb_buff_len) / maxp));
1449  }
1450 @@ -3482,7 +3488,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
1451                 field |= 0x1;
1452
1453         /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
1454 -       if (xhci->hci_version >= 0x100) {
1455 +       if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
1456                 if (urb->transfer_buffer_length > 0) {
1457                         if (setup->bRequestType & USB_DIR_IN)
1458                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
1459 --- a/drivers/usb/host/xhci.c
1460 +++ b/drivers/usb/host/xhci.c
1461 @@ -31,6 +31,7 @@
1462
1463  #include "xhci.h"
1464  #include "xhci-trace.h"
1465 +#include "xhci-mtk.h"
1466
1467  #define DRIVER_AUTHOR "Sarah Sharp"
1468  #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
1469 @@ -635,7 +636,11 @@ int xhci_run(struct usb_hcd *hcd)
1470                         "// Set the interrupt modulation register");
1471         temp = readl(&xhci->ir_set->irq_control);
1472         temp &= ~ER_IRQ_INTERVAL_MASK;
1473 -       temp |= (u32) 160;
1474 +       /*
1475 +        * the increment interval is 8 times as much as that defined
1476 +        * in xHCI spec on MTK's controller
1477 +        */
1478 +       temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
1479         writel(temp, &xhci->ir_set->irq_control);
1480
1481         /* Set the HCD state before we enable the irqs */
1482 @@ -1704,6 +1709,9 @@ int xhci_drop_endpoint(struct usb_hcd *h
1483
1484         xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1485
1486 +       if (xhci->quirks & XHCI_MTK_HOST)
1487 +               xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1488 +
1489         xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1490                         (unsigned int) ep->desc.bEndpointAddress,
1491                         udev->slot_id,
1492 @@ -1799,6 +1807,15 @@ int xhci_add_endpoint(struct usb_hcd *hc
1493                 return -ENOMEM;
1494         }
1495
1496 +       if (xhci->quirks & XHCI_MTK_HOST) {
1497 +               ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1498 +               if (ret < 0) {
1499 +                       xhci_free_or_cache_endpoint_ring(xhci,
1500 +                               virt_dev, ep_index);
1501 +                       return ret;
1502 +               }
1503 +       }
1504 +
1505         ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1506         new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1507
1508 --- a/drivers/usb/host/xhci.h
1509 +++ b/drivers/usb/host/xhci.h
1510 @@ -1631,6 +1631,7 @@ struct xhci_hcd {
1511  /* For controllers with a broken beyond repair streams implementation */
1512  #define XHCI_BROKEN_STREAMS    (1 << 19)
1513  #define XHCI_PME_STUCK_QUIRK   (1 << 20)
1514 +#define XHCI_MTK_HOST          (1 << 21)
1515         unsigned int            num_active_eps;
1516         unsigned int            limit_active_eps;
1517         /* There are two roothubs to keep track of bus suspend info for */