31854eff4bcee429a3abdb860253ac5b8e862bad
[openwrt/openwrt.git] / target / linux / ramips / patches-4.4 / 0044-i2c-MIPS-adds-ralink-I2C-driver.patch
1 From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:52:56 +0100
4 Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
9 drivers/i2c/busses/Kconfig | 4 +
10 drivers/i2c/busses/Makefile | 1 +
11 drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++
12 4 files changed, 359 insertions(+)
13 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
14 create mode 100644 drivers/i2c/busses/i2c-ralink.c
15
16 --- /dev/null
17 +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
18 @@ -0,0 +1,27 @@
19 +I2C for Ralink platforms
20 +
21 +Required properties :
22 +- compatible : Must be "link,rt3052-i2c"
23 +- reg: physical base address of the controller and length of memory mapped
24 + region.
25 +- #address-cells = <1>;
26 +- #size-cells = <0>;
27 +
28 +Optional properties:
29 +- Child nodes conforming to i2c bus binding
30 +
31 +Example :
32 +
33 +palmbus@10000000 {
34 + i2c@900 {
35 + compatible = "link,rt3052-i2c";
36 + reg = <0x900 0x100>;
37 + #address-cells = <1>;
38 + #size-cells = <0>;
39 +
40 + hwmon@4b {
41 + compatible = "national,lm92";
42 + reg = <0x4b>;
43 + };
44 + };
45 +};
46 --- a/drivers/i2c/busses/Kconfig
47 +++ b/drivers/i2c/busses/Kconfig
48 @@ -806,6 +806,10 @@ config I2C_RK3X
49 This driver can also be built as a module. If so, the module will
50 be called i2c-rk3x.
51
52 +config I2C_RALINK
53 + tristate "Ralink I2C Controller"
54 + select OF_I2C
55 +
56 config HAVE_S3C2410_I2C
57 bool
58 help
59 --- a/drivers/i2c/busses/Makefile
60 +++ b/drivers/i2c/busses/Makefile
61 @@ -75,6 +75,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
62 obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
63 obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
64 obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
65 +obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
66 obj-$(CONFIG_I2C_QUP) += i2c-qup.o
67 obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
68 obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
69 --- /dev/null
70 +++ b/drivers/i2c/busses/i2c-ralink.c
71 @@ -0,0 +1,327 @@
72 +/*
73 + * drivers/i2c/busses/i2c-ralink.c
74 + *
75 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
76 + *
77 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
78 + * (C) 2014 Sittisak <sittisaks@hotmail.com>
79 + *
80 + * This software is licensed under the terms of the GNU General Public
81 + * License version 2, as published by the Free Software Foundation, and
82 + * may be copied, distributed, and modified under those terms.
83 + *
84 + * This program is distributed in the hope that it will be useful,
85 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
86 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
87 + * GNU General Public License for more details.
88 + *
89 + */
90 +
91 +#include <linux/interrupt.h>
92 +#include <linux/kernel.h>
93 +#include <linux/module.h>
94 +#include <linux/reset.h>
95 +#include <linux/delay.h>
96 +#include <linux/slab.h>
97 +#include <linux/init.h>
98 +#include <linux/errno.h>
99 +#include <linux/platform_device.h>
100 +#include <linux/of_platform.h>
101 +#include <linux/i2c.h>
102 +#include <linux/io.h>
103 +#include <linux/err.h>
104 +
105 +#include <asm/mach-ralink/ralink_regs.h>
106 +
107 +#define REG_CONFIG_REG 0x00
108 +#define REG_CLKDIV_REG 0x04
109 +#define REG_DEVADDR_REG 0x08
110 +#define REG_ADDR_REG 0x0C
111 +#define REG_DATAOUT_REG 0x10
112 +#define REG_DATAIN_REG 0x14
113 +#define REG_STATUS_REG 0x18
114 +#define REG_STARTXFR_REG 0x1C
115 +#define REG_BYTECNT_REG 0x20
116 +#define REG_SM0CFG2 0x28
117 +#define REG_SM0CTL0 0x40
118 +
119 +#define I2C_STARTERR BIT(4)
120 +#define I2C_ACKERR BIT(3)
121 +#define I2C_DATARDY BIT(2)
122 +#define I2C_SDOEMPTY BIT(1)
123 +#define I2C_BUSY BIT(0)
124 +
125 +#define I2C_DEVADLEN_7 (6 << 2)
126 +#define I2C_ADDRDIS BIT(1)
127 +
128 +#define CLKDIV_VALUE 200 // clock rate is 40M, 40M / (200*2) = 100k (standard i2c bus rate).
129 +//#define CLKDIV_VALUE 50 // clock rate is 40M, 40M / (50*2) = 400k (fast i2c bus rate).
130 +
131 +#define READ_CMD 0x01
132 +#define WRITE_CMD 0x00
133 +#define READ_BLOCK 64
134 +
135 +#define SM0CTL0_OD BIT(31)
136 +#define SM0CTL0_VTRIG BIT(28)
137 +#define SM0CTL0_OUTHI BIT(6)
138 +#define SM0CTL0_STRETCH BIT(1)
139 +#define SM0CTL0_DEFAULT (SM0CTL0_OD | SM0CTL0_VTRIG | SM0CTL0_OUTHI | SM0CTL0_STRETCH)
140 +
141 +/* timeout waiting for I2C devices to respond (clock streching) */
142 +#define RT_I2C_TIMEOUT (msecs_to_jiffies(1000))
143 +
144 +enum {
145 + I2C_TYPE_RALINK,
146 + I2C_TYPE_MEDIATEK,
147 +};
148 +
149 +static void __iomem *membase;
150 +static struct i2c_adapter *adapter;
151 +static int hw_type;
152 +
153 +static void rt_i2c_w32(u32 val, unsigned reg)
154 +{
155 + iowrite32(val, membase + reg);
156 +}
157 +
158 +static u32 rt_i2c_r32(unsigned reg)
159 +{
160 + return ioread32(membase + reg);
161 +}
162 +
163 +static inline int rt_i2c_get_ack(void)
164 +{
165 + return (rt_i2c_r32(REG_STATUS_REG) & I2C_ACKERR) ? -EIO : 0;
166 +}
167 +
168 +static inline int rt_i2c_wait_rx_done(void)
169 +{
170 + unsigned long timeout;
171 +
172 + timeout = jiffies + RT_I2C_TIMEOUT;
173 +
174 + do {
175 + if (time_after(jiffies, timeout))
176 + return (-ETIMEDOUT);
177 +
178 + } while (!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY));
179 +
180 + return 0;
181 +}
182 +
183 +static inline int rt_i2c_wait_idle(void)
184 +{
185 + unsigned long timeout;
186 +
187 + timeout = jiffies + RT_I2C_TIMEOUT;
188 +
189 + do {
190 + if (time_after(jiffies, timeout)) {
191 + printk("i2c-read line busy\n");
192 + return 1;
193 + }
194 + } while (rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY);
195 +
196 + return 0;
197 +}
198 +
199 +static inline int rt_i2c_wait_tx_done(void)
200 +{
201 + unsigned long timeout;
202 +
203 + timeout = jiffies + RT_I2C_TIMEOUT;
204 +
205 + do {
206 + if (time_after(jiffies, timeout))
207 + return (-ETIMEDOUT);
208 +
209 + } while (!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY));
210 +
211 + return 0;
212 +}
213 +
214 +static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
215 +{
216 + int i = 0, j = 0, pos = 0;
217 + int nblock = msg->len / READ_BLOCK;
218 + int rem = msg->len % READ_BLOCK;
219 + int ret = 0;
220 +
221 + if (msg->flags & I2C_M_TEN) {
222 + printk("10 bits addr not supported\n");
223 + return -EINVAL;
224 + }
225 +
226 + if (msg->flags & I2C_M_RD) {
227 + for (i = 0; i < nblock; i++) {
228 + if (rt_i2c_wait_idle())
229 + return -ETIMEDOUT;
230 + rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
231 + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
232 + for (j = 0; j < READ_BLOCK; j++) {
233 + if (rt_i2c_wait_rx_done() < 0)
234 + ret = rt_i2c_wait_rx_done();
235 + if (rt_i2c_get_ack() < 0)
236 + ret = rt_i2c_get_ack();
237 + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
238 + }
239 + }
240 +
241 + if (rt_i2c_wait_idle())
242 + return -ETIMEDOUT;
243 + if (rem) {
244 + rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
245 + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
246 + }
247 + for (i = 0; i < rem; i++) {
248 + if (rt_i2c_wait_rx_done() < 0)
249 + ret = rt_i2c_wait_rx_done();
250 + if (rt_i2c_get_ack() < 0)
251 + ret = rt_i2c_get_ack();
252 +
253 + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
254 + }
255 + } else {
256 + if (rt_i2c_wait_idle())
257 + return -ETIMEDOUT;
258 + rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
259 + for (i = 0; i < msg->len; i++) {
260 + rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
261 + rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
262 +
263 + if (rt_i2c_wait_tx_done() < 0)
264 + ret = rt_i2c_wait_tx_done();
265 + if (rt_i2c_get_ack() < 0)
266 + ret = rt_i2c_get_ack();
267 + }
268 + }
269 +
270 + return ret;
271 +}
272 +
273 +static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
274 +{
275 + int i = 0;
276 + int ret = 0;
277 +
278 + if (rt_i2c_wait_idle())
279 + return -ETIMEDOUT;
280 +
281 + device_reset(a->dev.parent);
282 +
283 + rt_i2c_w32(m->addr, REG_DEVADDR_REG);
284 + rt_i2c_w32(I2C_DEVADLEN_7 | I2C_ADDRDIS, REG_CONFIG_REG);
285 + if (hw_type == I2C_TYPE_RALINK) {
286 + rt_i2c_w32(CLKDIV_VALUE, REG_CLKDIV_REG);
287 + } else {
288 + rt_i2c_w32((CLKDIV_VALUE << 16) | SM0CTL0_DEFAULT, REG_SM0CTL0);
289 + rt_i2c_w32(1, REG_SM0CFG2);
290 + }
291 +
292 + for (i = 0; i < n && !ret; i++) {
293 + ret = rt_i2c_handle_msg(a, &m[i]);
294 +
295 + if (ret < 0) {
296 + return ret;
297 + }
298 + }
299 +
300 + return n;
301 +}
302 +
303 +static u32 rt_i2c_func(struct i2c_adapter *a)
304 +{
305 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
306 +}
307 +
308 +static const struct i2c_algorithm rt_i2c_algo = {
309 + .master_xfer = rt_i2c_master_xfer,
310 + .functionality = rt_i2c_func,
311 +};
312 +
313 +static const struct of_device_id i2c_rt_dt_ids[] = {
314 + { .compatible = "ralink,rt2880-i2c", .data = (void *) I2C_TYPE_RALINK },
315 + { .compatible = "mediatek,mt7628-i2c", .data = (void *) I2C_TYPE_MEDIATEK },
316 + { /* sentinel */ }
317 +};
318 +
319 +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
320 +
321 +static int rt_i2c_probe(struct platform_device *pdev)
322 +{
323 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
324 + const struct of_device_id *match;
325 + int ret;
326 +
327 + match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
328 + hw_type = (int) match->data;
329 +
330 + if (!res) {
331 + dev_err(&pdev->dev, "no memory resource found\n");
332 + return -ENODEV;
333 + }
334 +
335 + adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), GFP_KERNEL);
336 + if (!adapter) {
337 + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
338 + return -ENOMEM;
339 + }
340 +
341 + membase = devm_ioremap_resource(&pdev->dev, res);
342 + if (IS_ERR(membase))
343 + return PTR_ERR(membase);
344 +
345 + strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
346 + adapter->owner = THIS_MODULE;
347 + adapter->nr = pdev->id;
348 + adapter->timeout = HZ;
349 + adapter->algo = &rt_i2c_algo;
350 + adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
351 + adapter->dev.parent = &pdev->dev;
352 + adapter->dev.of_node = pdev->dev.of_node;
353 +
354 + ret = i2c_add_numbered_adapter(adapter);
355 + if (ret)
356 + return ret;
357 +
358 + platform_set_drvdata(pdev, adapter);
359 +
360 + dev_info(&pdev->dev, "loaded\n");
361 +
362 + return 0;
363 +}
364 +
365 +static int rt_i2c_remove(struct platform_device *pdev)
366 +{
367 + platform_set_drvdata(pdev, NULL);
368 +
369 + return 0;
370 +}
371 +
372 +static struct platform_driver rt_i2c_driver = {
373 + .probe = rt_i2c_probe,
374 + .remove = rt_i2c_remove,
375 + .driver = {
376 + .owner = THIS_MODULE,
377 + .name = "i2c-ralink",
378 + .of_match_table = i2c_rt_dt_ids,
379 + },
380 +};
381 +
382 +static int __init i2c_rt_init (void)
383 +{
384 + return platform_driver_register(&rt_i2c_driver);
385 +}
386 +subsys_initcall(i2c_rt_init);
387 +
388 +static void __exit i2c_rt_exit (void)
389 +{
390 + platform_driver_unregister(&rt_i2c_driver);
391 +}
392 +
393 +module_exit (i2c_rt_exit);
394 +
395 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
396 +MODULE_DESCRIPTION("Ralink I2c host driver");
397 +MODULE_LICENSE("GPL");
398 +MODULE_ALIAS("platform:Ralink-I2C");