3020cdb6b587d469954f9c9f0050afebf417648b
[openwrt/openwrt.git] / target / linux / ramips / patches-4.4 / 0080-MIPS-ralink-fix-USB-frequency-scaling.patch
1 From ae28413b3b8901ea00af3571e1c90d0228976e16 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 4 Jan 2016 20:23:57 +0100
4 Subject: [PATCH 80/81] MIPS: ralink: fix USB frequency scaling
5
6 Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully
7 correct. The logic for the SoC check got inverted. We need to check if it
8 is not a MT76x8.
9
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 Cc: linux-mips@linux-mips.org
12 Patchwork: https://patchwork.linux-mips.org/patch/11992/
13 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
14 ---
15 arch/mips/ralink/mt7620.c | 2 +-
16 1 file changed, 1 insertion(+), 1 deletion(-)
17
18 --- a/arch/mips/ralink/mt7620.c
19 +++ b/arch/mips/ralink/mt7620.c
20 @@ -442,7 +442,7 @@ void __init ralink_clk_init(void)
21 ralink_clk_add("10000e00.uart2", periph_rate);
22 ralink_clk_add("10180000.wmac", xtal_rate);
23
24 - if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
25 + if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
26 /*
27 * When the CPU goes into sleep mode, the BUS clock will be
28 * too low for USB to function properly. Adjust the busses