target/linux/ramips/patches-4.4/0508-net-next-mediatek-add-support-for-mt7620.patch

   1 From 1efca7b539a91c49ab1d6484ec3a69c48fa6062b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 14 Dec 2015 21:25:35 +0100
   4 Subject: [PATCH 508/513] net-next: mediatek: add support for mt7620
   5
   6 Add support for SoCs from the mt7620 family. This include mt7620 and mt7621.
   7 These all have one dedicated external gbit port and a builtin 5 port 100mbit
   8 switch. Additionally one of the 5 switch ports can be changed to become an
   9 additional gbit port that we can attach a phy to. This patch includes
  10 rudimentary code to power up the switch. There are a lot of magic values
  11 that get written to the switch and the internal phys. These values come
  12 straight from the SDK driver.
  13
  14 Signed-off-by: John Crispin <blogic@openwrt.org>
  15 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  16 Signed-off-by: Michael Lee <igvtee@gmail.com>
  17 ---
  18  drivers/net/ethernet/mediatek/mdio_mt7620.c |  156 +++++++++++++
  19  drivers/net/ethernet/mediatek/soc_mt7620.c  |  334 +++++++++++++++++++++++++++
  20  2 files changed, 490 insertions(+)
  21  create mode 100644 drivers/net/ethernet/mediatek/mdio_mt7620.c
  22  create mode 100644 drivers/net/ethernet/mediatek/soc_mt7620.c
  23
  24 --- /dev/null
  25 +++ b/drivers/net/ethernet/mediatek/mdio_mt7620.c
  26 @@ -0,0 +1,156 @@
  27 +/*   This program is free software; you can redistribute it and/or modify
  28 + *   it under the terms of the GNU General Public License as published by
  29 + *   the Free Software Foundation; version 2 of the License
  30 + *
  31 + *   This program is distributed in the hope that it will be useful,
  32 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  33 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34 + *   GNU General Public License for more details.
  35 + *
  36 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  37 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  38 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  39 + */
  40 +
  41 +#include <linux/module.h>
  42 +#include <linux/kernel.h>
  43 +#include <linux/types.h>
  44 +
  45 +#include "mtk_eth_soc.h"
  46 +#include "gsw_mt7620.h"
  47 +#include "mdio.h"
  48 +
  49 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
  50 +{
  51 +       unsigned long t_start = jiffies;
  52 +
  53 +       while (1) {
  54 +               if (!(mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
  55 +                       return 0;
  56 +               if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))
  57 +                       break;
  58 +       }
  59 +
  60 +       dev_err(gsw->dev, "mdio: MDIO timeout\n");
  61 +       return -1;
  62 +}
  63 +
  64 +u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
  65 +                            u32 phy_register, u32 write_data)
  66 +{
  67 +       if (mt7620_mii_busy_wait(gsw))
  68 +               return -1;
  69 +
  70 +       write_data &= 0xffff;
  71 +
  72 +       mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
  73 +               (phy_register << GSW_MDIO_REG_SHIFT) |
  74 +               (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
  75 +               MT7620A_GSW_REG_PIAC);
  76 +
  77 +       if (mt7620_mii_busy_wait(gsw))
  78 +               return -1;
  79 +
  80 +       return 0;
  81 +}
  82 +
  83 +u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
  84 +{
  85 +       u32 d;
  86 +
  87 +       if (mt7620_mii_busy_wait(gsw))
  88 +               return 0xffff;
  89 +
  90 +       mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
  91 +               (phy_reg << GSW_MDIO_REG_SHIFT) |
  92 +               (phy_addr << GSW_MDIO_ADDR_SHIFT),
  93 +               MT7620A_GSW_REG_PIAC);
  94 +
  95 +       if (mt7620_mii_busy_wait(gsw))
  96 +               return 0xffff;
  97 +
  98 +       d = mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
  99 +
 100 +       return d;
 101 +}
 102 +
 103 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
 104 +{
 105 +       struct fe_priv *priv = bus->priv;
 106 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 107 +
 108 +       return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
 109 +}
 110 +
 111 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
 112 +{
 113 +       struct fe_priv *priv = bus->priv;
 114 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 115 +
 116 +       return _mt7620_mii_read(gsw, phy_addr, phy_reg);
 117 +}
 118 +
 119 +void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
 120 +{
 121 +       _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
 122 +       _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
 123 +       _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
 124 +}
 125 +
 126 +u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
 127 +{
 128 +       u16 high, low;
 129 +
 130 +       _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
 131 +       low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
 132 +       high = _mt7620_mii_read(gsw, 0x1f, 0x10);
 133 +
 134 +       return (high << 16) | (low & 0xffff);
 135 +}
 136 +
 137 +static unsigned char *fe_speed_str(int speed)
 138 +{
 139 +       switch (speed) {
 140 +       case 2:
 141 +       case SPEED_1000:
 142 +               return "1000";
 143 +       case 1:
 144 +       case SPEED_100:
 145 +               return "100";
 146 +       case 0:
 147 +       case SPEED_10:
 148 +               return "10";
 149 +       }
 150 +
 151 +       return "? ";
 152 +}
 153 +
 154 +int mt7620_has_carrier(struct fe_priv *priv)
 155 +{
 156 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 157 +       int i;
 158 +
 159 +       for (i = 0; i < GSW_PORT6; i++)
 160 +               if (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
 161 +                       return 1;
 162 +       return 0;
 163 +}
 164 +
 165 +
 166 +void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
 167 +                            int speed, int duplex)
 168 +{
 169 +       if (link)
 170 +               netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
 171 +                           port, fe_speed_str(speed),
 172 +                           (duplex) ? "Full" : "Half");
 173 +       else
 174 +               netdev_info(priv->netdev, "port %d link down\n", port);
 175 +}
 176 +
 177 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
 178 +{
 179 +       mt7620_print_link_state(priv, port, priv->link[port],
 180 +                               priv->phy->speed[port],
 181 +                               (priv->phy->duplex[port] == DUPLEX_FULL));
 182 +}
 183 --- /dev/null
 184 +++ b/drivers/net/ethernet/mediatek/soc_mt7620.c
 185 @@ -0,0 +1,334 @@
 186 +/*   This program is free software; you can redistribute it and/or modify
 187 + *   it under the terms of the GNU General Public License as published by
 188 + *   the Free Software Foundation; version 2 of the License
 189 + *
 190 + *   This program is distributed in the hope that it will be useful,
 191 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 192 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 193 + *   GNU General Public License for more details.
 194 + *
 195 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
 196 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
 197 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
 198 + */
 199 +
 200 +#include <linux/module.h>
 201 +#include <linux/platform_device.h>
 202 +#include <linux/if_vlan.h>
 203 +#include <linux/of_net.h>
 204 +
 205 +#include <asm/mach-ralink/ralink_regs.h>
 206 +
 207 +#include <mt7620.h>
 208 +#include "mtk_eth_soc.h"
 209 +#include "gsw_mt7620.h"
 210 +#include "mt7530.h"
 211 +#include "mdio.h"
 212 +
 213 +#define MT7620A_CDMA_CSG_CFG   0x400
 214 +#define MT7620_DMA_VID         (MT7620A_CDMA_CSG_CFG | 0x30)
 215 +#define MT7621_CDMP_IG_CTRL    (MT7620A_CDMA_CSG_CFG + 0x00)
 216 +#define MT7621_CDMP_EG_CTRL    (MT7620A_CDMA_CSG_CFG + 0x04)
 217 +#define MT7620A_RESET_FE       BIT(21)
 218 +#define MT7621_RESET_FE                BIT(6)
 219 +#define MT7620A_RESET_ESW      BIT(23)
 220 +#define MT7620_L4_VALID                BIT(23)
 221 +#define MT7621_L4_VALID                BIT(24)
 222 +
 223 +#define MT7620_TX_DMA_UDF      BIT(15)
 224 +#define MT7621_TX_DMA_UDF      BIT(19)
 225 +#define TX_DMA_FP_BMAP         ((0xff) << 19)
 226 +
 227 +#define CDMA_ICS_EN            BIT(2)
 228 +#define CDMA_UCS_EN            BIT(1)
 229 +#define CDMA_TCS_EN            BIT(0)
 230 +
 231 +#define GDMA_ICS_EN            BIT(22)
 232 +#define GDMA_TCS_EN            BIT(21)
 233 +#define GDMA_UCS_EN            BIT(20)
 234 +
 235 +/* frame engine counters */
 236 +#define MT7620_REG_MIB_OFFSET  0x1000
 237 +#define MT7620_PPE_AC_BCNT0    (MT7620_REG_MIB_OFFSET + 0x00)
 238 +#define MT7620_GDM1_TX_GBCNT   (MT7620_REG_MIB_OFFSET + 0x300)
 239 +#define MT7620_GDM2_TX_GBCNT   (MT7620_GDM1_TX_GBCNT + 0x40)
 240 +
 241 +#define MT7621_REG_MIB_OFFSET  0x2000
 242 +#define MT7621_PPE_AC_BCNT0    (MT7621_REG_MIB_OFFSET + 0x00)
 243 +#define MT7621_GDM1_TX_GBCNT   (MT7621_REG_MIB_OFFSET + 0x400)
 244 +#define MT7621_GDM2_TX_GBCNT   (MT7621_GDM1_TX_GBCNT + 0x40)
 245 +
 246 +#define GSW_REG_GDMA1_MAC_ADRL 0x508
 247 +#define GSW_REG_GDMA1_MAC_ADRH 0x50C
 248 +
 249 +#define MT7621_FE_RST_GL       (FE_FE_OFFSET + 0x04)
 250 +#define MT7620_FE_INT_STATUS2  (FE_FE_OFFSET + 0x08)
 251 +
 252 +/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
 253 + * but after test it should be BIT(13).
 254 + */
 255 +#define MT7620_FE_GDM1_AF      BIT(13)
 256 +#define MT7621_FE_GDM1_AF      BIT(28)
 257 +#define MT7621_FE_GDM2_AF      BIT(29)
 258 +
 259 +static const u16 mt7620_reg_table[FE_REG_COUNT] = {
 260 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
 261 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
 262 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
 263 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
 264 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
 265 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
 266 +       [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
 267 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
 268 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
 269 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
 270 +       [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
 271 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
 272 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
 273 +       [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
 274 +       [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
 275 +       [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
 276 +       [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
 277 +};
 278 +
 279 +static int mt7620_gsw_config(struct fe_priv *priv)
 280 +{
 281 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 282 +
 283 +       /* is the mt7530 internal or external */
 284 +       if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
 285 +               mt7530_probe(priv->device, gsw->base, NULL, 0);
 286 +               mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
 287 +       } else {
 288 +               mt7530_probe(priv->device, gsw->base, NULL, 1);
 289 +       }
 290 +
 291 +       return 0;
 292 +}
 293 +
 294 +static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
 295 +{
 296 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 297 +       unsigned long flags;
 298 +
 299 +       spin_lock_irqsave(&priv->page_lock, flags);
 300 +       mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 301 +       mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 302 +               GSW_REG_SMACCR0);
 303 +       spin_unlock_irqrestore(&priv->page_lock, flags);
 304 +}
 305 +
 306 +static void mt7620_auto_poll(struct mt7620_gsw *gsw)
 307 +{
 308 +       int phy;
 309 +       int lsb = -1, msb = 0;
 310 +
 311 +       for_each_set_bit(phy, &gsw->autopoll, 32) {
 312 +               if (lsb < 0)
 313 +                       lsb = phy;
 314 +               msb = phy;
 315 +       }
 316 +
 317 +       if (lsb == msb)
 318 +               lsb--;
 319 +
 320 +       mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
 321 +               (msb << 8) | lsb, ESW_PHY_POLLING);
 322 +}
 323 +
 324 +static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 325 +{
 326 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 327 +       const __be32 *_id = of_get_property(np, "reg", NULL);
 328 +       int phy_mode, size, id;
 329 +       int shift = 12;
 330 +       u32 val, mask = 0;
 331 +       int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
 332 +
 333 +       if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 334 +               if (_id)
 335 +                       pr_err("%s: invalid port id %d\n", np->name,
 336 +                              be32_to_cpu(*_id));
 337 +               else
 338 +                       pr_err("%s: invalid port id\n", np->name);
 339 +               return;
 340 +       }
 341 +
 342 +       id = be32_to_cpu(*_id);
 343 +
 344 +       if (id == 4)
 345 +               shift = 14;
 346 +
 347 +       priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
 348 +                                                  &size);
 349 +       if (priv->phy->phy_fixed[id] &&
 350 +           (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 351 +               pr_err("%s: invalid fixed link property\n", np->name);
 352 +               priv->phy->phy_fixed[id] = NULL;
 353 +               return;
 354 +       }
 355 +
 356 +       phy_mode = of_get_phy_mode(np);
 357 +       switch (phy_mode) {
 358 +       case PHY_INTERFACE_MODE_RGMII:
 359 +               mask = 0;
 360 +               break;
 361 +       case PHY_INTERFACE_MODE_MII:
 362 +               mask = 1;
 363 +               break;
 364 +       case PHY_INTERFACE_MODE_RMII:
 365 +               mask = 2;
 366 +               break;
 367 +       default:
 368 +               dev_err(priv->device, "port %d - invalid phy mode\n", id);
 369 +               return;
 370 +       }
 371 +
 372 +       priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 373 +       if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
 374 +               return;
 375 +
 376 +       val = rt_sysc_r32(SYSC_REG_CFG1);
 377 +       val &= ~(3 << shift);
 378 +       val |= mask << shift;
 379 +       rt_sysc_w32(val, SYSC_REG_CFG1);
 380 +
 381 +       if (priv->phy->phy_fixed[id]) {
 382 +               const __be32 *link = priv->phy->phy_fixed[id];
 383 +               int tx_fc, rx_fc;
 384 +               u32 val = 0;
 385 +
 386 +               priv->phy->speed[id] = be32_to_cpup(link++);
 387 +               tx_fc = be32_to_cpup(link++);
 388 +               rx_fc = be32_to_cpup(link++);
 389 +               priv->phy->duplex[id] = be32_to_cpup(link++);
 390 +               priv->link[id] = 1;
 391 +
 392 +               switch (priv->phy->speed[id]) {
 393 +               case SPEED_10:
 394 +                       val = 0;
 395 +                       break;
 396 +               case SPEED_100:
 397 +                       val = 1;
 398 +                       break;
 399 +               case SPEED_1000:
 400 +                       val = 2;
 401 +                       break;
 402 +               default:
 403 +                       dev_err(priv->device, "invalid link speed: %d\n",
 404 +                               priv->phy->speed[id]);
 405 +                       priv->phy->phy_fixed[id] = 0;
 406 +                       return;
 407 +               }
 408 +               val = PMCR_SPEED(val);
 409 +               val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 410 +                       PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 411 +               if (tx_fc)
 412 +                       val |= PMCR_TX_FC;
 413 +               if (rx_fc)
 414 +                       val |= PMCR_RX_FC;
 415 +               if (priv->phy->duplex[id])
 416 +                       val |= PMCR_DUPLEX;
 417 +               mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 418 +               dev_info(priv->device, "using fixed link parameters\n");
 419 +               return;
 420 +       }
 421 +
 422 +       if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
 423 +               u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 424 +                       PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 425 +
 426 +               mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 427 +               fe_connect_phy_node(priv, priv->phy->phy_node[id]);
 428 +               gsw->autopoll |= BIT(id);
 429 +               mt7620_auto_poll(gsw);
 430 +               return;
 431 +       }
 432 +}
 433 +
 434 +static void mt7620_fe_reset(void)
 435 +{
 436 +       fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
 437 +}
 438 +
 439 +static void mt7620_rxcsum_config(bool enable)
 440 +{
 441 +       if (enable)
 442 +               fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
 443 +                                       GDMA_TCS_EN | GDMA_UCS_EN),
 444 +                               MT7620A_GDMA1_FWD_CFG);
 445 +       else
 446 +               fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 447 +                                       GDMA_TCS_EN | GDMA_UCS_EN),
 448 +                               MT7620A_GDMA1_FWD_CFG);
 449 +}
 450 +
 451 +static void mt7620_txcsum_config(bool enable)
 452 +{
 453 +       if (enable)
 454 +               fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 455 +                                       CDMA_UCS_EN | CDMA_TCS_EN),
 456 +                               MT7620A_CDMA_CSG_CFG);
 457 +       else
 458 +               fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 459 +                                       CDMA_UCS_EN | CDMA_TCS_EN),
 460 +                               MT7620A_CDMA_CSG_CFG);
 461 +}
 462 +
 463 +static int mt7620_fwd_config(struct fe_priv *priv)
 464 +{
 465 +       struct net_device *dev = priv_netdev(priv);
 466 +
 467 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 468 +
 469 +       mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 470 +       mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 471 +
 472 +       return 0;
 473 +}
 474 +
 475 +static void mt7620_tx_dma(struct fe_tx_dma *txd)
 476 +{
 477 +}
 478 +
 479 +static void mt7620_init_data(struct fe_soc_data *data,
 480 +                            struct net_device *netdev)
 481 +{
 482 +       struct fe_priv *priv = netdev_priv(netdev);
 483 +
 484 +       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
 485 +               FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
 486 +
 487 +       netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 488 +               NETIF_F_HW_VLAN_CTAG_TX;
 489 +       if (mt7620_get_eco() >= 5)
 490 +               netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 491 +                       NETIF_F_IPV6_CSUM;
 492 +}
 493 +
 494 +static struct fe_soc_data mt7620_data = {
 495 +       .init_data = mt7620_init_data,
 496 +       .reset_fe = mt7620_fe_reset,
 497 +       .set_mac = mt7620_set_mac,
 498 +       .fwd_config = mt7620_fwd_config,
 499 +       .tx_dma = mt7620_tx_dma,
 500 +       .switch_init = mtk_gsw_init,
 501 +       .port_init = mt7620_port_init,
 502 +       .reg_table = mt7620_reg_table,
 503 +       .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
 504 +       .rx_int = RT5350_RX_DONE_INT,
 505 +       .tx_int = RT5350_TX_DONE_INT,
 506 +       .status_int = MT7620_FE_GDM1_AF,
 507 +       .checksum_bit = MT7620_L4_VALID,
 508 +       .has_carrier = mt7620_has_carrier,
 509 +       .mdio_read = mt7620_mdio_read,
 510 +       .mdio_write = mt7620_mdio_write,
 511 +       .mdio_adjust_link = mt7620_mdio_link_adjust,
 512 +};
 513 +
 514 +const struct of_device_id of_fe_match[] = {
 515 +       { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
 516 +       {},
 517 +};
 518 +
 519 +MODULE_DEVICE_TABLE(of, of_fe_match);