ramips: switch to linux 4.14
[openwrt/openwrt.git] / target / linux / ramips / patches-4.9 / 0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch
1 From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 4 Aug 2014 20:36:29 +0200
4 Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
5
6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
8
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Cc: linux-mips@linux-mips.org
11 Cc: linux-gpio@vger.kernel.org
12 ---
13 arch/mips/include/asm/mach-ralink/gpio.h | 24 ++
14 drivers/gpio/Kconfig | 6 +
15 drivers/gpio/Makefile | 1 +
16 drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++
17 4 files changed, 386 insertions(+)
18 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
19 create mode 100644 drivers/gpio/gpio-ralink.c
20
21 --- /dev/null
22 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
23 @@ -0,0 +1,24 @@
24 +/*
25 + * Ralink SoC GPIO API support
26 + *
27 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
28 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
29 + *
30 + * This program is free software; you can redistribute it and/or modify it
31 + * under the terms of the GNU General Public License version 2 as published
32 + * by the Free Software Foundation.
33 + *
34 + */
35 +
36 +#ifndef __ASM_MACH_RALINK_GPIO_H
37 +#define __ASM_MACH_RALINK_GPIO_H
38 +
39 +#define ARCH_NR_GPIOS 128
40 +#include <asm-generic/gpio.h>
41 +
42 +#define gpio_get_value __gpio_get_value
43 +#define gpio_set_value __gpio_set_value
44 +#define gpio_cansleep __gpio_cansleep
45 +#define gpio_to_irq __gpio_to_irq
46 +
47 +#endif /* __ASM_MACH_RALINK_GPIO_H */
48 --- a/drivers/gpio/Kconfig
49 +++ b/drivers/gpio/Kconfig
50 @@ -369,6 +369,12 @@ config GPIO_RCAR
51 help
52 Say yes here to support GPIO on Renesas R-Car SoCs.
53
54 +config GPIO_RALINK
55 + bool "Ralink GPIO Support"
56 + depends on RALINK
57 + help
58 + Say yes here to support the Ralink SoC GPIO device
59 +
60 config GPIO_SPEAR_SPICS
61 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
62 depends on PLAT_SPEAR
63 --- a/drivers/gpio/Makefile
64 +++ b/drivers/gpio/Makefile
65 @@ -91,6 +91,7 @@ obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
66 obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o
67 obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
68 obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
69 +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
70 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
71 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
72 obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
73 --- /dev/null
74 +++ b/drivers/gpio/gpio-ralink.c
75 @@ -0,0 +1,355 @@
76 +/*
77 + * This program is free software; you can redistribute it and/or modify it
78 + * under the terms of the GNU General Public License version 2 as published
79 + * by the Free Software Foundation.
80 + *
81 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
82 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
83 + */
84 +
85 +#include <linux/module.h>
86 +#include <linux/io.h>
87 +#include <linux/gpio.h>
88 +#include <linux/spinlock.h>
89 +#include <linux/platform_device.h>
90 +#include <linux/of_irq.h>
91 +#include <linux/irqdomain.h>
92 +#include <linux/interrupt.h>
93 +
94 +enum ralink_gpio_reg {
95 + GPIO_REG_INT = 0,
96 + GPIO_REG_EDGE,
97 + GPIO_REG_RENA,
98 + GPIO_REG_FENA,
99 + GPIO_REG_DATA,
100 + GPIO_REG_DIR,
101 + GPIO_REG_POL,
102 + GPIO_REG_SET,
103 + GPIO_REG_RESET,
104 + GPIO_REG_TOGGLE,
105 + GPIO_REG_MAX
106 +};
107 +
108 +struct ralink_gpio_chip {
109 + struct gpio_chip chip;
110 + u8 regs[GPIO_REG_MAX];
111 +
112 + spinlock_t lock;
113 + void __iomem *membase;
114 + struct irq_domain *domain;
115 + int irq;
116 +
117 + u32 rising;
118 + u32 falling;
119 +};
120 +
121 +#define MAP_MAX 4
122 +static struct irq_domain *irq_map[MAP_MAX];
123 +static int irq_map_count;
124 +static atomic_t irq_refcount = ATOMIC_INIT(0);
125 +
126 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
127 +{
128 + struct ralink_gpio_chip *rg;
129 +
130 + rg = container_of(chip, struct ralink_gpio_chip, chip);
131 +
132 + return rg;
133 +}
134 +
135 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
136 +{
137 + iowrite32(val, rg->membase + rg->regs[reg]);
138 +}
139 +
140 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
141 +{
142 + return ioread32(rg->membase + rg->regs[reg]);
143 +}
144 +
145 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
146 +{
147 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
148 +
149 + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
150 +}
151 +
152 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
153 +{
154 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
155 +
156 + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
157 +}
158 +
159 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
160 +{
161 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
162 + unsigned long flags;
163 + u32 t;
164 +
165 + spin_lock_irqsave(&rg->lock, flags);
166 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
167 + t &= ~BIT(offset);
168 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
169 + spin_unlock_irqrestore(&rg->lock, flags);
170 +
171 + return 0;
172 +}
173 +
174 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
175 + unsigned offset, int value)
176 +{
177 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
178 + unsigned long flags;
179 + u32 t;
180 +
181 + spin_lock_irqsave(&rg->lock, flags);
182 + ralink_gpio_set(chip, offset, value);
183 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
184 + t |= BIT(offset);
185 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
186 + spin_unlock_irqrestore(&rg->lock, flags);
187 +
188 + return 0;
189 +}
190 +
191 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
192 +{
193 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
194 +
195 + if (rg->irq < 1)
196 + return -1;
197 +
198 + return irq_create_mapping(rg->domain, pin);
199 +}
200 +
201 +static void ralink_gpio_irq_handler(struct irq_desc *desc)
202 +{
203 + int i;
204 +
205 + for (i = 0; i < irq_map_count; i++) {
206 + struct irq_domain *domain = irq_map[i];
207 + struct ralink_gpio_chip *rg;
208 + unsigned long pending;
209 + int bit;
210 +
211 + rg = (struct ralink_gpio_chip *) domain->host_data;
212 + pending = rt_gpio_r32(rg, GPIO_REG_INT);
213 +
214 + for_each_set_bit(bit, &pending, rg->chip.ngpio) {
215 + u32 map = irq_find_mapping(domain, bit);
216 + generic_handle_irq(map);
217 + rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
218 + }
219 + }
220 +}
221 +
222 +static void ralink_gpio_irq_unmask(struct irq_data *d)
223 +{
224 + struct ralink_gpio_chip *rg;
225 + unsigned long flags;
226 + u32 rise, fall;
227 +
228 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
229 + rise = rt_gpio_r32(rg, GPIO_REG_RENA);
230 + fall = rt_gpio_r32(rg, GPIO_REG_FENA);
231 +
232 + spin_lock_irqsave(&rg->lock, flags);
233 + rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
234 + rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
235 + spin_unlock_irqrestore(&rg->lock, flags);
236 +}
237 +
238 +static void ralink_gpio_irq_mask(struct irq_data *d)
239 +{
240 + struct ralink_gpio_chip *rg;
241 + unsigned long flags;
242 + u32 rise, fall;
243 +
244 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
245 + rise = rt_gpio_r32(rg, GPIO_REG_RENA);
246 + fall = rt_gpio_r32(rg, GPIO_REG_FENA);
247 +
248 + spin_lock_irqsave(&rg->lock, flags);
249 + rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
250 + rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
251 + spin_unlock_irqrestore(&rg->lock, flags);
252 +}
253 +
254 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
255 +{
256 + struct ralink_gpio_chip *rg;
257 + u32 mask = BIT(d->hwirq);
258 +
259 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
260 +
261 + if (type == IRQ_TYPE_PROBE) {
262 + if ((rg->rising | rg->falling) & mask)
263 + return 0;
264 +
265 + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
266 + }
267 +
268 + if (type & IRQ_TYPE_EDGE_RISING)
269 + rg->rising |= mask;
270 + else
271 + rg->rising &= ~mask;
272 +
273 + if (type & IRQ_TYPE_EDGE_FALLING)
274 + rg->falling |= mask;
275 + else
276 + rg->falling &= ~mask;
277 +
278 + return 0;
279 +}
280 +
281 +static struct irq_chip ralink_gpio_irq_chip = {
282 + .name = "GPIO",
283 + .irq_unmask = ralink_gpio_irq_unmask,
284 + .irq_mask = ralink_gpio_irq_mask,
285 + .irq_mask_ack = ralink_gpio_irq_mask,
286 + .irq_set_type = ralink_gpio_irq_type,
287 +};
288 +
289 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
290 +{
291 + irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
292 + irq_set_handler_data(irq, d);
293 +
294 + return 0;
295 +}
296 +
297 +static const struct irq_domain_ops irq_domain_ops = {
298 + .xlate = irq_domain_xlate_onecell,
299 + .map = gpio_map,
300 +};
301 +
302 +static void ralink_gpio_irq_init(struct device_node *np,
303 + struct ralink_gpio_chip *rg)
304 +{
305 + if (irq_map_count >= MAP_MAX)
306 + return;
307 +
308 + rg->irq = irq_of_parse_and_map(np, 0);
309 + if (!rg->irq)
310 + return;
311 +
312 + rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
313 + &irq_domain_ops, rg);
314 + if (!rg->domain) {
315 + dev_err(rg->chip.parent, "irq_domain_add_linear failed\n");
316 + return;
317 + }
318 +
319 + irq_map[irq_map_count++] = rg->domain;
320 +
321 + rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
322 + rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
323 +
324 + if (!atomic_read(&irq_refcount))
325 + irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
326 + atomic_inc(&irq_refcount);
327 +
328 + dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio);
329 +}
330 +
331 +static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
332 +{
333 + int gpio = chip->base + offset;
334 +
335 + return pinctrl_request_gpio(gpio);
336 +}
337 +
338 +static void ralink_gpio_free(struct gpio_chip *chip, unsigned offset)
339 +{
340 + int gpio = chip->base + offset;
341 +
342 + pinctrl_free_gpio(gpio);
343 +}
344 +
345 +static int ralink_gpio_probe(struct platform_device *pdev)
346 +{
347 + struct device_node *np = pdev->dev.of_node;
348 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
349 + struct ralink_gpio_chip *rg;
350 + const __be32 *ngpio, *gpiobase;
351 +
352 + if (!res) {
353 + dev_err(&pdev->dev, "failed to find resource\n");
354 + return -ENOMEM;
355 + }
356 +
357 + rg = devm_kzalloc(&pdev->dev,
358 + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
359 + if (!rg)
360 + return -ENOMEM;
361 +
362 + rg->membase = devm_ioremap_resource(&pdev->dev, res);
363 + if (!rg->membase) {
364 + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
365 + return -ENOMEM;
366 + }
367 +
368 + if (of_property_read_u8_array(np, "ralink,register-map",
369 + rg->regs, GPIO_REG_MAX)) {
370 + dev_err(&pdev->dev, "failed to read register definition\n");
371 + return -EINVAL;
372 + }
373 +
374 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
375 + if (!ngpio) {
376 + dev_err(&pdev->dev, "failed to read number of pins\n");
377 + return -EINVAL;
378 + }
379 +
380 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
381 + if (gpiobase)
382 + rg->chip.base = be32_to_cpu(*gpiobase);
383 + else
384 + rg->chip.base = -1;
385 +
386 + spin_lock_init(&rg->lock);
387 +
388 + rg->chip.parent = &pdev->dev;
389 + rg->chip.label = dev_name(&pdev->dev);
390 + rg->chip.of_node = np;
391 + rg->chip.ngpio = be32_to_cpu(*ngpio);
392 + rg->chip.direction_input = ralink_gpio_direction_input;
393 + rg->chip.direction_output = ralink_gpio_direction_output;
394 + rg->chip.get = ralink_gpio_get;
395 + rg->chip.set = ralink_gpio_set;
396 + rg->chip.request = ralink_gpio_request;
397 + rg->chip.to_irq = ralink_gpio_to_irq;
398 + rg->chip.free = ralink_gpio_free;
399 +
400 + /* set polarity to low for all lines */
401 + rt_gpio_w32(rg, GPIO_REG_POL, 0);
402 +
403 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
404 +
405 + ralink_gpio_irq_init(np, rg);
406 +
407 + return gpiochip_add(&rg->chip);
408 +}
409 +
410 +static const struct of_device_id ralink_gpio_match[] = {
411 + { .compatible = "ralink,rt2880-gpio" },
412 + {},
413 +};
414 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
415 +
416 +static struct platform_driver ralink_gpio_driver = {
417 + .probe = ralink_gpio_probe,
418 + .driver = {
419 + .name = "rt2880_gpio",
420 + .owner = THIS_MODULE,
421 + .of_match_table = ralink_gpio_match,
422 + },
423 +};
424 +
425 +static int __init ralink_gpio_init(void)
426 +{
427 + return platform_driver_register(&ralink_gpio_driver);
428 +}
429 +
430 +subsys_initcall(ralink_gpio_init);