target/linux/ramips/patches-4.9/0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch

   1 From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 11:15:12 +0100
   4 Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver
   5
   6 Add the driver needed to make SPI work on Ralink SoC.
   7
   8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   9 Acked-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  drivers/spi/Kconfig      |    6 +
  12  drivers/spi/Makefile     |    1 +
  13  drivers/spi/spi-rt2880.c |  530 ++++++++++++++++++++++++++++++++++++++++++++++
  14  3 files changed, 537 insertions(+)
  15  create mode 100644 drivers/spi/spi-rt2880.c
  16
  17 --- a/drivers/spi/Kconfig
  18 +++ b/drivers/spi/Kconfig
  19 @@ -533,6 +533,12 @@ config SPI_QUP
  20           This driver can also be built as a module.  If so, the module
  21           will be called spi_qup.
  22
  23 +config SPI_RT2880
  24 +       tristate "Ralink RT288x SPI Controller"
  25 +       depends on RALINK
  26 +       help
  27 +         This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  28 +
  29  config SPI_S3C24XX
  30         tristate "Samsung S3C24XX series SPI"
  31         depends on ARCH_S3C24XX
  32 --- a/drivers/spi/Makefile
  33 +++ b/drivers/spi/Makefile
  34 @@ -76,6 +76,7 @@ obj-$(CONFIG_SPI_QUP)                 += spi-qup.o
  35  obj-$(CONFIG_SPI_ROCKCHIP)             += spi-rockchip.o
  36  obj-$(CONFIG_SPI_RB4XX)                        += spi-rb4xx.o
  37  obj-$(CONFIG_SPI_RSPI)                 += spi-rspi.o
  38 +obj-$(CONFIG_SPI_RT2880)               += spi-rt2880.o
  39  obj-$(CONFIG_SPI_S3C24XX)              += spi-s3c24xx-hw.o
  40  spi-s3c24xx-hw-y                       := spi-s3c24xx.o
  41  spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
  42 --- /dev/null
  43 +++ b/drivers/spi/spi-rt2880.c
  44 @@ -0,0 +1,530 @@
  45 +/*
  46 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
  47 + *
  48 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  49 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  50 + *
  51 + * Some parts are based on spi-orion.c:
  52 + *   Author: Shadi Ammouri <shadi@marvell.com>
  53 + *   Copyright (C) 2007-2008 Marvell Ltd.
  54 + *
  55 + * This program is free software; you can redistribute it and/or modify
  56 + * it under the terms of the GNU General Public License version 2 as
  57 + * published by the Free Software Foundation.
  58 + */
  59 +
  60 +#include <linux/init.h>
  61 +#include <linux/module.h>
  62 +#include <linux/clk.h>
  63 +#include <linux/err.h>
  64 +#include <linux/delay.h>
  65 +#include <linux/io.h>
  66 +#include <linux/reset.h>
  67 +#include <linux/spi/spi.h>
  68 +#include <linux/platform_device.h>
  69 +#include <linux/gpio.h>
  70 +
  71 +#define DRIVER_NAME                    "spi-rt2880"
  72 +
  73 +#define RAMIPS_SPI_STAT                        0x00
  74 +#define RAMIPS_SPI_CFG                 0x10
  75 +#define RAMIPS_SPI_CTL                 0x14
  76 +#define RAMIPS_SPI_DATA                        0x20
  77 +#define RAMIPS_SPI_ADDR                        0x24
  78 +#define RAMIPS_SPI_BS                  0x28
  79 +#define RAMIPS_SPI_USER                        0x2C
  80 +#define RAMIPS_SPI_TXFIFO              0x30
  81 +#define RAMIPS_SPI_RXFIFO              0x34
  82 +#define RAMIPS_SPI_FIFO_STAT           0x38
  83 +#define RAMIPS_SPI_MODE                        0x3C
  84 +#define RAMIPS_SPI_DEV_OFFSET          0x40
  85 +#define RAMIPS_SPI_DMA                 0x80
  86 +#define RAMIPS_SPI_DMASTAT             0x84
  87 +#define RAMIPS_SPI_ARBITER             0xF0
  88 +
  89 +/* SPISTAT register bit field */
  90 +#define SPISTAT_BUSY                   BIT(0)
  91 +
  92 +/* SPICFG register bit field */
  93 +#define SPICFG_ADDRMODE                        BIT(12)
  94 +#define SPICFG_RXENVDIS                        BIT(11)
  95 +#define SPICFG_RXCAP                   BIT(10)
  96 +#define SPICFG_SPIENMODE               BIT(9)
  97 +#define SPICFG_MSBFIRST                        BIT(8)
  98 +#define SPICFG_SPICLKPOL               BIT(6)
  99 +#define SPICFG_RXCLKEDGE_FALLING       BIT(5)
 100 +#define SPICFG_TXCLKEDGE_FALLING       BIT(4)
 101 +#define SPICFG_HIZSPI                  BIT(3)
 102 +#define SPICFG_SPICLK_PRESCALE_MASK    0x7
 103 +#define SPICFG_SPICLK_DIV2             0
 104 +#define SPICFG_SPICLK_DIV4             1
 105 +#define SPICFG_SPICLK_DIV8             2
 106 +#define SPICFG_SPICLK_DIV16            3
 107 +#define SPICFG_SPICLK_DIV32            4
 108 +#define SPICFG_SPICLK_DIV64            5
 109 +#define SPICFG_SPICLK_DIV128           6
 110 +#define SPICFG_SPICLK_DISABLE          7
 111 +
 112 +/* SPICTL register bit field */
 113 +#define SPICTL_START                   BIT(4)
 114 +#define SPICTL_HIZSDO                  BIT(3)
 115 +#define SPICTL_STARTWR                 BIT(2)
 116 +#define SPICTL_STARTRD                 BIT(1)
 117 +#define SPICTL_SPIENA                  BIT(0)
 118 +
 119 +/* SPIUSER register bit field */
 120 +#define SPIUSER_USERMODE               BIT(21)
 121 +#define SPIUSER_INSTR_PHASE            BIT(20)
 122 +#define SPIUSER_ADDR_PHASE_MASK                0x7
 123 +#define SPIUSER_ADDR_PHASE_OFFSET      17
 124 +#define SPIUSER_MODE_PHASE             BIT(16)
 125 +#define SPIUSER_DUMMY_PHASE_MASK       0x3
 126 +#define SPIUSER_DUMMY_PHASE_OFFSET     14
 127 +#define SPIUSER_DATA_PHASE_MASK                0x3
 128 +#define SPIUSER_DATA_PHASE_OFFSET      12
 129 +#define SPIUSER_DATA_READ              (BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
 130 +#define SPIUSER_DATA_WRITE             (BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
 131 +#define SPIUSER_ADDR_TYPE_OFFSET       9
 132 +#define SPIUSER_MODE_TYPE_OFFSET       6
 133 +#define SPIUSER_DUMMY_TYPE_OFFSET      3
 134 +#define SPIUSER_DATA_TYPE_OFFSET       0
 135 +#define SPIUSER_TRANSFER_MASK          0x7
 136 +#define SPIUSER_TRANSFER_SINGLE                BIT(0)
 137 +#define SPIUSER_TRANSFER_DUAL          BIT(1)
 138 +#define SPIUSER_TRANSFER_QUAD          BIT(2)
 139 +
 140 +#define SPIUSER_TRANSFER_TYPE(type) ( \
 141 +       (type << SPIUSER_ADDR_TYPE_OFFSET) | \
 142 +       (type << SPIUSER_MODE_TYPE_OFFSET) | \
 143 +       (type << SPIUSER_DUMMY_TYPE_OFFSET) | \
 144 +       (type << SPIUSER_DATA_TYPE_OFFSET) \
 145 +)
 146 +
 147 +/* SPIFIFOSTAT register bit field */
 148 +#define SPIFIFOSTAT_TXEMPTY            BIT(19)
 149 +#define SPIFIFOSTAT_RXEMPTY            BIT(18)
 150 +#define SPIFIFOSTAT_TXFULL             BIT(17)
 151 +#define SPIFIFOSTAT_RXFULL             BIT(16)
 152 +#define SPIFIFOSTAT_FIFO_MASK          0xff
 153 +#define SPIFIFOSTAT_TX_OFFSET          8
 154 +#define SPIFIFOSTAT_RX_OFFSET          0
 155 +
 156 +#define SPI_FIFO_DEPTH                 16
 157 +
 158 +/* SPIMODE register bit field */
 159 +#define SPIMODE_MODE_OFFSET            24
 160 +#define SPIMODE_DUMMY_OFFSET           0
 161 +
 162 +/* SPIARB register bit field */
 163 +#define SPICTL_ARB_EN                  BIT(31)
 164 +#define SPICTL_CSCTL1                  BIT(16)
 165 +#define SPI1_POR                       BIT(1)
 166 +#define SPI0_POR                       BIT(0)
 167 +
 168 +#define RT2880_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
 169 +               SPI_CS_HIGH)
 170 +
 171 +static atomic_t hw_reset_count = ATOMIC_INIT(0);
 172 +
 173 +struct rt2880_spi {
 174 +       struct spi_master       *master;
 175 +       void __iomem            *base;
 176 +       u32                     speed;
 177 +       u16                     wait_loops;
 178 +       u16                     mode;
 179 +       struct clk              *clk;
 180 +};
 181 +
 182 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
 183 +{
 184 +       return spi_master_get_devdata(spi->master);
 185 +}
 186 +
 187 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
 188 +{
 189 +       return ioread32(rs->base + reg);
 190 +}
 191 +
 192 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
 193 +               const u32 val)
 194 +{
 195 +       iowrite32(val, rs->base + reg);
 196 +}
 197 +
 198 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 199 +{
 200 +       void __iomem *addr = rs->base + reg;
 201 +
 202 +       iowrite32((ioread32(addr) | mask), addr);
 203 +}
 204 +
 205 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 206 +{
 207 +       void __iomem *addr = rs->base + reg;
 208 +
 209 +       iowrite32((ioread32(addr) & ~mask), addr);
 210 +}
 211 +
 212 +static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)
 213 +{
 214 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 215 +       u32 rate;
 216 +       u32 prescale;
 217 +
 218 +       /*
 219 +        * the supported rates are: 2, 4, 8, ... 128
 220 +        * round up as we look for equal or less speed
 221 +        */
 222 +       rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);
 223 +       rate = roundup_pow_of_two(rate);
 224 +
 225 +       /* Convert the rate to SPI clock divisor value. */
 226 +       prescale = ilog2(rate / 2);
 227 +
 228 +       /* some tolerance. double and add 100 */
 229 +       rs->wait_loops = (8 * HZ * loops_per_jiffy) /
 230 +               (clk_get_rate(rs->clk) / rate);
 231 +       rs->wait_loops = (rs->wait_loops << 1) + 100;
 232 +       rs->speed = speed;
 233 +
 234 +       dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n",
 235 +                       clk_get_rate(rs->clk) / rate, speed, rate, prescale,
 236 +                       rs->wait_loops);
 237 +
 238 +       return prescale;
 239 +}
 240 +
 241 +static u32 get_arbiter_offset(struct spi_master *master)
 242 +{
 243 +       u32 offset;
 244 +
 245 +       offset = RAMIPS_SPI_ARBITER;
 246 +       if (master->bus_num == 1)
 247 +               offset -= RAMIPS_SPI_DEV_OFFSET;
 248 +
 249 +       return offset;
 250 +}
 251 +
 252 +static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)
 253 +{
 254 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 255 +
 256 +       if (enable)
 257 +               rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 258 +       else
 259 +               rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 260 +}
 261 +
 262 +static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
 263 +{
 264 +       int loop = rs->wait_loops * len;
 265 +
 266 +       while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
 267 +               cpu_relax();
 268 +
 269 +       if (loop)
 270 +               return 0;
 271 +
 272 +       return -ETIMEDOUT;
 273 +}
 274 +
 275 +static void rt2880_dump_reg(struct spi_master *master)
 276 +{
 277 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 278 +
 279 +       dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \
 280 +                       "data: %08x, arb: %08x\n",
 281 +                       rt2880_spi_read(rs, RAMIPS_SPI_STAT),
 282 +                       rt2880_spi_read(rs, RAMIPS_SPI_CFG),
 283 +                       rt2880_spi_read(rs, RAMIPS_SPI_CTL),
 284 +                       rt2880_spi_read(rs, RAMIPS_SPI_DATA),
 285 +                       rt2880_spi_read(rs, get_arbiter_offset(master)));
 286 +}
 287 +
 288 +static int rt2880_spi_transfer_one(struct spi_master *master,
 289 +               struct spi_device *spi, struct spi_transfer *xfer)
 290 +{
 291 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 292 +       unsigned len;
 293 +       const u8 *tx = xfer->tx_buf;
 294 +       u8 *rx = xfer->rx_buf;
 295 +       int err = 0;
 296 +
 297 +       /* change clock speed  */
 298 +       if (unlikely(rs->speed != xfer->speed_hz)) {
 299 +               u32 reg;
 300 +               reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
 301 +               reg &= ~SPICFG_SPICLK_PRESCALE_MASK;
 302 +               reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);
 303 +               rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
 304 +       }
 305 +
 306 +       if (tx) {
 307 +               len = xfer->len;
 308 +               while (len-- > 0) {
 309 +                       rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);
 310 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
 311 +                       err = rt2880_spi_wait_ready(rs, 1);
 312 +                       if (err) {
 313 +                               dev_err(&spi->dev, "TX failed, err=%d\n", err);
 314 +                               goto out;
 315 +                       }
 316 +               }
 317 +       }
 318 +
 319 +       if (rx) {
 320 +               len = xfer->len;
 321 +               while (len-- > 0) {
 322 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
 323 +                       err = rt2880_spi_wait_ready(rs, 1);
 324 +                       if (err) {
 325 +                               dev_err(&spi->dev, "RX failed, err=%d\n", err);
 326 +                               goto out;
 327 +                       }
 328 +                       *rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
 329 +               }
 330 +       }
 331 +
 332 +out:
 333 +       return err;
 334 +}
 335 +
 336 +/* copy from spi.c */
 337 +static void spi_set_cs(struct spi_device *spi, bool enable)
 338 +{
 339 +       if (spi->mode & SPI_CS_HIGH)
 340 +               enable = !enable;
 341 +
 342 +       if (spi->cs_gpio >= 0)
 343 +               gpio_set_value(spi->cs_gpio, !enable);
 344 +       else if (spi->master->set_cs)
 345 +               spi->master->set_cs(spi, !enable);
 346 +}
 347 +
 348 +static int rt2880_spi_setup(struct spi_device *spi)
 349 +{
 350 +       struct spi_master *master = spi->master;
 351 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 352 +       u32 reg, old_reg, arbit_off;
 353 +
 354 +       if ((spi->max_speed_hz > master->max_speed_hz) ||
 355 +                       (spi->max_speed_hz < master->min_speed_hz)) {
 356 +               dev_err(&spi->dev, "invalide requested speed %d Hz\n",
 357 +                               spi->max_speed_hz);
 358 +               return -EINVAL;
 359 +       }
 360 +
 361 +       if (!(master->bits_per_word_mask &
 362 +                               BIT(spi->bits_per_word - 1))) {
 363 +               dev_err(&spi->dev, "invalide bits_per_word %d\n",
 364 +                               spi->bits_per_word);
 365 +               return -EINVAL;
 366 +       }
 367 +
 368 +       /* the hardware seems can't work on mode0 force it to mode3 */
 369 +       if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
 370 +               dev_warn(&spi->dev, "force spi mode3\n");
 371 +               spi->mode |= SPI_MODE_3;
 372 +       }
 373 +
 374 +       /* chip polarity */
 375 +       arbit_off = get_arbiter_offset(master);
 376 +       reg = old_reg = rt2880_spi_read(rs, arbit_off);
 377 +       if (spi->mode & SPI_CS_HIGH) {
 378 +               switch (master->bus_num) {
 379 +               case 1:
 380 +                       reg |= SPI1_POR;
 381 +                       break;
 382 +               default:
 383 +                       reg |= SPI0_POR;
 384 +                       break;
 385 +               }
 386 +       } else {
 387 +               switch (master->bus_num) {
 388 +               case 1:
 389 +                       reg &= ~SPI1_POR;
 390 +                       break;
 391 +               default:
 392 +                       reg &= ~SPI0_POR;
 393 +                       break;
 394 +               }
 395 +       }
 396 +
 397 +       /* enable spi1 */
 398 +       if (master->bus_num == 1)
 399 +               reg |= SPICTL_ARB_EN;
 400 +
 401 +       if (reg != old_reg)
 402 +               rt2880_spi_write(rs, arbit_off, reg);
 403 +
 404 +       /* deselected the spi device */
 405 +       spi_set_cs(spi, false);
 406 +
 407 +       rt2880_dump_reg(master);
 408 +
 409 +       return 0;
 410 +}
 411 +
 412 +static int rt2880_spi_prepare_message(struct spi_master *master,
 413 +               struct spi_message *msg)
 414 +{
 415 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 416 +       struct spi_device *spi = msg->spi;
 417 +       u32 reg;
 418 +
 419 +       if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))
 420 +               return 0;
 421 +
 422 +#if 0
 423 +       /* set spido to tri-state */
 424 +       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);
 425 +#endif
 426 +
 427 +       reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
 428 +
 429 +       reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |
 430 +                       SPICFG_RXCLKEDGE_FALLING |
 431 +                       SPICFG_TXCLKEDGE_FALLING |
 432 +                       SPICFG_SPICLK_PRESCALE_MASK);
 433 +
 434 +       /* MSB */
 435 +       if (!(spi->mode & SPI_LSB_FIRST))
 436 +               reg |= SPICFG_MSBFIRST;
 437 +
 438 +       /* spi mode */
 439 +       switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
 440 +       case SPI_MODE_0:
 441 +               reg |= SPICFG_TXCLKEDGE_FALLING;
 442 +               break;
 443 +       case SPI_MODE_1:
 444 +               reg |= SPICFG_RXCLKEDGE_FALLING;
 445 +               break;
 446 +       case SPI_MODE_2:
 447 +               reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
 448 +               break;
 449 +       case SPI_MODE_3:
 450 +               reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
 451 +               break;
 452 +       }
 453 +       rs->mode = spi->mode;
 454 +
 455 +#if 0
 456 +       /* set spiclk and spiena to tri-state */
 457 +       reg |= SPICFG_HIZSPI;
 458 +#endif
 459 +
 460 +       /* clock divide */
 461 +       reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);
 462 +
 463 +       rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
 464 +
 465 +       return 0;
 466 +}
 467 +
 468 +static int rt2880_spi_probe(struct platform_device *pdev)
 469 +{
 470 +       struct spi_master *master;
 471 +       struct rt2880_spi *rs;
 472 +       void __iomem *base;
 473 +       struct resource *r;
 474 +       struct clk *clk;
 475 +       int ret;
 476 +
 477 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 478 +       base = devm_ioremap_resource(&pdev->dev, r);
 479 +       if (IS_ERR(base))
 480 +               return PTR_ERR(base);
 481 +
 482 +       clk = devm_clk_get(&pdev->dev, NULL);
 483 +       if (IS_ERR(clk)) {
 484 +               dev_err(&pdev->dev, "unable to get SYS clock\n");
 485 +               return PTR_ERR(clk);
 486 +       }
 487 +
 488 +       ret = clk_prepare_enable(clk);
 489 +       if (ret)
 490 +               goto err_clk;
 491 +
 492 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 493 +       if (master == NULL) {
 494 +               dev_dbg(&pdev->dev, "master allocation failed\n");
 495 +               ret = -ENOMEM;
 496 +               goto err_clk;
 497 +       }
 498 +
 499 +       master->dev.of_node = pdev->dev.of_node;
 500 +       master->mode_bits = RT2880_SPI_MODE_BITS;
 501 +       master->bits_per_word_mask = SPI_BPW_MASK(8);
 502 +       master->min_speed_hz = clk_get_rate(clk) / 128;
 503 +       master->max_speed_hz = clk_get_rate(clk) / 2;
 504 +       master->flags = SPI_MASTER_HALF_DUPLEX;
 505 +       master->setup = rt2880_spi_setup;
 506 +       master->prepare_message = rt2880_spi_prepare_message;
 507 +       master->set_cs = rt2880_spi_set_cs;
 508 +       master->transfer_one = rt2880_spi_transfer_one,
 509 +
 510 +       dev_set_drvdata(&pdev->dev, master);
 511 +
 512 +       rs = spi_master_get_devdata(master);
 513 +       rs->master = master;
 514 +       rs->base = base;
 515 +       rs->clk = clk;
 516 +
 517 +       if (atomic_inc_return(&hw_reset_count) == 1)
 518 +               device_reset(&pdev->dev);
 519 +
 520 +       ret = devm_spi_register_master(&pdev->dev, master);
 521 +       if (ret < 0) {
 522 +               dev_err(&pdev->dev, "devm_spi_register_master error.\n");
 523 +               goto err_master;
 524 +       }
 525 +
 526 +       return ret;
 527 +
 528 +err_master:
 529 +       spi_master_put(master);
 530 +       kfree(master);
 531 +err_clk:
 532 +       clk_disable_unprepare(clk);
 533 +
 534 +       return ret;
 535 +}
 536 +
 537 +static int rt2880_spi_remove(struct platform_device *pdev)
 538 +{
 539 +       struct spi_master *master;
 540 +       struct rt2880_spi *rs;
 541 +
 542 +       master = dev_get_drvdata(&pdev->dev);
 543 +       rs = spi_master_get_devdata(master);
 544 +
 545 +       clk_disable_unprepare(rs->clk);
 546 +       atomic_dec(&hw_reset_count);
 547 +
 548 +       return 0;
 549 +}
 550 +
 551 +MODULE_ALIAS("platform:" DRIVER_NAME);
 552 +
 553 +static const struct of_device_id rt2880_spi_match[] = {
 554 +       { .compatible = "ralink,rt2880-spi" },
 555 +       {},
 556 +};
 557 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 558 +
 559 +static struct platform_driver rt2880_spi_driver = {
 560 +       .driver = {
 561 +               .name = DRIVER_NAME,
 562 +               .owner = THIS_MODULE,
 563 +               .of_match_table = rt2880_spi_match,
 564 +       },
 565 +       .probe = rt2880_spi_probe,
 566 +       .remove = rt2880_spi_remove,
 567 +};
 568 +
 569 +module_platform_driver(rt2880_spi_driver);
 570 +
 571 +MODULE_DESCRIPTION("Ralink SPI driver");
 572 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
 573 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 574 +MODULE_LICENSE("GPL");