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[openwrt/openwrt.git] / target / linux / ramips / patches-4.9 / 0043-spi-add-mt7621-support.patch
1 From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:49:07 +0100
4 Subject: [PATCH 43/53] spi: add mt7621 support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/spi/Kconfig | 6 +
9 drivers/spi/Makefile | 1 +
10 drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 487 insertions(+)
12 create mode 100644 drivers/spi/spi-mt7621.c
13
14 --- a/drivers/spi/Kconfig
15 +++ b/drivers/spi/Kconfig
16 @@ -540,6 +540,12 @@ config SPI_RT2880
17 help
18 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
19
20 +config SPI_MT7621
21 + tristate "MediaTek MT7621 SPI Controller"
22 + depends on RALINK
23 + help
24 + This selects a driver for the MediaTek MT7621 SPI Controller.
25 +
26 config SPI_S3C24XX
27 tristate "Samsung S3C24XX series SPI"
28 depends on ARCH_S3C24XX
29 --- a/drivers/spi/Makefile
30 +++ b/drivers/spi/Makefile
31 @@ -55,6 +55,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
32 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
33 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
34 obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
35 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
36 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
37 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
38 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
39 --- /dev/null
40 +++ b/drivers/spi/spi-mt7621.c
41 @@ -0,0 +1,483 @@
42 +/*
43 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
44 + *
45 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
46 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
47 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
48 + *
49 + * Some parts are based on spi-orion.c:
50 + * Author: Shadi Ammouri <shadi@marvell.com>
51 + * Copyright (C) 2007-2008 Marvell Ltd.
52 + *
53 + * This program is free software; you can redistribute it and/or modify
54 + * it under the terms of the GNU General Public License version 2 as
55 + * published by the Free Software Foundation.
56 + */
57 +
58 +#include <linux/init.h>
59 +#include <linux/module.h>
60 +#include <linux/clk.h>
61 +#include <linux/err.h>
62 +#include <linux/delay.h>
63 +#include <linux/io.h>
64 +#include <linux/reset.h>
65 +#include <linux/spi/spi.h>
66 +#include <linux/of_device.h>
67 +#include <linux/platform_device.h>
68 +#include <linux/swab.h>
69 +
70 +#include <ralink_regs.h>
71 +
72 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
73 +
74 +#define DRIVER_NAME "spi-mt7621"
75 +/* in usec */
76 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
77 +
78 +/* SPISTAT register bit field */
79 +#define SPISTAT_BUSY BIT(0)
80 +
81 +#define MT7621_SPI_TRANS 0x00
82 +#define SPITRANS_BUSY BIT(16)
83 +
84 +#define MT7621_SPI_OPCODE 0x04
85 +#define MT7621_SPI_DATA0 0x08
86 +#define MT7621_SPI_DATA4 0x18
87 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
88 +#define SPI_CTL_START BIT(8)
89 +
90 +#define MT7621_SPI_POLAR 0x38
91 +#define MT7621_SPI_MASTER 0x28
92 +#define MT7621_SPI_MOREBUF 0x2c
93 +#define MT7621_SPI_SPACE 0x3c
94 +
95 +#define MT7621_CPHA BIT(5)
96 +#define MT7621_CPOL BIT(4)
97 +#define MT7621_LSB_FIRST BIT(3)
98 +
99 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
100 +
101 +struct mt7621_spi;
102 +
103 +struct mt7621_spi {
104 + struct spi_master *master;
105 + void __iomem *base;
106 + unsigned int sys_freq;
107 + unsigned int speed;
108 + struct clk *clk;
109 + spinlock_t lock;
110 +
111 + struct mt7621_spi_ops *ops;
112 +};
113 +
114 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
115 +{
116 + return spi_master_get_devdata(spi->master);
117 +}
118 +
119 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
120 +{
121 + return ioread32(rs->base + reg);
122 +}
123 +
124 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
125 +{
126 + iowrite32(val, rs->base + reg);
127 +}
128 +
129 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
130 +{
131 + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
132 +
133 + master |= 7 << 29;
134 + master |= 1 << 2;
135 + if (duplex)
136 + master |= 1 << 10;
137 + else
138 + master &= ~(1 << 10);
139 +
140 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
141 +}
142 +
143 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
144 +{
145 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
146 + int cs = spi->chip_select;
147 + u32 polar = 0;
148 +
149 + mt7621_spi_reset(rs, cs);
150 + if (enable)
151 + polar = BIT(cs);
152 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
153 +}
154 +
155 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
156 +{
157 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
158 + u32 rate;
159 + u32 reg;
160 +
161 + dev_dbg(&spi->dev, "speed:%u\n", speed);
162 +
163 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
164 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
165 +
166 + if (rate > 4097)
167 + return -EINVAL;
168 +
169 + if (rate < 2)
170 + rate = 2;
171 +
172 + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
173 + reg &= ~(0xfff << 16);
174 + reg |= (rate - 2) << 16;
175 + rs->speed = speed;
176 +
177 + reg &= ~MT7621_LSB_FIRST;
178 + if (spi->mode & SPI_LSB_FIRST)
179 + reg |= MT7621_LSB_FIRST;
180 +
181 + reg &= ~(MT7621_CPHA | MT7621_CPOL);
182 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
183 + case SPI_MODE_0:
184 + break;
185 + case SPI_MODE_1:
186 + reg |= MT7621_CPHA;
187 + break;
188 + case SPI_MODE_2:
189 + reg |= MT7621_CPOL;
190 + break;
191 + case SPI_MODE_3:
192 + reg |= MT7621_CPOL | MT7621_CPHA;
193 + break;
194 + }
195 + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
196 +
197 + return 0;
198 +}
199 +
200 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
201 +{
202 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
203 + int i;
204 +
205 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
206 + u32 status;
207 +
208 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
209 + if ((status & SPITRANS_BUSY) == 0) {
210 + return 0;
211 + }
212 + cpu_relax();
213 + udelay(1);
214 + }
215 +
216 + return -ETIMEDOUT;
217 +}
218 +
219 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
220 + struct spi_message *m)
221 +{
222 + struct mt7621_spi *rs = spi_master_get_devdata(master);
223 + struct spi_device *spi = m->spi;
224 + unsigned int speed = spi->max_speed_hz;
225 + struct spi_transfer *t = NULL;
226 + int status = 0;
227 + int i, len = 0;
228 + int rx_len = 0;
229 + u32 data[9] = { 0 };
230 + u32 val;
231 +
232 + mt7621_spi_wait_till_ready(spi);
233 +
234 + list_for_each_entry(t, &m->transfers, transfer_list) {
235 + const u8 *buf = t->tx_buf;
236 +
237 + if (t->rx_buf)
238 + rx_len += t->len;
239 +
240 + if (!buf)
241 + continue;
242 +
243 + if (t->speed_hz < speed)
244 + speed = t->speed_hz;
245 +
246 + if (WARN_ON(len + t->len > 36)) {
247 + status = -EIO;
248 + goto msg_done;
249 + }
250 +
251 + for (i = 0; i < t->len; i++, len++)
252 + data[len / 4] |= buf[i] << (8 * (len & 3));
253 + }
254 +
255 + if (WARN_ON(rx_len > 32)) {
256 + status = -EIO;
257 + goto msg_done;
258 + }
259 +
260 + if (mt7621_spi_prepare(spi, speed)) {
261 + status = -EIO;
262 + goto msg_done;
263 + }
264 + data[0] = swab32(data[0]);
265 + if (len < 4)
266 + data[0] >>= (4 - len) * 8;
267 +
268 + for (i = 0; i < len; i += 4)
269 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
270 +
271 + val = (min_t(int, len, 4) * 8) << 24;
272 + if (len > 4)
273 + val |= (len - 4) * 8;
274 + val |= (rx_len * 8) << 12;
275 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
276 +
277 + mt7621_spi_set_cs(spi, 1);
278 +
279 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
280 + val |= SPI_CTL_START;
281 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
282 +
283 + mt7621_spi_wait_till_ready(spi);
284 +
285 + mt7621_spi_set_cs(spi, 0);
286 +
287 + for (i = 0; i < rx_len; i += 4)
288 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
289 +
290 + m->actual_length = len + rx_len;
291 +
292 + len = 0;
293 + list_for_each_entry(t, &m->transfers, transfer_list) {
294 + u8 *buf = t->rx_buf;
295 +
296 + if (!buf)
297 + continue;
298 +
299 + for (i = 0; i < t->len; i++, len++)
300 + buf[i] = data[len / 4] >> (8 * (len & 3));
301 + }
302 +
303 +msg_done:
304 + m->status = status;
305 + spi_finalize_current_message(master);
306 +
307 + return 0;
308 +}
309 +
310 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
311 + struct spi_message *m)
312 +{
313 + struct mt7621_spi *rs = spi_master_get_devdata(master);
314 + struct spi_device *spi = m->spi;
315 + unsigned int speed = spi->max_speed_hz;
316 + struct spi_transfer *t = NULL;
317 + int status = 0;
318 + int i, len = 0;
319 + int rx_len = 0;
320 + u32 data[9] = { 0 };
321 + u32 val = 0;
322 +
323 + mt7621_spi_wait_till_ready(spi);
324 +
325 + list_for_each_entry(t, &m->transfers, transfer_list) {
326 + const u8 *buf = t->tx_buf;
327 +
328 + if (t->rx_buf)
329 + rx_len += t->len;
330 +
331 + if (!buf)
332 + continue;
333 +
334 + if (WARN_ON(len + t->len > 16)) {
335 + status = -EIO;
336 + goto msg_done;
337 + }
338 +
339 + for (i = 0; i < t->len; i++, len++)
340 + data[len / 4] |= buf[i] << (8 * (len & 3));
341 + if (speed > t->speed_hz)
342 + speed = t->speed_hz;
343 + }
344 +
345 + if (WARN_ON(rx_len > 16)) {
346 + status = -EIO;
347 + goto msg_done;
348 + }
349 +
350 + if (mt7621_spi_prepare(spi, speed)) {
351 + status = -EIO;
352 + goto msg_done;
353 + }
354 +
355 + for (i = 0; i < len; i += 4)
356 + mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
357 +
358 + val |= len * 8;
359 + val |= (rx_len * 8) << 12;
360 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
361 +
362 + mt7621_spi_set_cs(spi, 1);
363 +
364 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
365 + val |= SPI_CTL_START;
366 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
367 +
368 + mt7621_spi_wait_till_ready(spi);
369 +
370 + mt7621_spi_set_cs(spi, 0);
371 +
372 + for (i = 0; i < rx_len; i += 4)
373 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
374 +
375 + m->actual_length = rx_len;
376 +
377 + len = 0;
378 + list_for_each_entry(t, &m->transfers, transfer_list) {
379 + u8 *buf = t->rx_buf;
380 +
381 + if (!buf)
382 + continue;
383 +
384 + for (i = 0; i < t->len; i++, len++)
385 + buf[i] = data[len / 4] >> (8 * (len & 3));
386 + }
387 +
388 +msg_done:
389 + m->status = status;
390 + spi_finalize_current_message(master);
391 +
392 + return 0;
393 +}
394 +
395 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
396 + struct spi_message *m)
397 +{
398 + struct spi_device *spi = m->spi;
399 + int cs = spi->chip_select;
400 +
401 + if (cs)
402 + return mt7621_spi_transfer_full_duplex(master, m);
403 + return mt7621_spi_transfer_half_duplex(master, m);
404 +}
405 +
406 +static int mt7621_spi_setup(struct spi_device *spi)
407 +{
408 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
409 +
410 + if ((spi->max_speed_hz == 0) ||
411 + (spi->max_speed_hz > (rs->sys_freq / 2)))
412 + spi->max_speed_hz = (rs->sys_freq / 2);
413 +
414 + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
415 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
416 + spi->max_speed_hz);
417 + return -EINVAL;
418 + }
419 +
420 + return 0;
421 +}
422 +
423 +static const struct of_device_id mt7621_spi_match[] = {
424 + { .compatible = "ralink,mt7621-spi" },
425 + {},
426 +};
427 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
428 +
429 +static int mt7621_spi_probe(struct platform_device *pdev)
430 +{
431 + const struct of_device_id *match;
432 + struct spi_master *master;
433 + struct mt7621_spi *rs;
434 + unsigned long flags;
435 + void __iomem *base;
436 + struct resource *r;
437 + int status = 0;
438 + struct clk *clk;
439 + struct mt7621_spi_ops *ops;
440 +
441 + match = of_match_device(mt7621_spi_match, &pdev->dev);
442 + if (!match)
443 + return -EINVAL;
444 + ops = (struct mt7621_spi_ops *)match->data;
445 +
446 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
447 + base = devm_ioremap_resource(&pdev->dev, r);
448 + if (IS_ERR(base))
449 + return PTR_ERR(base);
450 +
451 + clk = devm_clk_get(&pdev->dev, NULL);
452 + if (IS_ERR(clk)) {
453 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
454 + status);
455 + return PTR_ERR(clk);
456 + }
457 +
458 + status = clk_prepare_enable(clk);
459 + if (status)
460 + return status;
461 +
462 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
463 + if (master == NULL) {
464 + dev_info(&pdev->dev, "master allocation failed\n");
465 + return -ENOMEM;
466 + }
467 +
468 + master->mode_bits = RT2880_SPI_MODE_BITS;
469 +
470 + master->setup = mt7621_spi_setup;
471 + master->transfer_one_message = mt7621_spi_transfer_one_message;
472 + master->bits_per_word_mask = SPI_BPW_MASK(8);
473 + master->dev.of_node = pdev->dev.of_node;
474 + master->num_chipselect = 2;
475 +
476 + dev_set_drvdata(&pdev->dev, master);
477 +
478 + rs = spi_master_get_devdata(master);
479 + rs->base = base;
480 + rs->clk = clk;
481 + rs->master = master;
482 + rs->sys_freq = clk_get_rate(rs->clk);
483 + rs->ops = ops;
484 + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
485 + spin_lock_irqsave(&rs->lock, flags);
486 +
487 + device_reset(&pdev->dev);
488 +
489 + mt7621_spi_reset(rs, 0);
490 +
491 + return spi_register_master(master);
492 +}
493 +
494 +static int mt7621_spi_remove(struct platform_device *pdev)
495 +{
496 + struct spi_master *master;
497 + struct mt7621_spi *rs;
498 +
499 + master = dev_get_drvdata(&pdev->dev);
500 + rs = spi_master_get_devdata(master);
501 +
502 + clk_disable(rs->clk);
503 + spi_unregister_master(master);
504 +
505 + return 0;
506 +}
507 +
508 +MODULE_ALIAS("platform:" DRIVER_NAME);
509 +
510 +static struct platform_driver mt7621_spi_driver = {
511 + .driver = {
512 + .name = DRIVER_NAME,
513 + .owner = THIS_MODULE,
514 + .of_match_table = mt7621_spi_match,
515 + },
516 + .probe = mt7621_spi_probe,
517 + .remove = mt7621_spi_remove,
518 +};
519 +
520 +module_platform_driver(mt7621_spi_driver);
521 +
522 +MODULE_DESCRIPTION("MT7621 SPI driver");
523 +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
524 +MODULE_LICENSE("GPL");