target/linux/ramips/patches-4.9/0045-i2c-add-mt7621-driver.patch

   1 From d5c54ff3d1db0a4348fa04d8e78f3bf6063e3afc Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:21:27 +0100
   4 Subject: [PATCH 45/53] i2c: add mt7621 driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/i2c/busses/Kconfig      |    4 +
   9  drivers/i2c/busses/Makefile     |    1 +
  10  drivers/i2c/busses/i2c-mt7621.c |  303 +++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 308 insertions(+)
  12  create mode 100644 drivers/i2c/busses/i2c-mt7621.c
  13
  14 --- a/drivers/i2c/busses/Kconfig
  15 +++ b/drivers/i2c/busses/Kconfig
  16 @@ -815,6 +815,11 @@ config I2C_RALINK
  17         depends on RALINK && !SOC_MT7621
  18         select OF_I2C
  19
  20 +config I2C_MT7621
  21 +       tristate "MT7621/MT7628 I2C Controller"
  22 +       depends on RALINK && (SOC_MT7620 || SOC_MT7621)
  23 +       select OF_I2C
  24 +
  25  config HAVE_S3C2410_I2C
  26         bool
  27         help
  28 --- a/drivers/i2c/busses/Makefile
  29 +++ b/drivers/i2c/busses/Makefile
  30 @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_PUV3)                += i2c-puv3.o
  31  obj-$(CONFIG_I2C_PXA)          += i2c-pxa.o
  32  obj-$(CONFIG_I2C_PXA_PCI)      += i2c-pxa-pci.o
  33  obj-$(CONFIG_I2C_RALINK)       += i2c-ralink.o
  34 +obj-$(CONFIG_I2C_MT7621)       += i2c-mt7621.o
  35  obj-$(CONFIG_I2C_QUP)          += i2c-qup.o
  36  obj-$(CONFIG_I2C_RIIC)         += i2c-riic.o
  37  obj-$(CONFIG_I2C_RK3X)         += i2c-rk3x.o
  38 --- /dev/null
  39 +++ b/drivers/i2c/busses/i2c-mt7621.c
  40 @@ -0,0 +1,433 @@
  41 +/*
  42 + * drivers/i2c/busses/i2c-mt7621.c
  43 + *
  44 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
  45 + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
  46 + *
  47 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
  48 + * (C) 2014 Sittisak <sittisaks@hotmail.com>
  49 + *
  50 + * This software is licensed under the terms of the GNU General Public
  51 + * License version 2, as published by the Free Software Foundation, and
  52 + * may be copied, distributed, and modified under those terms.
  53 + *
  54 + * This program is distributed in the hope that it will be useful,
  55 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  56 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  57 + * GNU General Public License for more details.
  58 + *
  59 + */
  60 +
  61 +#include <linux/interrupt.h>
  62 +#include <linux/kernel.h>
  63 +#include <linux/module.h>
  64 +#include <linux/reset.h>
  65 +#include <linux/delay.h>
  66 +#include <linux/slab.h>
  67 +#include <linux/init.h>
  68 +#include <linux/errno.h>
  69 +#include <linux/platform_device.h>
  70 +#include <linux/of_platform.h>
  71 +#include <linux/i2c.h>
  72 +#include <linux/io.h>
  73 +#include <linux/err.h>
  74 +#include <linux/clk.h>
  75 +
  76 +#define REG_SM0CFG0            0x08
  77 +#define REG_SM0DOUT            0x10
  78 +#define REG_SM0DIN             0x14
  79 +#define REG_SM0ST              0x18
  80 +#define REG_SM0AUTO            0x1C
  81 +#define REG_SM0CFG1            0x20
  82 +#define REG_SM0CFG2            0x28
  83 +#define REG_SM0CTL0            0x40
  84 +#define REG_SM0CTL1            0x44
  85 +#define REG_SM0D0              0x50
  86 +#define REG_SM0D1              0x54
  87 +#define REG_PINTEN             0x5C
  88 +#define REG_PINTST             0x60
  89 +#define REG_PINTCL             0x64
  90 +
  91 +/* REG_SM0CFG0 */
  92 +#define I2C_DEVADDR_MASK       0x7f
  93 +
  94 +/* REG_SM0ST */
  95 +#define I2C_DATARDY            BIT(2)
  96 +#define I2C_SDOEMPTY           BIT(1)
  97 +#define I2C_BUSY               BIT(0)
  98 +
  99 +/* REG_SM0AUTO */
 100 +#define READ_CMD               BIT(0)
 101 +
 102 +/* REG_SM0CFG1 */
 103 +#define BYTECNT_MAX            64
 104 +#define SET_BYTECNT(x)         (x - 1)
 105 +
 106 +/* REG_SM0CFG2 */
 107 +#define AUTOMODE_EN            BIT(0)
 108 +
 109 +/* REG_SM0CTL0 */
 110 +#define ODRAIN_HIGH_SM0                BIT(31)
 111 +#define VSYNC_SHIFT            28
 112 +#define VSYNC_MASK             0x3
 113 +#define VSYNC_PULSE            (0x1 << VSYNC_SHIFT)
 114 +#define VSYNC_RISING           (0x2 << VSYNC_SHIFT)
 115 +#define CLK_DIV_SHIFT          16
 116 +#define CLK_DIV_MASK           0xfff
 117 +#define DEG_CNT_SHIFT          8
 118 +#define DEG_CNT_MASK           0xff
 119 +#define WAIT_HIGH              BIT(6)
 120 +#define DEG_EN                 BIT(5)
 121 +#define CS_STATUA              BIT(4)
 122 +#define SCL_STATUS             BIT(3)
 123 +#define SDA_STATUS             BIT(2)
 124 +#define SM0_EN                 BIT(1)
 125 +#define SCL_STRECH             BIT(0)
 126 +
 127 +/* REG_SM0CTL1 */
 128 +#define ACK_SHIFT              16
 129 +#define ACK_MASK               0xff
 130 +#define PGLEN_SHIFT            8
 131 +#define PGLEN_MASK             0x7
 132 +#define SM0_MODE_SHIFT         4
 133 +#define SM0_MODE_MASK          0x7
 134 +#define SM0_MODE_START         0x1
 135 +#define SM0_MODE_WRITE         0x2
 136 +#define SM0_MODE_STOP          0x3
 137 +#define SM0_MODE_READ_NACK     0x4
 138 +#define SM0_MODE_READ_ACK      0x5
 139 +#define SM0_TRI_BUSY           BIT(0)
 140 +
 141 +/* timeout waiting for I2C devices to respond (clock streching) */
 142 +#define TIMEOUT_MS              1000
 143 +#define DELAY_INTERVAL_US       100
 144 +
 145 +struct mtk_i2c {
 146 +       void __iomem *base;
 147 +       struct clk *clk;
 148 +       struct device *dev;
 149 +       struct i2c_adapter adap;
 150 +       u32 cur_clk;
 151 +       u32 clk_div;
 152 +       u32 flags;
 153 +};
 154 +
 155 +static void mtk_i2c_w32(struct mtk_i2c *i2c, u32 val, unsigned reg)
 156 +{
 157 +       iowrite32(val, i2c->base + reg);
 158 +}
 159 +
 160 +static u32 mtk_i2c_r32(struct mtk_i2c *i2c, unsigned reg)
 161 +{
 162 +       return ioread32(i2c->base + reg);
 163 +}
 164 +
 165 +static int poll_down_timeout(void __iomem *addr, u32 mask)
 166 +{
 167 +       unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
 168 +
 169 +       do {
 170 +               if (!(readl_relaxed(addr) & mask))
 171 +                       return 0;
 172 +
 173 +               usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
 174 +       } while (time_before(jiffies, timeout));
 175 +
 176 +       return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
 177 +}
 178 +
 179 +static int mtk_i2c_wait_idle(struct mtk_i2c *i2c)
 180 +{
 181 +       int ret;
 182 +
 183 +       ret = poll_down_timeout(i2c->base + REG_SM0ST, I2C_BUSY);
 184 +       if (ret < 0)
 185 +               dev_dbg(i2c->dev, "idle err(%d)\n", ret);
 186 +
 187 +       return ret;
 188 +}
 189 +
 190 +static int poll_up_timeout(void __iomem *addr, u32 mask)
 191 +{
 192 +       unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
 193 +       u32 status;
 194 +
 195 +       do {
 196 +               status = readl_relaxed(addr);
 197 +               if (status & mask)
 198 +                       return 0;
 199 +               usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
 200 +       } while (time_before(jiffies, timeout));
 201 +
 202 +       return -ETIMEDOUT;
 203 +}
 204 +
 205 +static int mtk_i2c_wait_rx_done(struct mtk_i2c *i2c)
 206 +{
 207 +       int ret;
 208 +
 209 +       ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_DATARDY);
 210 +       if (ret < 0)
 211 +               dev_dbg(i2c->dev, "rx err(%d)\n", ret);
 212 +
 213 +       return ret;
 214 +}
 215 +
 216 +static int mtk_i2c_wait_tx_done(struct mtk_i2c *i2c)
 217 +{
 218 +       int ret;
 219 +
 220 +       ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_SDOEMPTY);
 221 +       if (ret < 0)
 222 +               dev_dbg(i2c->dev, "tx err(%d)\n", ret);
 223 +
 224 +       return ret;
 225 +}
 226 +
 227 +static void mtk_i2c_reset(struct mtk_i2c *i2c)
 228 +{
 229 +       u32 reg;
 230 +       device_reset(i2c->adap.dev.parent);
 231 +       barrier();
 232 +
 233 +       /* ctrl0 */
 234 +       reg = ODRAIN_HIGH_SM0 | VSYNC_PULSE | (i2c->clk_div << CLK_DIV_SHIFT) |
 235 +               WAIT_HIGH | SM0_EN;
 236 +       mtk_i2c_w32(i2c, reg, REG_SM0CTL0);
 237 +
 238 +       /* auto mode */
 239 +       mtk_i2c_w32(i2c, AUTOMODE_EN, REG_SM0CFG2);
 240 +}
 241 +
 242 +static void mtk_i2c_dump_reg(struct mtk_i2c *i2c)
 243 +{
 244 +       dev_dbg(i2c->dev, "cfg0 %08x, dout %08x, din %08x, " \
 245 +                       "status %08x, auto %08x, cfg1 %08x, " \
 246 +                       "cfg2 %08x, ctl0 %08x, ctl1 %08x\n",
 247 +                       mtk_i2c_r32(i2c, REG_SM0CFG0),
 248 +                       mtk_i2c_r32(i2c, REG_SM0DOUT),
 249 +                       mtk_i2c_r32(i2c, REG_SM0DIN),
 250 +                       mtk_i2c_r32(i2c, REG_SM0ST),
 251 +                       mtk_i2c_r32(i2c, REG_SM0AUTO),
 252 +                       mtk_i2c_r32(i2c, REG_SM0CFG1),
 253 +                       mtk_i2c_r32(i2c, REG_SM0CFG2),
 254 +                       mtk_i2c_r32(i2c, REG_SM0CTL0),
 255 +                       mtk_i2c_r32(i2c, REG_SM0CTL1));
 256 +}
 257 +
 258 +static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 259 +               int num)
 260 +{
 261 +       struct mtk_i2c *i2c;
 262 +       struct i2c_msg *pmsg;
 263 +       int i, j, ret;
 264 +       u32 cmd;
 265 +
 266 +       i2c = i2c_get_adapdata(adap);
 267 +
 268 +       for (i = 0; i < num; i++) {
 269 +               pmsg = &msgs[i];
 270 +               cmd = 0;
 271 +
 272 +               dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x\n",
 273 +                               pmsg->addr, pmsg->len, pmsg->flags);
 274 +
 275 +               /* wait hardware idle */
 276 +               if ((ret = mtk_i2c_wait_idle(i2c)))
 277 +                       goto err_timeout;
 278 +
 279 +               if (pmsg->flags & I2C_M_TEN) {
 280 +                       dev_dbg(i2c->dev, "10 bits addr not supported\n");
 281 +                       return -EINVAL;
 282 +               } else {
 283 +                       /* 7 bits address */
 284 +                       mtk_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
 285 +                                       REG_SM0CFG0);
 286 +               }
 287 +
 288 +               /* buffer length */
 289 +               if (pmsg->len == 0) {
 290 +                       dev_dbg(i2c->dev, "length is 0\n");
 291 +                       return -EINVAL;
 292 +               } else
 293 +                       mtk_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
 294 +                                       REG_SM0CFG1);
 295 +
 296 +               j = 0;
 297 +               if (pmsg->flags & I2C_M_RD) {
 298 +                       cmd |= READ_CMD;
 299 +                       /* start transfer */
 300 +                       barrier();
 301 +                       mtk_i2c_w32(i2c, cmd, REG_SM0AUTO);
 302 +                       do {
 303 +                               /* wait */
 304 +                               if ((ret = mtk_i2c_wait_rx_done(i2c)))
 305 +                                       goto err_timeout;
 306 +                               /* read data */
 307 +                               if (pmsg->len)
 308 +                                       pmsg->buf[j] = mtk_i2c_r32(i2c,
 309 +                                                       REG_SM0DIN);
 310 +                               j++;
 311 +                       } while (j < pmsg->len);
 312 +               } else {
 313 +                       do {
 314 +                               /* write data */
 315 +                               if (pmsg->len)
 316 +                                       mtk_i2c_w32(i2c, pmsg->buf[j],
 317 +                                                       REG_SM0DOUT);
 318 +                               /* start transfer */
 319 +                               if (j == 0) {
 320 +                                       barrier();
 321 +                                       mtk_i2c_w32(i2c, cmd, REG_SM0AUTO);
 322 +                               }
 323 +                               /* wait */
 324 +                               if ((ret = mtk_i2c_wait_tx_done(i2c)))
 325 +                                       goto err_timeout;
 326 +                               j++;
 327 +                       } while (j < pmsg->len);
 328 +               }
 329 +       }
 330 +       /* the return value is number of executed messages */
 331 +       ret = i;
 332 +
 333 +       return ret;
 334 +
 335 +err_timeout:
 336 +       mtk_i2c_dump_reg(i2c);
 337 +       mtk_i2c_reset(i2c);
 338 +       return ret;
 339 +}
 340 +
 341 +static u32 mtk_i2c_func(struct i2c_adapter *a)
 342 +{
 343 +       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 344 +}
 345 +
 346 +static const struct i2c_algorithm mtk_i2c_algo = {
 347 +       .master_xfer    = mtk_i2c_master_xfer,
 348 +       .functionality  = mtk_i2c_func,
 349 +};
 350 +
 351 +static const struct of_device_id i2c_mtk_dt_ids[] = {
 352 +       { .compatible = "mediatek,mt7621-i2c" },
 353 +       { /* sentinel */ }
 354 +};
 355 +
 356 +MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids);
 357 +
 358 +static struct i2c_adapter_quirks mtk_i2c_quirks = {
 359 +        .max_write_len = BYTECNT_MAX,
 360 +        .max_read_len = BYTECNT_MAX,
 361 +};
 362 +
 363 +static void mtk_i2c_init(struct mtk_i2c *i2c)
 364 +{
 365 +       i2c->clk_div = clk_get_rate(i2c->clk) / i2c->cur_clk;
 366 +       if (i2c->clk_div > CLK_DIV_MASK)
 367 +               i2c->clk_div = CLK_DIV_MASK;
 368 +
 369 +       mtk_i2c_reset(i2c);
 370 +}
 371 +
 372 +static int mtk_i2c_probe(struct platform_device *pdev)
 373 +{
 374 +       struct resource *res;
 375 +       struct mtk_i2c *i2c;
 376 +       struct i2c_adapter *adap;
 377 +       const struct of_device_id *match;
 378 +       int ret;
 379 +
 380 +       match = of_match_device(i2c_mtk_dt_ids, &pdev->dev);
 381 +
 382 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 383 +       if (!res) {
 384 +               dev_err(&pdev->dev, "no memory resource found\n");
 385 +               return -ENODEV;
 386 +       }
 387 +
 388 +       i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL);
 389 +       if (!i2c) {
 390 +               dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
 391 +               return -ENOMEM;
 392 +       }
 393 +
 394 +       i2c->base = devm_ioremap_resource(&pdev->dev, res);
 395 +       if (IS_ERR(i2c->base))
 396 +               return PTR_ERR(i2c->base);
 397 +
 398 +       i2c->clk = devm_clk_get(&pdev->dev, NULL);
 399 +       if (IS_ERR(i2c->clk)) {
 400 +               dev_err(&pdev->dev, "no clock defined\n");
 401 +               return -ENODEV;
 402 +       }
 403 +       clk_prepare_enable(i2c->clk);
 404 +       i2c->dev = &pdev->dev;
 405 +
 406 +       if (of_property_read_u32(pdev->dev.of_node,
 407 +                               "clock-frequency", &i2c->cur_clk))
 408 +               i2c->cur_clk = 100000;
 409 +
 410 +       adap = &i2c->adap;
 411 +       adap->owner = THIS_MODULE;
 412 +       adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 413 +       adap->algo = &mtk_i2c_algo;
 414 +       adap->retries = 3;
 415 +       adap->dev.parent = &pdev->dev;
 416 +       i2c_set_adapdata(adap, i2c);
 417 +       adap->dev.of_node = pdev->dev.of_node;
 418 +       strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
 419 +       adap->quirks = &mtk_i2c_quirks;
 420 +
 421 +       platform_set_drvdata(pdev, i2c);
 422 +
 423 +       mtk_i2c_init(i2c);
 424 +
 425 +       ret = i2c_add_adapter(adap);
 426 +       if (ret < 0) {
 427 +               dev_err(&pdev->dev, "failed to add adapter\n");
 428 +               clk_disable_unprepare(i2c->clk);
 429 +               return ret;
 430 +       }
 431 +
 432 +       dev_info(&pdev->dev, "clock %uKHz, re-start not support\n",
 433 +                       i2c->cur_clk/1000);
 434 +
 435 +       return ret;
 436 +}
 437 +
 438 +static int mtk_i2c_remove(struct platform_device *pdev)
 439 +{
 440 +       struct mtk_i2c *i2c = platform_get_drvdata(pdev);
 441 +
 442 +       i2c_del_adapter(&i2c->adap);
 443 +       clk_disable_unprepare(i2c->clk);
 444 +
 445 +       return 0;
 446 +}
 447 +
 448 +static struct platform_driver mtk_i2c_driver = {
 449 +       .probe          = mtk_i2c_probe,
 450 +       .remove         = mtk_i2c_remove,
 451 +       .driver         = {
 452 +               .owner  = THIS_MODULE,
 453 +               .name   = "i2c-mt7621",
 454 +               .of_match_table = i2c_mtk_dt_ids,
 455 +       },
 456 +};
 457 +
 458 +static int __init i2c_mtk_init (void)
 459 +{
 460 +       return platform_driver_register(&mtk_i2c_driver);
 461 +}
 462 +subsys_initcall(i2c_mtk_init);
 463 +
 464 +static void __exit i2c_mtk_exit (void)
 465 +{
 466 +       platform_driver_unregister(&mtk_i2c_driver);
 467 +}
 468 +module_exit(i2c_mtk_exit);
 469 +
 470 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
 471 +MODULE_DESCRIPTION("MT7621 I2c host driver");
 472 +MODULE_LICENSE("GPL");
 473 +MODULE_ALIAS("platform:MT7621-I2C");