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ramips: mt7620: eMMC: clear owner field
[openwrt/openwrt.git] / target / linux / ramips / patches-4.9 / 0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
1 From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 13 Nov 2014 19:08:40 +0100
4 Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mmc/host/Kconfig | 2 +
9 drivers/mmc/host/Makefile | 1 +
10 drivers/mmc/host/mtk-mmc/Kconfig | 16 +
11 drivers/mmc/host/mtk-mmc/Makefile | 42 +
12 drivers/mmc/host/mtk-mmc/board.h | 137 ++
13 drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++
14 drivers/mmc/host/mtk-mmc/dbg.h | 156 ++
15 drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
16 drivers/mmc/host/mtk-mmc/sd.c | 3060 ++++++++++++++++++++++++++++++++++
17 9 files changed, 4762 insertions(+)
18 create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
19 create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
20 create mode 100644 drivers/mmc/host/mtk-mmc/board.h
21 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
22 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
23 create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
24 create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
25
26 --- a/drivers/mmc/host/Kconfig
27 +++ b/drivers/mmc/host/Kconfig
28 @@ -798,3 +798,6 @@ config MMC_SDHCI_BRCMSTB
29 Broadcom STB SoCs.
30
31 If unsure, say Y.
32 +
33 +source "drivers/mmc/host/mtk-mmc/Kconfig"
34 +
35 --- a/drivers/mmc/host/Makefile
36 +++ b/drivers/mmc/host/Makefile
37 @@ -2,6 +2,7 @@
38 # Makefile for MMC/SD host controller drivers
39 #
40
41 +obj-$(CONFIG_MTK_MMC) += mtk-mmc/
42 obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
43 obj-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
44 obj-$(CONFIG_MMC_PXA) += pxamci.o
45 --- /dev/null
46 +++ b/drivers/mmc/host/mtk-mmc/Kconfig
47 @@ -0,0 +1,16 @@
48 +config MTK_MMC
49 + tristate "MTK SD/MMC"
50 + depends on !MTD_NAND_RALINK
51 +
52 +config MTK_AEE_KDUMP
53 + bool "MTK AEE KDUMP"
54 + depends on MTK_MMC
55 +
56 +config MTK_MMC_CD_POLL
57 + bool "Card Detect with Polling"
58 + depends on MTK_MMC
59 +
60 +config MTK_MMC_EMMC_8BIT
61 + bool "eMMC 8-bit support"
62 + depends on MTK_MMC && RALINK_MT7628
63 +
64 --- /dev/null
65 +++ b/drivers/mmc/host/mtk-mmc/Makefile
66 @@ -0,0 +1,42 @@
67 +# Copyright Statement:
68 +#
69 +# This software/firmware and related documentation ("MediaTek Software") are
70 +# protected under relevant copyright laws. The information contained herein
71 +# is confidential and proprietary to MediaTek Inc. and/or its licensors.
72 +# Without the prior written permission of MediaTek inc. and/or its licensors,
73 +# any reproduction, modification, use or disclosure of MediaTek Software,
74 +# and information contained herein, in whole or in part, shall be strictly prohibited.
75 +#
76 +# MediaTek Inc. (C) 2010. All rights reserved.
77 +#
78 +# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
79 +# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
80 +# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
81 +# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
82 +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
83 +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
84 +# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
85 +# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
86 +# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
87 +# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
88 +# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
89 +# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
90 +# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
91 +# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
92 +# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
93 +# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
94 +# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
95 +# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
96 +#
97 +# The following software/firmware and/or related documentation ("MediaTek Software")
98 +# have been modified by MediaTek Inc. All revisions are subject to any receiver's
99 +# applicable license agreements with MediaTek Inc.
100 +
101 +obj-$(CONFIG_MTK_MMC) += mtk_sd.o
102 +mtk_sd-objs := sd.o dbg.o
103 +ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
104 +EXTRA_CFLAGS += -DMT6575_SD_DEBUG
105 +endif
106 +
107 +clean:
108 + @rm -f *.o modules.order .*.cmd
109 --- /dev/null
110 +++ b/drivers/mmc/host/mtk-mmc/board.h
111 @@ -0,0 +1,137 @@
112 +/* Copyright Statement:
113 + *
114 + * This software/firmware and related documentation ("MediaTek Software") are
115 + * protected under relevant copyright laws. The information contained herein
116 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
117 + * Without the prior written permission of MediaTek inc. and/or its licensors,
118 + * any reproduction, modification, use or disclosure of MediaTek Software,
119 + * and information contained herein, in whole or in part, shall be strictly prohibited.
120 + */
121 +/* MediaTek Inc. (C) 2010. All rights reserved.
122 + *
123 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
124 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
125 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
126 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
127 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
128 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
129 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
130 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
131 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
132 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
133 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
134 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
135 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
136 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
137 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
138 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
139 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
140 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
141 + *
142 + * The following software/firmware and/or related documentation ("MediaTek Software")
143 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
144 + * applicable license agreements with MediaTek Inc.
145 + */
146 +
147 +#ifndef __ARCH_ARM_MACH_BOARD_H
148 +#define __ARCH_ARM_MACH_BOARD_H
149 +
150 +#include <generated/autoconf.h>
151 +#include <linux/pm.h>
152 +/* --- chhung */
153 +// #include <mach/mt6575.h>
154 +// #include <board-custom.h>
155 +/* end of chhung */
156 +
157 +typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
158 +typedef void (*pm_callback_t)(pm_message_t state, void *data);
159 +
160 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
161 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
162 +#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
163 +#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
164 +#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
165 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
166 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
167 +#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
168 +#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
169 +#define MSDC_DDR (1 << 9) /* ddr mode support */
170 +
171 +
172 +#define MSDC_SMPL_RISING (0)
173 +#define MSDC_SMPL_FALLING (1)
174 +
175 +#define MSDC_CMD_PIN (0)
176 +#define MSDC_DAT_PIN (1)
177 +#define MSDC_CD_PIN (2)
178 +#define MSDC_WP_PIN (3)
179 +#define MSDC_RST_PIN (4)
180 +
181 +enum {
182 + MSDC_CLKSRC_48MHZ = 0,
183 +// MSDC_CLKSRC_26MHZ = 0,
184 +// MSDC_CLKSRC_197MHZ = 1,
185 +// MSDC_CLKSRC_208MHZ = 2
186 +};
187 +
188 +struct msdc_hw {
189 + unsigned char clk_src; /* host clock source */
190 + unsigned char cmd_edge; /* command latch edge */
191 + unsigned char data_edge; /* data latch edge */
192 + unsigned char clk_drv; /* clock pad driving */
193 + unsigned char cmd_drv; /* command pad driving */
194 + unsigned char dat_drv; /* data pad driving */
195 + unsigned long flags; /* hardware capability flags */
196 + unsigned long data_pins; /* data pins */
197 + unsigned long data_offset; /* data address offset */
198 +
199 + /* config gpio pull mode */
200 + void (*config_gpio_pin)(int type, int pull);
201 +
202 + /* external power control for card */
203 + void (*ext_power_on)(void);
204 + void (*ext_power_off)(void);
205 +
206 + /* external sdio irq operations */
207 + void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
208 + void (*enable_sdio_eirq)(void);
209 + void (*disable_sdio_eirq)(void);
210 +
211 + /* external cd irq operations */
212 + void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
213 + void (*enable_cd_eirq)(void);
214 + void (*disable_cd_eirq)(void);
215 + int (*get_cd_status)(void);
216 +
217 + /* power management callback for external module */
218 + void (*register_pm)(pm_callback_t pm_cb, void *data);
219 +};
220 +
221 +extern struct msdc_hw msdc0_hw;
222 +extern struct msdc_hw msdc1_hw;
223 +extern struct msdc_hw msdc2_hw;
224 +extern struct msdc_hw msdc3_hw;
225 +
226 +/*GPS driver*/
227 +#define GPS_FLAG_FORCE_OFF 0x0001
228 +struct mt3326_gps_hardware {
229 + int (*ext_power_on)(int);
230 + int (*ext_power_off)(int);
231 +};
232 +extern struct mt3326_gps_hardware mt3326_gps_hw;
233 +
234 +/* NAND driver */
235 +struct mt6575_nand_host_hw {
236 + unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
237 + unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
238 + unsigned int nfi_cs_num; /* NFI_CS_NUM */
239 + unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
240 + unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
241 + unsigned int nand_ecc_size;
242 + unsigned int nand_ecc_bytes;
243 + unsigned int nand_ecc_mode;
244 +};
245 +extern struct mt6575_nand_host_hw mt6575_nand_hw;
246 +
247 +#endif /* __ARCH_ARM_MACH_BOARD_H */
248 +
249 --- /dev/null
250 +++ b/drivers/mmc/host/mtk-mmc/dbg.c
251 @@ -0,0 +1,347 @@
252 +/* Copyright Statement:
253 + *
254 + * This software/firmware and related documentation ("MediaTek Software") are
255 + * protected under relevant copyright laws. The information contained herein
256 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
257 + * Without the prior written permission of MediaTek inc. and/or its licensors,
258 + * any reproduction, modification, use or disclosure of MediaTek Software,
259 + * and information contained herein, in whole or in part, shall be strictly prohibited.
260 + *
261 + * MediaTek Inc. (C) 2010. All rights reserved.
262 + *
263 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
264 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
265 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
266 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
267 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
268 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
269 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
270 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
271 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
272 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
273 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
274 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
275 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
276 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
277 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
278 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
279 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
280 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
281 + *
282 + * The following software/firmware and/or related documentation ("MediaTek Software")
283 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
284 + * applicable license agreements with MediaTek Inc.
285 + */
286 +
287 +#include <linux/version.h>
288 +#include <linux/kernel.h>
289 +#include <linux/sched.h>
290 +#include <linux/kthread.h>
291 +#include <linux/delay.h>
292 +#include <linux/module.h>
293 +#include <linux/init.h>
294 +#include <linux/proc_fs.h>
295 +#include <linux/string.h>
296 +#include <linux/uaccess.h>
297 +// #include <mach/mt6575_gpt.h> /* --- by chhung */
298 +#include "dbg.h"
299 +#include "mt6575_sd.h"
300 +#include <linux/seq_file.h>
301 +
302 +static char cmd_buf[256];
303 +
304 +/* for debug zone */
305 +unsigned int sd_debug_zone[4]={
306 + 0,
307 + 0,
308 + 0,
309 + 0
310 +};
311 +
312 +/* mode select */
313 +u32 dma_size[4]={
314 + 512,
315 + 512,
316 + 512,
317 + 512
318 +};
319 +msdc_mode drv_mode[4]={
320 + MODE_SIZE_DEP, /* using DMA or not depend on the size */
321 + MODE_SIZE_DEP,
322 + MODE_SIZE_DEP,
323 + MODE_SIZE_DEP
324 +};
325 +
326 +#if defined (MT6575_SD_DEBUG)
327 +/* for driver profile */
328 +#define TICKS_ONE_MS (13000)
329 +u32 gpt_enable = 0;
330 +u32 sdio_pro_enable = 0; /* make sure gpt is enabled */
331 +u32 sdio_pro_time = 0; /* no more than 30s */
332 +struct sdio_profile sdio_perfomance = {0};
333 +
334 +#if 0 /* --- chhung */
335 +void msdc_init_gpt(void)
336 +{
337 + GPT_CONFIG config;
338 +
339 + config.num = GPT6;
340 + config.mode = GPT_FREE_RUN;
341 + config.clkSrc = GPT_CLK_SRC_SYS;
342 + config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
343 +
344 + if (GPT_Config(config) == FALSE )
345 + return;
346 +
347 + GPT_Start(GPT6);
348 +}
349 +#endif /* end of --- */
350 +
351 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
352 +{
353 + u32 ret = 0;
354 +
355 + if (new_H32 == old_H32) {
356 + ret = new_L32 - old_L32;
357 + } else if(new_H32 == (old_H32 + 1)) {
358 + if (new_L32 > old_L32) {
359 + printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
360 + }
361 + ret = (0xffffffff - old_L32);
362 + ret += new_L32;
363 + } else {
364 + printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
365 + }
366 +
367 + return ret;
368 +}
369 +
370 +void msdc_sdio_profile(struct sdio_profile* result)
371 +{
372 + struct cmd_profile* cmd;
373 + u32 i;
374 +
375 + printk("sdio === performance dump ===\n");
376 + printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
377 + result->total_tc, result->total_tc / TICKS_ONE_MS,
378 + result->total_tx_bytes, result->total_rx_bytes);
379 +
380 + /* CMD52 Dump */
381 + cmd = &result->cmd52_rx;
382 + printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
383 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
384 + cmd = &result->cmd52_tx;
385 + printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
386 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
387 +
388 + /* CMD53 Rx bytes + block mode */
389 + for (i=0; i<512; i++) {
390 + cmd = &result->cmd53_rx_byte[i];
391 + if (cmd->count) {
392 + printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
393 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
394 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
395 + }
396 + }
397 + for (i=0; i<100; i++) {
398 + cmd = &result->cmd53_rx_blk[i];
399 + if (cmd->count) {
400 + printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
401 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
402 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
403 + }
404 + }
405 +
406 + /* CMD53 Tx bytes + block mode */
407 + for (i=0; i<512; i++) {
408 + cmd = &result->cmd53_tx_byte[i];
409 + if (cmd->count) {
410 + printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
411 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
412 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
413 + }
414 + }
415 + for (i=0; i<100; i++) {
416 + cmd = &result->cmd53_tx_blk[i];
417 + if (cmd->count) {
418 + printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
419 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
420 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
421 + }
422 + }
423 +
424 + printk("sdio === performance dump done ===\n");
425 +}
426 +
427 +//========= sdio command table ===========
428 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
429 +{
430 + struct sdio_profile* result = &sdio_perfomance;
431 + struct cmd_profile* cmd;
432 + u32 block;
433 +
434 + if (sdio_pro_enable == 0) {
435 + return;
436 + }
437 +
438 + if (opcode == 52) {
439 + cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
440 + } else if (opcode == 53) {
441 + if (sizes < 512) {
442 + cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
443 + } else {
444 + block = sizes / 512;
445 + if (block >= 99) {
446 + printk("cmd53 error blocks\n");
447 + while(1);
448 + }
449 + cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
450 + }
451 + } else {
452 + return;
453 + }
454 +
455 + /* update the members */
456 + if (ticks > cmd->max_tc){
457 + cmd->max_tc = ticks;
458 + }
459 + if (cmd->min_tc == 0 || ticks < cmd->min_tc) {
460 + cmd->min_tc = ticks;
461 + }
462 + cmd->tot_tc += ticks;
463 + cmd->tot_bytes += sizes;
464 + cmd->count ++;
465 +
466 + if (bRx) {
467 + result->total_rx_bytes += sizes;
468 + } else {
469 + result->total_tx_bytes += sizes;
470 + }
471 + result->total_tc += ticks;
472 +
473 + /* dump when total_tc > 30s */
474 + if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
475 + msdc_sdio_profile(result);
476 + memset(result, 0 , sizeof(struct sdio_profile));
477 + }
478 +}
479 +
480 +//========== driver proc interface ===========
481 +static int msdc_debug_proc_read(struct seq_file *s, void *p)
482 +{
483 + seq_printf(s, "\n=========================================\n");
484 + seq_printf(s, "Index<0> + Id + Zone\n");
485 + seq_printf(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
486 + seq_printf(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
487 + seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
488 + seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
489 + seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
490 + seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
491 +
492 + seq_printf(s, "Index<1> + ID:4|Mode:4 + DMA_SIZE\n");
493 + seq_printf(s, "-> 0)PIO 1)DMA 2)SIZE\n");
494 + seq_printf(s, "-> echo 1 22 0x200 >msdc_bebug -> host[2] size mode, dma when >= 512\n");
495 + seq_printf(s, "-> MSDC[0] mode<%d> size<%d>\n", drv_mode[0], dma_size[0]);
496 + seq_printf(s, "-> MSDC[1] mode<%d> size<%d>\n", drv_mode[1], dma_size[1]);
497 + seq_printf(s, "-> MSDC[2] mode<%d> size<%d>\n", drv_mode[2], dma_size[2]);
498 + seq_printf(s, "-> MSDC[3] mode<%d> size<%d>\n", drv_mode[3], dma_size[3]);
499 +
500 + seq_printf(s, "Index<3> + SDIO_PROFILE + TIME\n");
501 + seq_printf(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
502 + seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
503 + seq_printf(s, "=========================================\n\n");
504 +
505 + return 0;
506 +}
507 +
508 +static ssize_t msdc_debug_proc_write(struct file *file,
509 + const char __user *buf, size_t count, loff_t *data)
510 +{
511 + int ret;
512 +
513 + int cmd, p1, p2;
514 + int id, zone;
515 + int mode, size;
516 +
517 + if (count == 0)return -1;
518 + if(count > 255)count = 255;
519 +
520 + ret = copy_from_user(cmd_buf, buf, count);
521 + if (ret < 0)return -1;
522 +
523 + cmd_buf[count] = '\0';
524 + printk("msdc Write %s\n", cmd_buf);
525 +
526 + sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
527 +
528 + if(cmd == SD_TOOL_ZONE) {
529 + id = p1; zone = p2; zone &= 0x3ff;
530 + printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
531 + if(id >=0 && id<=3){
532 + sd_debug_zone[id] = zone;
533 + }
534 + else if(id == 4){
535 + sd_debug_zone[0] = sd_debug_zone[1] = zone;
536 + sd_debug_zone[2] = sd_debug_zone[3] = zone;
537 + }
538 + else{
539 + printk("msdc host_id error when set debug zone\n");
540 + }
541 + } else if (cmd == SD_TOOL_DMA_SIZE) {
542 + id = p1>>4; mode = (p1&0xf); size = p2;
543 + if(id >=0 && id<=3){
544 + drv_mode[id] = mode;
545 + dma_size[id] = p2;
546 + }
547 + else if(id == 4){
548 + drv_mode[0] = drv_mode[1] = mode;
549 + drv_mode[2] = drv_mode[3] = mode;
550 + dma_size[0] = dma_size[1] = p2;
551 + dma_size[2] = dma_size[3] = p2;
552 + }
553 + else{
554 + printk("msdc host_id error when select mode\n");
555 + }
556 + } else if (cmd == SD_TOOL_SDIO_PROFILE) {
557 + if (p1 == 1) { /* enable profile */
558 + if (gpt_enable == 0) {
559 + // msdc_init_gpt(); /* --- by chhung */
560 + gpt_enable = 1;
561 + }
562 + sdio_pro_enable = 1;
563 + if (p2 == 0) p2 = 1; if (p2 >= 30) p2 = 30;
564 + sdio_pro_time = p2 ;
565 + } else if (p1 == 0) {
566 + /* todo */
567 + sdio_pro_enable = 0;
568 + }
569 + }
570 +
571 + return count;
572 +}
573 +
574 +static int msdc_debug_show(struct inode *inode, struct file *file)
575 +{
576 + return single_open(file, msdc_debug_proc_read, NULL);
577 +}
578 +
579 +static const struct file_operations msdc_debug_fops = {
580 + .owner = THIS_MODULE,
581 + .open = msdc_debug_show,
582 + .read = seq_read,
583 + .write = msdc_debug_proc_write,
584 + .llseek = seq_lseek,
585 + .release = single_release,
586 +};
587 +
588 +int msdc_debug_proc_init(void)
589 +{
590 + struct proc_dir_entry *de = proc_create("msdc_debug", 0667, NULL, &msdc_debug_fops);
591 +
592 + if (!de || IS_ERR(de))
593 + printk("!! Create MSDC debug PROC fail !!\n");
594 +
595 + return 0 ;
596 +}
597 +EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
598 +#endif
599 --- /dev/null
600 +++ b/drivers/mmc/host/mtk-mmc/dbg.h
601 @@ -0,0 +1,156 @@
602 +/* Copyright Statement:
603 + *
604 + * This software/firmware and related documentation ("MediaTek Software") are
605 + * protected under relevant copyright laws. The information contained herein
606 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
607 + * Without the prior written permission of MediaTek inc. and/or its licensors,
608 + * any reproduction, modification, use or disclosure of MediaTek Software,
609 + * and information contained herein, in whole or in part, shall be strictly prohibited.
610 + *
611 + * MediaTek Inc. (C) 2010. All rights reserved.
612 + *
613 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
614 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
615 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
616 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
617 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
618 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
619 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
620 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
621 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
622 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
623 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
624 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
625 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
626 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
627 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
628 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
629 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
630 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
631 + *
632 + * The following software/firmware and/or related documentation ("MediaTek Software")
633 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
634 + * applicable license agreements with MediaTek Inc.
635 + */
636 +#ifndef __MT_MSDC_DEUBG__
637 +#define __MT_MSDC_DEUBG__
638 +
639 +//==========================
640 +extern u32 sdio_pro_enable;
641 +/* for a type command, e.g. CMD53, 2 blocks */
642 +struct cmd_profile {
643 + u32 max_tc; /* Max tick count */
644 + u32 min_tc;
645 + u32 tot_tc; /* total tick count */
646 + u32 tot_bytes;
647 + u32 count; /* the counts of the command */
648 +};
649 +
650 +/* dump when total_tc and total_bytes */
651 +struct sdio_profile {
652 + u32 total_tc; /* total tick count of CMD52 and CMD53 */
653 + u32 total_tx_bytes; /* total bytes of CMD53 Tx */
654 + u32 total_rx_bytes; /* total bytes of CMD53 Rx */
655 +
656 + /*CMD52*/
657 + struct cmd_profile cmd52_tx;
658 + struct cmd_profile cmd52_rx;
659 +
660 + /*CMD53 in byte unit */
661 + struct cmd_profile cmd53_tx_byte[512];
662 + struct cmd_profile cmd53_rx_byte[512];
663 +
664 + /*CMD53 in block unit */
665 + struct cmd_profile cmd53_tx_blk[100];
666 + struct cmd_profile cmd53_rx_blk[100];
667 +};
668 +
669 +//==========================
670 +typedef enum {
671 + SD_TOOL_ZONE = 0,
672 + SD_TOOL_DMA_SIZE = 1,
673 + SD_TOOL_PM_ENABLE = 2,
674 + SD_TOOL_SDIO_PROFILE = 3,
675 +} msdc_dbg;
676 +
677 +typedef enum {
678 + MODE_PIO = 0,
679 + MODE_DMA = 1,
680 + MODE_SIZE_DEP = 2,
681 +} msdc_mode;
682 +extern msdc_mode drv_mode[4];
683 +extern u32 dma_size[4];
684 +
685 +/* Debug message event */
686 +#define DBG_EVT_NONE (0) /* No event */
687 +#define DBG_EVT_DMA (1 << 0) /* DMA related event */
688 +#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
689 +#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
690 +#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
691 +#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
692 +#define DBG_EVT_FUC (1 << 5) /* Function event */
693 +#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
694 +#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
695 +#define DBG_EVT_WRN (1 << 8) /* Warning event */
696 +#define DBG_EVT_PWR (1 << 9) /* Power event */
697 +#define DBG_EVT_ALL (0xffffffff)
698 +
699 +#define DBG_EVT_MASK (DBG_EVT_ALL)
700 +
701 +extern unsigned int sd_debug_zone[4];
702 +#define TAG "msdc"
703 +#if 0 /* +++ chhung */
704 +#define BUG_ON(x) \
705 +do { \
706 + if (x) { \
707 + printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
708 + while(1); \
709 + } \
710 +}while(0)
711 +#endif /* end of +++ */
712 +
713 +#define N_MSG(evt, fmt, args...)
714 +/*
715 +do { \
716 + if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
717 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
718 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
719 + } \
720 +} while(0)
721 +*/
722 +
723 +#define ERR_MSG(fmt, args...) \
724 +do { \
725 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
726 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
727 +} while(0);
728 +
729 +#if 1
730 +//defined CONFIG_MTK_MMC_CD_POLL
731 +#define INIT_MSG(fmt, args...)
732 +#define IRQ_MSG(fmt, args...)
733 +#else
734 +#define INIT_MSG(fmt, args...) \
735 +do { \
736 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
737 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
738 +} while(0);
739 +
740 +/* PID in ISR in not corrent */
741 +#define IRQ_MSG(fmt, args...) \
742 +do { \
743 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
744 + host->id, ##args , __FUNCTION__, __LINE__); \
745 +} while(0);
746 +#endif
747 +
748 +int msdc_debug_proc_init(void);
749 +
750 +#if 0 /* --- chhung */
751 +void msdc_init_gpt(void);
752 +extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
753 +#endif /* end of --- */
754 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
755 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
756 +
757 +#endif
758 --- /dev/null
759 +++ b/drivers/mmc/host/mtk-mmc/mt6575_sd.h
760 @@ -0,0 +1,1001 @@
761 +/* Copyright Statement:
762 + *
763 + * This software/firmware and related documentation ("MediaTek Software") are
764 + * protected under relevant copyright laws. The information contained herein
765 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
766 + * Without the prior written permission of MediaTek inc. and/or its licensors,
767 + * any reproduction, modification, use or disclosure of MediaTek Software,
768 + * and information contained herein, in whole or in part, shall be strictly prohibited.
769 + */
770 +/* MediaTek Inc. (C) 2010. All rights reserved.
771 + *
772 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
773 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
774 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
775 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
776 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
777 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
778 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
779 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
780 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
781 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
782 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
783 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
784 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
785 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
786 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
787 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
788 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
789 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
790 + *
791 + * The following software/firmware and/or related documentation ("MediaTek Software")
792 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
793 + * applicable license agreements with MediaTek Inc.
794 + */
795 +
796 +#ifndef MT6575_SD_H
797 +#define MT6575_SD_H
798 +
799 +#include <linux/bitops.h>
800 +#include <linux/mmc/host.h>
801 +
802 +// #include <mach/mt6575_reg_base.h> /* --- by chhung */
803 +
804 +/*--------------------------------------------------------------------------*/
805 +/* Common Macro */
806 +/*--------------------------------------------------------------------------*/
807 +#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
808 +
809 +/*--------------------------------------------------------------------------*/
810 +/* Common Definition */
811 +/*--------------------------------------------------------------------------*/
812 +#define MSDC_FIFO_SZ (128)
813 +#define MSDC_FIFO_THD (64) // (128)
814 +#define MSDC_NUM (4)
815 +
816 +#define MSDC_MS (0)
817 +#define MSDC_SDMMC (1)
818 +
819 +#define MSDC_MODE_UNKNOWN (0)
820 +#define MSDC_MODE_PIO (1)
821 +#define MSDC_MODE_DMA_BASIC (2)
822 +#define MSDC_MODE_DMA_DESC (3)
823 +#define MSDC_MODE_DMA_ENHANCED (4)
824 +#define MSDC_MODE_MMC_STREAM (5)
825 +
826 +#define MSDC_BUS_1BITS (0)
827 +#define MSDC_BUS_4BITS (1)
828 +#define MSDC_BUS_8BITS (2)
829 +
830 +#define MSDC_BRUST_8B (3)
831 +#define MSDC_BRUST_16B (4)
832 +#define MSDC_BRUST_32B (5)
833 +#define MSDC_BRUST_64B (6)
834 +
835 +#define MSDC_PIN_PULL_NONE (0)
836 +#define MSDC_PIN_PULL_DOWN (1)
837 +#define MSDC_PIN_PULL_UP (2)
838 +#define MSDC_PIN_KEEP (3)
839 +
840 +#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
841 +#define MSDC_MIN_SCLK (260000)
842 +
843 +#define MSDC_AUTOCMD12 (0x0001)
844 +#define MSDC_AUTOCMD23 (0x0002)
845 +#define MSDC_AUTOCMD19 (0x0003)
846 +
847 +#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
848 +#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
849 +
850 +enum {
851 + RESP_NONE = 0,
852 + RESP_R1,
853 + RESP_R2,
854 + RESP_R3,
855 + RESP_R4,
856 + RESP_R5,
857 + RESP_R6,
858 + RESP_R7,
859 + RESP_R1B
860 +};
861 +
862 +/*--------------------------------------------------------------------------*/
863 +/* Register Offset */
864 +/*--------------------------------------------------------------------------*/
865 +#define OFFSET_MSDC_CFG (0x0)
866 +#define OFFSET_MSDC_IOCON (0x04)
867 +#define OFFSET_MSDC_PS (0x08)
868 +#define OFFSET_MSDC_INT (0x0c)
869 +#define OFFSET_MSDC_INTEN (0x10)
870 +#define OFFSET_MSDC_FIFOCS (0x14)
871 +#define OFFSET_MSDC_TXDATA (0x18)
872 +#define OFFSET_MSDC_RXDATA (0x1c)
873 +#define OFFSET_SDC_CFG (0x30)
874 +#define OFFSET_SDC_CMD (0x34)
875 +#define OFFSET_SDC_ARG (0x38)
876 +#define OFFSET_SDC_STS (0x3c)
877 +#define OFFSET_SDC_RESP0 (0x40)
878 +#define OFFSET_SDC_RESP1 (0x44)
879 +#define OFFSET_SDC_RESP2 (0x48)
880 +#define OFFSET_SDC_RESP3 (0x4c)
881 +#define OFFSET_SDC_BLK_NUM (0x50)
882 +#define OFFSET_SDC_CSTS (0x58)
883 +#define OFFSET_SDC_CSTS_EN (0x5c)
884 +#define OFFSET_SDC_DCRC_STS (0x60)
885 +#define OFFSET_EMMC_CFG0 (0x70)
886 +#define OFFSET_EMMC_CFG1 (0x74)
887 +#define OFFSET_EMMC_STS (0x78)
888 +#define OFFSET_EMMC_IOCON (0x7c)
889 +#define OFFSET_SDC_ACMD_RESP (0x80)
890 +#define OFFSET_SDC_ACMD19_TRG (0x84)
891 +#define OFFSET_SDC_ACMD19_STS (0x88)
892 +#define OFFSET_MSDC_DMA_SA (0x90)
893 +#define OFFSET_MSDC_DMA_CA (0x94)
894 +#define OFFSET_MSDC_DMA_CTRL (0x98)
895 +#define OFFSET_MSDC_DMA_CFG (0x9c)
896 +#define OFFSET_MSDC_DBG_SEL (0xa0)
897 +#define OFFSET_MSDC_DBG_OUT (0xa4)
898 +#define OFFSET_MSDC_PATCH_BIT (0xb0)
899 +#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
900 +#define OFFSET_MSDC_PAD_CTL0 (0xe0)
901 +#define OFFSET_MSDC_PAD_CTL1 (0xe4)
902 +#define OFFSET_MSDC_PAD_CTL2 (0xe8)
903 +#define OFFSET_MSDC_PAD_TUNE (0xec)
904 +#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
905 +#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
906 +#define OFFSET_MSDC_HW_DBG (0xf8)
907 +#define OFFSET_MSDC_VERSION (0x100)
908 +#define OFFSET_MSDC_ECO_VER (0x104)
909 +
910 +/*--------------------------------------------------------------------------*/
911 +/* Register Address */
912 +/*--------------------------------------------------------------------------*/
913 +
914 +/* common register */
915 +#define MSDC_CFG REG_ADDR(MSDC_CFG)
916 +#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
917 +#define MSDC_PS REG_ADDR(MSDC_PS)
918 +#define MSDC_INT REG_ADDR(MSDC_INT)
919 +#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
920 +#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
921 +#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
922 +#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
923 +#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
924 +
925 +/* sdmmc register */
926 +#define SDC_CFG REG_ADDR(SDC_CFG)
927 +#define SDC_CMD REG_ADDR(SDC_CMD)
928 +#define SDC_ARG REG_ADDR(SDC_ARG)
929 +#define SDC_STS REG_ADDR(SDC_STS)
930 +#define SDC_RESP0 REG_ADDR(SDC_RESP0)
931 +#define SDC_RESP1 REG_ADDR(SDC_RESP1)
932 +#define SDC_RESP2 REG_ADDR(SDC_RESP2)
933 +#define SDC_RESP3 REG_ADDR(SDC_RESP3)
934 +#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
935 +#define SDC_CSTS REG_ADDR(SDC_CSTS)
936 +#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
937 +#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
938 +
939 +/* emmc register*/
940 +#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
941 +#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
942 +#define EMMC_STS REG_ADDR(EMMC_STS)
943 +#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
944 +
945 +/* auto command register */
946 +#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
947 +#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
948 +#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
949 +
950 +/* dma register */
951 +#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
952 +#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
953 +#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
954 +#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
955 +
956 +/* pad ctrl register */
957 +#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
958 +#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
959 +#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
960 +
961 +/* data read delay */
962 +#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
963 +#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
964 +
965 +/* debug register */
966 +#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
967 +#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
968 +
969 +/* misc register */
970 +#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
971 +#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
972 +#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
973 +#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
974 +#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
975 +#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
976 +
977 +/*--------------------------------------------------------------------------*/
978 +/* Register Mask */
979 +/*--------------------------------------------------------------------------*/
980 +
981 +/* MSDC_CFG mask */
982 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
983 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
984 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
985 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
986 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
987 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
988 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
989 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
990 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
991 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
992 +
993 +/* MSDC_IOCON mask */
994 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
995 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
996 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
997 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
998 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
999 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
1000 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
1001 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
1002 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
1003 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
1004 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
1005 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
1006 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
1007 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
1008 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
1009 +
1010 +/* MSDC_PS mask */
1011 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
1012 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
1013 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
1014 +#define MSDC_PS_DAT (0xff << 16) /* R */
1015 +#define MSDC_PS_CMD (0x1 << 24) /* R */
1016 +#define MSDC_PS_WP (0x1UL<< 31) /* R */
1017 +
1018 +/* MSDC_INT mask */
1019 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
1020 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
1021 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
1022 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
1023 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
1024 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
1025 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
1026 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
1027 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
1028 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
1029 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
1030 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
1031 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
1032 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
1033 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
1034 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
1035 +
1036 +/* MSDC_INTEN mask */
1037 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
1038 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
1039 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
1040 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
1041 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
1042 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
1043 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
1044 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
1045 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
1046 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
1047 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
1048 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
1049 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
1050 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
1051 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
1052 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
1053 +
1054 +/* MSDC_FIFOCS mask */
1055 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
1056 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
1057 +#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
1058 +
1059 +/* SDC_CFG mask */
1060 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
1061 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
1062 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
1063 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
1064 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
1065 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
1066 +#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
1067 +
1068 +/* SDC_CMD mask */
1069 +#define SDC_CMD_OPC (0x3f << 0) /* RW */
1070 +#define SDC_CMD_BRK (0x1 << 6) /* RW */
1071 +#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
1072 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1073 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1074 +#define SDC_CMD_RW (0x1 << 13) /* RW */
1075 +#define SDC_CMD_STOP (0x1 << 14) /* RW */
1076 +#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
1077 +#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
1078 +#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
1079 +#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
1080 +
1081 +/* SDC_STS mask */
1082 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
1083 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
1084 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
1085 +
1086 +/* SDC_DCRC_STS mask */
1087 +#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
1088 +#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
1089 +
1090 +/* EMMC_CFG0 mask */
1091 +#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
1092 +#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
1093 +#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
1094 +#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
1095 +#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
1096 +#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
1097 +
1098 +/* EMMC_CFG1 mask */
1099 +#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
1100 +#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
1101 +
1102 +/* EMMC_STS mask */
1103 +#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
1104 +#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
1105 +#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
1106 +#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
1107 +#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
1108 +#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
1109 +#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
1110 +
1111 +/* EMMC_IOCON mask */
1112 +#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
1113 +
1114 +/* SDC_ACMD19_TRG mask */
1115 +#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
1116 +
1117 +/* MSDC_DMA_CTRL mask */
1118 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
1119 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
1120 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
1121 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
1122 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
1123 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
1124 +#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
1125 +
1126 +/* MSDC_DMA_CFG mask */
1127 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
1128 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
1129 +#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
1130 +#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
1131 +
1132 +/* MSDC_PATCH_BIT mask */
1133 +#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
1134 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
1135 +#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
1136 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
1137 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
1138 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
1139 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
1140 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
1141 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
1142 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
1143 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
1144 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
1145 +
1146 +/* MSDC_PATCH_BIT1 mask */
1147 +#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
1148 +#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
1149 +
1150 +/* MSDC_PAD_CTL0 mask */
1151 +#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
1152 +#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
1153 +#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
1154 +#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
1155 +#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
1156 +#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
1157 +#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
1158 +#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
1159 +#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
1160 +
1161 +/* MSDC_PAD_CTL1 mask */
1162 +#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
1163 +#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
1164 +#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
1165 +#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
1166 +#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
1167 +#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
1168 +#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
1169 +#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
1170 +#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
1171 +
1172 +/* MSDC_PAD_CTL2 mask */
1173 +#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
1174 +#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
1175 +#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
1176 +#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
1177 +#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
1178 +#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
1179 +#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
1180 +#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
1181 +#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
1182 +
1183 +/* MSDC_PAD_TUNE mask */
1184 +#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
1185 +#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
1186 +#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
1187 +#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
1188 +#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
1189 +
1190 +/* MSDC_DAT_RDDLY0/1 mask */
1191 +#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
1192 +#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
1193 +#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
1194 +#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
1195 +
1196 +#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
1197 +#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
1198 +#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
1199 +#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
1200 +
1201 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
1202 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
1203 +#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
1204 +#define CARD_READY_FOR_DATA (1<<8)
1205 +#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
1206 +
1207 +/*--------------------------------------------------------------------------*/
1208 +/* Descriptor Structure */
1209 +/*--------------------------------------------------------------------------*/
1210 +typedef struct {
1211 + u32 hwo:1; /* could be changed by hw */
1212 + u32 bdp:1;
1213 + u32 rsv0:6;
1214 + u32 chksum:8;
1215 + u32 intr:1;
1216 + u32 rsv1:15;
1217 + void *next;
1218 + void *ptr;
1219 + u32 buflen:16;
1220 + u32 extlen:8;
1221 + u32 rsv2:8;
1222 + u32 arg;
1223 + u32 blknum;
1224 + u32 cmd;
1225 +} gpd_t;
1226 +
1227 +typedef struct {
1228 + u32 eol:1;
1229 + u32 rsv0:7;
1230 + u32 chksum:8;
1231 + u32 rsv1:1;
1232 + u32 blkpad:1;
1233 + u32 dwpad:1;
1234 + u32 rsv2:13;
1235 + void *next;
1236 + void *ptr;
1237 + u32 buflen:16;
1238 + u32 rsv3:16;
1239 +} bd_t;
1240 +
1241 +/*--------------------------------------------------------------------------*/
1242 +/* Register Debugging Structure */
1243 +/*--------------------------------------------------------------------------*/
1244 +
1245 +typedef struct {
1246 + u32 msdc:1;
1247 + u32 ckpwn:1;
1248 + u32 rst:1;
1249 + u32 pio:1;
1250 + u32 ckdrven:1;
1251 + u32 start18v:1;
1252 + u32 pass18v:1;
1253 + u32 ckstb:1;
1254 + u32 ckdiv:8;
1255 + u32 ckmod:2;
1256 + u32 pad:14;
1257 +} msdc_cfg_reg;
1258 +typedef struct {
1259 + u32 sdr104cksel:1;
1260 + u32 rsmpl:1;
1261 + u32 dsmpl:1;
1262 + u32 ddlysel:1;
1263 + u32 ddr50ckd:1;
1264 + u32 dsplsel:1;
1265 + u32 pad1:10;
1266 + u32 d0spl:1;
1267 + u32 d1spl:1;
1268 + u32 d2spl:1;
1269 + u32 d3spl:1;
1270 + u32 d4spl:1;
1271 + u32 d5spl:1;
1272 + u32 d6spl:1;
1273 + u32 d7spl:1;
1274 + u32 riscsz:1;
1275 + u32 pad2:7;
1276 +} msdc_iocon_reg;
1277 +typedef struct {
1278 + u32 cden:1;
1279 + u32 cdsts:1;
1280 + u32 pad1:10;
1281 + u32 cddebounce:4;
1282 + u32 dat:8;
1283 + u32 cmd:1;
1284 + u32 pad2:6;
1285 + u32 wp:1;
1286 +} msdc_ps_reg;
1287 +typedef struct {
1288 + u32 mmcirq:1;
1289 + u32 cdsc:1;
1290 + u32 pad1:1;
1291 + u32 atocmdrdy:1;
1292 + u32 atocmdtmo:1;
1293 + u32 atocmdcrc:1;
1294 + u32 dmaqempty:1;
1295 + u32 sdioirq:1;
1296 + u32 cmdrdy:1;
1297 + u32 cmdtmo:1;
1298 + u32 rspcrc:1;
1299 + u32 csta:1;
1300 + u32 xfercomp:1;
1301 + u32 dxferdone:1;
1302 + u32 dattmo:1;
1303 + u32 datcrc:1;
1304 + u32 atocmd19done:1;
1305 + u32 pad2:15;
1306 +} msdc_int_reg;
1307 +typedef struct {
1308 + u32 mmcirq:1;
1309 + u32 cdsc:1;
1310 + u32 pad1:1;
1311 + u32 atocmdrdy:1;
1312 + u32 atocmdtmo:1;
1313 + u32 atocmdcrc:1;
1314 + u32 dmaqempty:1;
1315 + u32 sdioirq:1;
1316 + u32 cmdrdy:1;
1317 + u32 cmdtmo:1;
1318 + u32 rspcrc:1;
1319 + u32 csta:1;
1320 + u32 xfercomp:1;
1321 + u32 dxferdone:1;
1322 + u32 dattmo:1;
1323 + u32 datcrc:1;
1324 + u32 atocmd19done:1;
1325 + u32 pad2:15;
1326 +} msdc_inten_reg;
1327 +typedef struct {
1328 + u32 rxcnt:8;
1329 + u32 pad1:8;
1330 + u32 txcnt:8;
1331 + u32 pad2:7;
1332 + u32 clr:1;
1333 +} msdc_fifocs_reg;
1334 +typedef struct {
1335 + u32 val;
1336 +} msdc_txdat_reg;
1337 +typedef struct {
1338 + u32 val;
1339 +} msdc_rxdat_reg;
1340 +typedef struct {
1341 + u32 sdiowkup:1;
1342 + u32 inswkup:1;
1343 + u32 pad1:14;
1344 + u32 buswidth:2;
1345 + u32 pad2:1;
1346 + u32 sdio:1;
1347 + u32 sdioide:1;
1348 + u32 intblkgap:1;
1349 + u32 pad4:2;
1350 + u32 dtoc:8;
1351 +} sdc_cfg_reg;
1352 +typedef struct {
1353 + u32 cmd:6;
1354 + u32 brk:1;
1355 + u32 rsptyp:3;
1356 + u32 pad1:1;
1357 + u32 dtype:2;
1358 + u32 rw:1;
1359 + u32 stop:1;
1360 + u32 goirq:1;
1361 + u32 blklen:12;
1362 + u32 atocmd:2;
1363 + u32 volswth:1;
1364 + u32 pad2:1;
1365 +} sdc_cmd_reg;
1366 +typedef struct {
1367 + u32 arg;
1368 +} sdc_arg_reg;
1369 +typedef struct {
1370 + u32 sdcbusy:1;
1371 + u32 cmdbusy:1;
1372 + u32 pad:29;
1373 + u32 swrcmpl:1;
1374 +} sdc_sts_reg;
1375 +typedef struct {
1376 + u32 val;
1377 +} sdc_resp0_reg;
1378 +typedef struct {
1379 + u32 val;
1380 +} sdc_resp1_reg;
1381 +typedef struct {
1382 + u32 val;
1383 +} sdc_resp2_reg;
1384 +typedef struct {
1385 + u32 val;
1386 +} sdc_resp3_reg;
1387 +typedef struct {
1388 + u32 num;
1389 +} sdc_blknum_reg;
1390 +typedef struct {
1391 + u32 sts;
1392 +} sdc_csts_reg;
1393 +typedef struct {
1394 + u32 sts;
1395 +} sdc_cstsen_reg;
1396 +typedef struct {
1397 + u32 datcrcsts:8;
1398 + u32 ddrcrcsts:4;
1399 + u32 pad:20;
1400 +} sdc_datcrcsts_reg;
1401 +typedef struct {
1402 + u32 bootstart:1;
1403 + u32 bootstop:1;
1404 + u32 bootmode:1;
1405 + u32 pad1:9;
1406 + u32 bootwaidly:3;
1407 + u32 bootsupp:1;
1408 + u32 pad2:16;
1409 +} emmc_cfg0_reg;
1410 +typedef struct {
1411 + u32 bootcrctmc:16;
1412 + u32 pad:4;
1413 + u32 bootacktmc:12;
1414 +} emmc_cfg1_reg;
1415 +typedef struct {
1416 + u32 bootcrcerr:1;
1417 + u32 bootackerr:1;
1418 + u32 bootdattmo:1;
1419 + u32 bootacktmo:1;
1420 + u32 bootupstate:1;
1421 + u32 bootackrcv:1;
1422 + u32 bootdatrcv:1;
1423 + u32 pad:25;
1424 +} emmc_sts_reg;
1425 +typedef struct {
1426 + u32 bootrst:1;
1427 + u32 pad:31;
1428 +} emmc_iocon_reg;
1429 +typedef struct {
1430 + u32 val;
1431 +} msdc_acmd_resp_reg;
1432 +typedef struct {
1433 + u32 tunesel:4;
1434 + u32 pad:28;
1435 +} msdc_acmd19_trg_reg;
1436 +typedef struct {
1437 + u32 val;
1438 +} msdc_acmd19_sts_reg;
1439 +typedef struct {
1440 + u32 addr;
1441 +} msdc_dma_sa_reg;
1442 +typedef struct {
1443 + u32 addr;
1444 +} msdc_dma_ca_reg;
1445 +typedef struct {
1446 + u32 start:1;
1447 + u32 stop:1;
1448 + u32 resume:1;
1449 + u32 pad1:5;
1450 + u32 mode:1;
1451 + u32 pad2:1;
1452 + u32 lastbuf:1;
1453 + u32 pad3:1;
1454 + u32 brustsz:3;
1455 + u32 pad4:1;
1456 + u32 xfersz:16;
1457 +} msdc_dma_ctrl_reg;
1458 +typedef struct {
1459 + u32 status:1;
1460 + u32 decsen:1;
1461 + u32 pad1:2;
1462 + u32 bdcsen:1;
1463 + u32 gpdcsen:1;
1464 + u32 pad2:26;
1465 +} msdc_dma_cfg_reg;
1466 +typedef struct {
1467 + u32 sel:16;
1468 + u32 pad2:16;
1469 +} msdc_dbg_sel_reg;
1470 +typedef struct {
1471 + u32 val;
1472 +} msdc_dbg_out_reg;
1473 +typedef struct {
1474 + u32 clkdrvn:3;
1475 + u32 rsv0:1;
1476 + u32 clkdrvp:3;
1477 + u32 rsv1:1;
1478 + u32 clksr:1;
1479 + u32 rsv2:7;
1480 + u32 clkpd:1;
1481 + u32 clkpu:1;
1482 + u32 clksmt:1;
1483 + u32 clkies:1;
1484 + u32 clktdsel:4;
1485 + u32 clkrdsel:8;
1486 +} msdc_pad_ctl0_reg;
1487 +typedef struct {
1488 + u32 cmddrvn:3;
1489 + u32 rsv0:1;
1490 + u32 cmddrvp:3;
1491 + u32 rsv1:1;
1492 + u32 cmdsr:1;
1493 + u32 rsv2:7;
1494 + u32 cmdpd:1;
1495 + u32 cmdpu:1;
1496 + u32 cmdsmt:1;
1497 + u32 cmdies:1;
1498 + u32 cmdtdsel:4;
1499 + u32 cmdrdsel:8;
1500 +} msdc_pad_ctl1_reg;
1501 +typedef struct {
1502 + u32 datdrvn:3;
1503 + u32 rsv0:1;
1504 + u32 datdrvp:3;
1505 + u32 rsv1:1;
1506 + u32 datsr:1;
1507 + u32 rsv2:7;
1508 + u32 datpd:1;
1509 + u32 datpu:1;
1510 + u32 datsmt:1;
1511 + u32 daties:1;
1512 + u32 dattdsel:4;
1513 + u32 datrdsel:8;
1514 +} msdc_pad_ctl2_reg;
1515 +typedef struct {
1516 + u32 wrrxdly:3;
1517 + u32 pad1:5;
1518 + u32 rdrxdly:8;
1519 + u32 pad2:16;
1520 +} msdc_pad_tune_reg;
1521 +typedef struct {
1522 + u32 dat0:5;
1523 + u32 rsv0:3;
1524 + u32 dat1:5;
1525 + u32 rsv1:3;
1526 + u32 dat2:5;
1527 + u32 rsv2:3;
1528 + u32 dat3:5;
1529 + u32 rsv3:3;
1530 +} msdc_dat_rddly0;
1531 +typedef struct {
1532 + u32 dat4:5;
1533 + u32 rsv4:3;
1534 + u32 dat5:5;
1535 + u32 rsv5:3;
1536 + u32 dat6:5;
1537 + u32 rsv6:3;
1538 + u32 dat7:5;
1539 + u32 rsv7:3;
1540 +} msdc_dat_rddly1;
1541 +typedef struct {
1542 + u32 dbg0sel:8;
1543 + u32 dbg1sel:6;
1544 + u32 pad1:2;
1545 + u32 dbg2sel:6;
1546 + u32 pad2:2;
1547 + u32 dbg3sel:6;
1548 + u32 pad3:2;
1549 +} msdc_hw_dbg_reg;
1550 +typedef struct {
1551 + u32 val;
1552 +} msdc_version_reg;
1553 +typedef struct {
1554 + u32 val;
1555 +} msdc_eco_ver_reg;
1556 +
1557 +struct msdc_regs {
1558 + msdc_cfg_reg msdc_cfg; /* base+0x00h */
1559 + msdc_iocon_reg msdc_iocon; /* base+0x04h */
1560 + msdc_ps_reg msdc_ps; /* base+0x08h */
1561 + msdc_int_reg msdc_int; /* base+0x0ch */
1562 + msdc_inten_reg msdc_inten; /* base+0x10h */
1563 + msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
1564 + msdc_txdat_reg msdc_txdat; /* base+0x18h */
1565 + msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
1566 + u32 rsv1[4];
1567 + sdc_cfg_reg sdc_cfg; /* base+0x30h */
1568 + sdc_cmd_reg sdc_cmd; /* base+0x34h */
1569 + sdc_arg_reg sdc_arg; /* base+0x38h */
1570 + sdc_sts_reg sdc_sts; /* base+0x3ch */
1571 + sdc_resp0_reg sdc_resp0; /* base+0x40h */
1572 + sdc_resp1_reg sdc_resp1; /* base+0x44h */
1573 + sdc_resp2_reg sdc_resp2; /* base+0x48h */
1574 + sdc_resp3_reg sdc_resp3; /* base+0x4ch */
1575 + sdc_blknum_reg sdc_blknum; /* base+0x50h */
1576 + u32 rsv2[1];
1577 + sdc_csts_reg sdc_csts; /* base+0x58h */
1578 + sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
1579 + sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
1580 + u32 rsv3[3];
1581 + emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
1582 + emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
1583 + emmc_sts_reg emmc_sts; /* base+0x78h */
1584 + emmc_iocon_reg emmc_iocon; /* base+0x7ch */
1585 + msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
1586 + msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
1587 + msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
1588 + u32 rsv4[1];
1589 + msdc_dma_sa_reg dma_sa; /* base+0x90h */
1590 + msdc_dma_ca_reg dma_ca; /* base+0x94h */
1591 + msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
1592 + msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
1593 + msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
1594 + msdc_dbg_out_reg dbg_out; /* base+0xa4h */
1595 + u32 rsv5[2];
1596 + u32 patch0; /* base+0xb0h */
1597 + u32 patch1; /* base+0xb4h */
1598 + u32 rsv6[10];
1599 + msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
1600 + msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
1601 + msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
1602 + msdc_pad_tune_reg pad_tune; /* base+0xech */
1603 + msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
1604 + msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
1605 + msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
1606 + u32 rsv7[1];
1607 + msdc_version_reg version; /* base+0x100h */
1608 + msdc_eco_ver_reg eco_ver; /* base+0x104h */
1609 +};
1610 +
1611 +struct scatterlist_ex {
1612 + u32 cmd;
1613 + u32 arg;
1614 + u32 sglen;
1615 + struct scatterlist *sg;
1616 +};
1617 +
1618 +#define DMA_FLAG_NONE (0x00000000)
1619 +#define DMA_FLAG_EN_CHKSUM (0x00000001)
1620 +#define DMA_FLAG_PAD_BLOCK (0x00000002)
1621 +#define DMA_FLAG_PAD_DWORD (0x00000004)
1622 +
1623 +struct msdc_dma {
1624 + u32 flags; /* flags */
1625 + u32 xfersz; /* xfer size in bytes */
1626 + u32 sglen; /* size of scatter list */
1627 + u32 blklen; /* block size */
1628 + struct scatterlist *sg; /* I/O scatter list */
1629 + struct scatterlist_ex *esg; /* extended I/O scatter list */
1630 + u8 mode; /* dma mode */
1631 + u8 burstsz; /* burst size */
1632 + u8 intr; /* dma done interrupt */
1633 + u8 padding; /* padding */
1634 + u32 cmd; /* enhanced mode command */
1635 + u32 arg; /* enhanced mode arg */
1636 + u32 rsp; /* enhanced mode command response */
1637 + u32 autorsp; /* auto command response */
1638 +
1639 + gpd_t *gpd; /* pointer to gpd array */
1640 + bd_t *bd; /* pointer to bd array */
1641 + dma_addr_t gpd_addr; /* the physical address of gpd array */
1642 + dma_addr_t bd_addr; /* the physical address of bd array */
1643 + u32 used_gpd; /* the number of used gpd elements */
1644 + u32 used_bd; /* the number of used bd elements */
1645 +};
1646 +
1647 +struct msdc_host
1648 +{
1649 + struct msdc_hw *hw;
1650 +
1651 + struct mmc_host *mmc; /* mmc structure */
1652 + struct mmc_command *cmd;
1653 + struct mmc_data *data;
1654 + struct mmc_request *mrq;
1655 + int cmd_rsp;
1656 + int cmd_rsp_done;
1657 + int cmd_r1b_done;
1658 +
1659 + int error;
1660 + spinlock_t lock; /* mutex */
1661 + struct semaphore sem;
1662 +
1663 + u32 blksz; /* host block size */
1664 + u32 base; /* host base address */
1665 + int id; /* host id */
1666 + int pwr_ref; /* core power reference count */
1667 +
1668 + u32 xfer_size; /* total transferred size */
1669 +
1670 + struct msdc_dma dma; /* dma channel */
1671 + u32 dma_addr; /* dma transfer address */
1672 + u32 dma_left_size; /* dma transfer left size */
1673 + u32 dma_xfer_size; /* dma transfer size in bytes */
1674 + int dma_xfer; /* dma transfer mode */
1675 +
1676 + u32 timeout_ns; /* data timeout ns */
1677 + u32 timeout_clks; /* data timeout clks */
1678 +
1679 + atomic_t abort; /* abort transfer */
1680 +
1681 + int irq; /* host interrupt */
1682 +
1683 + struct tasklet_struct card_tasklet;
1684 +#if 0
1685 + struct work_struct card_workqueue;
1686 +#else
1687 + struct delayed_work card_delaywork;
1688 +#endif
1689 +
1690 + struct completion cmd_done;
1691 + struct completion xfer_done;
1692 + struct pm_message pm_state;
1693 +
1694 + u32 mclk; /* mmc subsystem clock */
1695 + u32 hclk; /* host clock speed */
1696 + u32 sclk; /* SD/MS clock speed */
1697 + u8 core_clkon; /* Host core clock on ? */
1698 + u8 card_clkon; /* Card clock on ? */
1699 + u8 core_power; /* core power */
1700 + u8 power_mode; /* host power mode */
1701 + u8 card_inserted; /* card inserted ? */
1702 + u8 suspend; /* host suspended ? */
1703 + u8 reserved;
1704 + u8 app_cmd; /* for app command */
1705 + u32 app_cmd_arg;
1706 + u64 starttime;
1707 +};
1708 +
1709 +static inline unsigned int uffs(unsigned int x)
1710 +{
1711 + unsigned int r = 1;
1712 +
1713 + if (!x)
1714 + return 0;
1715 + if (!(x & 0xffff)) {
1716 + x >>= 16;
1717 + r += 16;
1718 + }
1719 + if (!(x & 0xff)) {
1720 + x >>= 8;
1721 + r += 8;
1722 + }
1723 + if (!(x & 0xf)) {
1724 + x >>= 4;
1725 + r += 4;
1726 + }
1727 + if (!(x & 3)) {
1728 + x >>= 2;
1729 + r += 2;
1730 + }
1731 + if (!(x & 1)) {
1732 + x >>= 1;
1733 + r += 1;
1734 + }
1735 + return r;
1736 +}
1737 +#define sdr_read8(reg) __raw_readb(reg)
1738 +#define sdr_read16(reg) __raw_readw(reg)
1739 +#define sdr_read32(reg) __raw_readl(reg)
1740 +#define sdr_write8(reg,val) __raw_writeb(val,reg)
1741 +#define sdr_write16(reg,val) __raw_writew(val,reg)
1742 +#define sdr_write32(reg,val) __raw_writel(val,reg)
1743 +
1744 +#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
1745 +#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
1746 +
1747 +#define sdr_set_field(reg,field,val) \
1748 + do { \
1749 + volatile unsigned int tv = sdr_read32(reg); \
1750 + tv &= ~(field); \
1751 + tv |= ((val) << (uffs((unsigned int)field) - 1)); \
1752 + sdr_write32(reg,tv); \
1753 + } while(0)
1754 +#define sdr_get_field(reg,field,val) \
1755 + do { \
1756 + volatile unsigned int tv = sdr_read32(reg); \
1757 + val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
1758 + } while(0)
1759 +
1760 +#endif
1761 +
1762 --- /dev/null
1763 +++ b/drivers/mmc/host/mtk-mmc/sd.c
1764 @@ -0,0 +1,3066 @@
1765 +/* Copyright Statement:
1766 + *
1767 + * This software/firmware and related documentation ("MediaTek Software") are
1768 + * protected under relevant copyright laws. The information contained herein
1769 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
1770 + * Without the prior written permission of MediaTek inc. and/or its licensors,
1771 + * any reproduction, modification, use or disclosure of MediaTek Software,
1772 + * and information contained herein, in whole or in part, shall be strictly prohibited.
1773 + *
1774 + * MediaTek Inc. (C) 2010. All rights reserved.
1775 + *
1776 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1777 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1778 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
1779 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1780 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1781 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1782 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1783 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1784 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
1785 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
1786 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
1787 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
1788 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
1789 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
1790 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1791 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1792 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
1793 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1794 + *
1795 + * The following software/firmware and/or related documentation ("MediaTek Software")
1796 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
1797 + * applicable license agreements with MediaTek Inc.
1798 + */
1799 +
1800 +#include <linux/module.h>
1801 +#include <linux/moduleparam.h>
1802 +#include <linux/init.h>
1803 +#include <linux/spinlock.h>
1804 +#include <linux/timer.h>
1805 +#include <linux/ioport.h>
1806 +#include <linux/device.h>
1807 +#include <linux/platform_device.h>
1808 +#include <linux/interrupt.h>
1809 +#include <linux/delay.h>
1810 +#include <linux/blkdev.h>
1811 +#include <linux/slab.h>
1812 +#include <linux/mmc/host.h>
1813 +#include <linux/mmc/card.h>
1814 +#include <linux/mmc/core.h>
1815 +#include <linux/mmc/mmc.h>
1816 +#include <linux/mmc/sd.h>
1817 +#include <linux/mmc/sdio.h>
1818 +#include <linux/dma-mapping.h>
1819 +
1820 +/* +++ by chhung */
1821 +#include <linux/types.h>
1822 +#include <linux/kernel.h>
1823 +#include <linux/version.h>
1824 +#include <linux/pm.h>
1825 +#include <linux/of.h>
1826 +
1827 +#define MSDC_SMPL_FALLING (1)
1828 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
1829 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
1830 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
1831 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
1832 +#define MSDC_HIGHSPEED (1 << 7)
1833 +
1834 +//#define IRQ_SDC 14 //MT7620 /*FIXME*/
1835 +#ifdef CONFIG_SOC_MT7621
1836 +#define RALINK_SYSCTL_BASE 0xbe000000
1837 +#define RALINK_MSDC_BASE 0xbe130000
1838 +#else
1839 +#define RALINK_SYSCTL_BASE 0xb0000000
1840 +#define RALINK_MSDC_BASE 0xb0130000
1841 +#endif
1842 +#define IRQ_SDC 22 /*FIXME*/
1843 +
1844 +#include <asm/dma.h>
1845 +/* end of +++ */
1846 +
1847 +
1848 +#include <asm/mach-ralink/ralink_regs.h>
1849 +
1850 +#if 0 /* --- by chhung */
1851 +#include <mach/board.h>
1852 +#include <mach/mt6575_devs.h>
1853 +#include <mach/mt6575_typedefs.h>
1854 +#include <mach/mt6575_clock_manager.h>
1855 +#include <mach/mt6575_pm_ldo.h>
1856 +//#include <mach/mt6575_pll.h>
1857 +//#include <mach/mt6575_gpio.h>
1858 +//#include <mach/mt6575_gpt_sw.h>
1859 +#include <asm/tcm.h>
1860 +// #include <mach/mt6575_gpt.h>
1861 +#endif /* end of --- */
1862 +
1863 +#include "mt6575_sd.h"
1864 +#include "dbg.h"
1865 +
1866 +/* +++ by chhung */
1867 +#include "board.h"
1868 +/* end of +++ */
1869 +
1870 +#if 0 /* --- by chhung */
1871 +#define isb() __asm__ __volatile__ ("" : : : "memory")
1872 +#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
1873 + : : "r" (0) : "memory")
1874 +#define dmb() __asm__ __volatile__ ("" : : : "memory")
1875 +#endif /* end of --- */
1876 +
1877 +#define DRV_NAME "mtk-sd"
1878 +
1879 +#define HOST_MAX_NUM (1) /* +/- by chhung */
1880 +
1881 +#if defined (CONFIG_SOC_MT7620)
1882 +#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
1883 +#elif defined (CONFIG_SOC_MT7621)
1884 +#define HOST_MAX_MCLK (50000000) /* +/- by chhung */
1885 +#endif
1886 +#define HOST_MIN_MCLK (260000)
1887 +
1888 +#define HOST_MAX_BLKSZ (2048)
1889 +
1890 +#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
1891 +
1892 +#define GPIO_PULL_DOWN (0)
1893 +#define GPIO_PULL_UP (1)
1894 +
1895 +#if 0 /* --- by chhung */
1896 +#define MSDC_CLKSRC_REG (0xf100000C)
1897 +#define PDN_REG (0xF1000010)
1898 +#endif /* end of --- */
1899 +
1900 +#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
1901 +#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
1902 +
1903 +#define CMD_TIMEOUT (HZ/10) /* 100ms */
1904 +#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
1905 +
1906 +#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
1907 +
1908 +#define MAX_GPD_NUM (1 + 1) /* one null gpd */
1909 +#define MAX_BD_NUM (1024)
1910 +#define MAX_BD_PER_GPD (MAX_BD_NUM)
1911 +
1912 +#define MAX_HW_SGMTS (MAX_BD_NUM)
1913 +#define MAX_PHY_SGMTS (MAX_BD_NUM)
1914 +#define MAX_SGMT_SZ (MAX_DMA_CNT)
1915 +#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
1916 +
1917 +#ifdef MT6575_SD_DEBUG
1918 +static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
1919 +#endif
1920 +
1921 +static int mtk_sw_poll;
1922 +
1923 +static int cd_active_low = 1;
1924 +
1925 +//=================================
1926 +#define PERI_MSDC0_PDN (15)
1927 +//#define PERI_MSDC1_PDN (16)
1928 +//#define PERI_MSDC2_PDN (17)
1929 +//#define PERI_MSDC3_PDN (18)
1930 +
1931 +struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
1932 +#if 0 /* --- by chhung */
1933 +/* gate means clock power down */
1934 +static int g_clk_gate = 0;
1935 +#define msdc_gate_clock(id) \
1936 + do { \
1937 + g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
1938 + } while(0)
1939 +/* not like power down register. 1 means clock on. */
1940 +#define msdc_ungate_clock(id) \
1941 + do { \
1942 + g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
1943 + } while(0)
1944 +
1945 +// do we need sync object or not
1946 +void msdc_clk_status(int * status)
1947 +{
1948 + *status = g_clk_gate;
1949 +}
1950 +#endif /* end of --- */
1951 +
1952 +/* +++ by chhung */
1953 +struct msdc_hw msdc0_hw = {
1954 + .clk_src = 0,
1955 + .cmd_edge = MSDC_SMPL_FALLING,
1956 + .data_edge = MSDC_SMPL_FALLING,
1957 + .clk_drv = 4,
1958 + .cmd_drv = 4,
1959 + .dat_drv = 4,
1960 + .data_pins = 4,
1961 + .data_offset = 0,
1962 + .flags = MSDC_SYS_SUSPEND | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
1963 +// .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
1964 +};
1965 +
1966 +static struct resource mtk_sd_resources[] = {
1967 + [0] = {
1968 + .start = RALINK_MSDC_BASE,
1969 + .end = RALINK_MSDC_BASE+0x3fff,
1970 + .flags = IORESOURCE_MEM,
1971 + },
1972 + [1] = {
1973 + .start = IRQ_SDC, /*FIXME*/
1974 + .end = IRQ_SDC, /*FIXME*/
1975 + .flags = IORESOURCE_IRQ,
1976 + },
1977 +};
1978 +
1979 +static struct platform_device mtk_sd_device = {
1980 + .name = "mtk-sd",
1981 + .id = 0,
1982 + .num_resources = ARRAY_SIZE(mtk_sd_resources),
1983 + .resource = mtk_sd_resources,
1984 +};
1985 +/* end of +++ */
1986 +
1987 +static int msdc_rsp[] = {
1988 + 0, /* RESP_NONE */
1989 + 1, /* RESP_R1 */
1990 + 2, /* RESP_R2 */
1991 + 3, /* RESP_R3 */
1992 + 4, /* RESP_R4 */
1993 + 1, /* RESP_R5 */
1994 + 1, /* RESP_R6 */
1995 + 1, /* RESP_R7 */
1996 + 7, /* RESP_R1b */
1997 +};
1998 +
1999 +/* For Inhanced DMA */
2000 +#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
2001 + do { \
2002 + ((gpd_t*)gpd)->extlen = extlen; \
2003 + ((gpd_t*)gpd)->cmd = cmd; \
2004 + ((gpd_t*)gpd)->arg = arg; \
2005 + ((gpd_t*)gpd)->blknum = blknum; \
2006 + }while(0)
2007 +
2008 +#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
2009 + do { \
2010 + BUG_ON(dlen > 0xFFFFUL); \
2011 + ((bd_t*)bd)->blkpad = blkpad; \
2012 + ((bd_t*)bd)->dwpad = dwpad; \
2013 + ((bd_t*)bd)->ptr = (void*)dptr; \
2014 + ((bd_t*)bd)->buflen = dlen; \
2015 + }while(0)
2016 +
2017 +#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
2018 +#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
2019 +#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
2020 +#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
2021 +#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
2022 +#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
2023 +
2024 +
2025 +#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
2026 +#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
2027 +
2028 +#define msdc_retry(expr,retry,cnt) \
2029 + do { \
2030 + int backup = cnt; \
2031 + while (retry) { \
2032 + if (!(expr)) break; \
2033 + if (cnt-- == 0) { \
2034 + retry--; mdelay(1); cnt = backup; \
2035 + } \
2036 + } \
2037 + WARN_ON(retry == 0); \
2038 + } while(0)
2039 +
2040 +#if 0 /* --- by chhung */
2041 +#define msdc_reset() \
2042 + do { \
2043 + int retry = 3, cnt = 1000; \
2044 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2045 + dsb(); \
2046 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2047 + } while(0)
2048 +#else
2049 +#define msdc_reset() \
2050 + do { \
2051 + int retry = 3, cnt = 1000; \
2052 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2053 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2054 + } while(0)
2055 +#endif /* end of +/- */
2056 +
2057 +#define msdc_clr_int() \
2058 + do { \
2059 + volatile u32 val = sdr_read32(MSDC_INT); \
2060 + sdr_write32(MSDC_INT, val); \
2061 + } while(0)
2062 +
2063 +#define msdc_clr_fifo() \
2064 + do { \
2065 + int retry = 3, cnt = 1000; \
2066 + sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
2067 + msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
2068 + } while(0)
2069 +
2070 +#define msdc_irq_save(val) \
2071 + do { \
2072 + val = sdr_read32(MSDC_INTEN); \
2073 + sdr_clr_bits(MSDC_INTEN, val); \
2074 + } while(0)
2075 +
2076 +#define msdc_irq_restore(val) \
2077 + do { \
2078 + sdr_set_bits(MSDC_INTEN, val); \
2079 + } while(0)
2080 +
2081 +/* clock source for host: global */
2082 +#if defined (CONFIG_SOC_MT7620)
2083 +static u32 hclks[] = {48000000}; /* +/- by chhung */
2084 +#elif defined (CONFIG_SOC_MT7621)
2085 +static u32 hclks[] = {50000000}; /* +/- by chhung */
2086 +#endif
2087 +
2088 +//============================================
2089 +// the power for msdc host controller: global
2090 +// always keep the VMC on.
2091 +//============================================
2092 +#define msdc_vcore_on(host) \
2093 + do { \
2094 + INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
2095 + (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
2096 + } while (0)
2097 +#define msdc_vcore_off(host) \
2098 + do { \
2099 + INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
2100 + (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
2101 + } while (0)
2102 +
2103 +//====================================
2104 +// the vdd output for card: global
2105 +// always keep the VMCH on.
2106 +//====================================
2107 +#define msdc_vdd_on(host) \
2108 + do { \
2109 + (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
2110 + } while (0)
2111 +#define msdc_vdd_off(host) \
2112 + do { \
2113 + (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
2114 + } while (0)
2115 +
2116 +#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
2117 +#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
2118 +
2119 +#define sdc_send_cmd(cmd,arg) \
2120 + do { \
2121 + sdr_write32(SDC_ARG, (arg)); \
2122 + sdr_write32(SDC_CMD, (cmd)); \
2123 + } while(0)
2124 +
2125 +// can modify to read h/w register.
2126 +//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
2127 +#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
2128 +
2129 +/* +++ by chhung */
2130 +#ifndef __ASSEMBLY__
2131 +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
2132 +#else
2133 +#define PHYSADDR(a) ((a) & 0x1fffffff)
2134 +#endif
2135 +/* end of +++ */
2136 +static unsigned int msdc_do_command(struct msdc_host *host,
2137 + struct mmc_command *cmd,
2138 + int tune,
2139 + unsigned long timeout);
2140 +
2141 +static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
2142 +
2143 +#ifdef MT6575_SD_DEBUG
2144 +static void msdc_dump_card_status(struct msdc_host *host, u32 status)
2145 +{
2146 + static char *state[] = {
2147 + "Idle", /* 0 */
2148 + "Ready", /* 1 */
2149 + "Ident", /* 2 */
2150 + "Stby", /* 3 */
2151 + "Tran", /* 4 */
2152 + "Data", /* 5 */
2153 + "Rcv", /* 6 */
2154 + "Prg", /* 7 */
2155 + "Dis", /* 8 */
2156 + "Reserved", /* 9 */
2157 + "Reserved", /* 10 */
2158 + "Reserved", /* 11 */
2159 + "Reserved", /* 12 */
2160 + "Reserved", /* 13 */
2161 + "Reserved", /* 14 */
2162 + "I/O mode", /* 15 */
2163 + };
2164 + if (status & R1_OUT_OF_RANGE)
2165 + N_MSG(RSP, "[CARD_STATUS] Out of Range");
2166 + if (status & R1_ADDRESS_ERROR)
2167 + N_MSG(RSP, "[CARD_STATUS] Address Error");
2168 + if (status & R1_BLOCK_LEN_ERROR)
2169 + N_MSG(RSP, "[CARD_STATUS] Block Len Error");
2170 + if (status & R1_ERASE_SEQ_ERROR)
2171 + N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
2172 + if (status & R1_ERASE_PARAM)
2173 + N_MSG(RSP, "[CARD_STATUS] Erase Param");
2174 + if (status & R1_WP_VIOLATION)
2175 + N_MSG(RSP, "[CARD_STATUS] WP Violation");
2176 + if (status & R1_CARD_IS_LOCKED)
2177 + N_MSG(RSP, "[CARD_STATUS] Card is Locked");
2178 + if (status & R1_LOCK_UNLOCK_FAILED)
2179 + N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
2180 + if (status & R1_COM_CRC_ERROR)
2181 + N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
2182 + if (status & R1_ILLEGAL_COMMAND)
2183 + N_MSG(RSP, "[CARD_STATUS] Illegal Command");
2184 + if (status & R1_CARD_ECC_FAILED)
2185 + N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
2186 + if (status & R1_CC_ERROR)
2187 + N_MSG(RSP, "[CARD_STATUS] CC Error");
2188 + if (status & R1_ERROR)
2189 + N_MSG(RSP, "[CARD_STATUS] Error");
2190 + if (status & R1_UNDERRUN)
2191 + N_MSG(RSP, "[CARD_STATUS] Underrun");
2192 + if (status & R1_OVERRUN)
2193 + N_MSG(RSP, "[CARD_STATUS] Overrun");
2194 + if (status & R1_CID_CSD_OVERWRITE)
2195 + N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
2196 + if (status & R1_WP_ERASE_SKIP)
2197 + N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
2198 + if (status & R1_CARD_ECC_DISABLED)
2199 + N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
2200 + if (status & R1_ERASE_RESET)
2201 + N_MSG(RSP, "[CARD_STATUS] Erase Reset");
2202 + if (status & R1_READY_FOR_DATA)
2203 + N_MSG(RSP, "[CARD_STATUS] Ready for Data");
2204 + if (status & R1_SWITCH_ERROR)
2205 + N_MSG(RSP, "[CARD_STATUS] Switch error");
2206 + if (status & R1_APP_CMD)
2207 + N_MSG(RSP, "[CARD_STATUS] App Command");
2208 +
2209 + N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
2210 +}
2211 +
2212 +static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
2213 +{
2214 + if (resp & (1 << 7))
2215 + N_MSG(RSP, "[OCR] Low Voltage Range");
2216 + if (resp & (1 << 15))
2217 + N_MSG(RSP, "[OCR] 2.7-2.8 volt");
2218 + if (resp & (1 << 16))
2219 + N_MSG(RSP, "[OCR] 2.8-2.9 volt");
2220 + if (resp & (1 << 17))
2221 + N_MSG(RSP, "[OCR] 2.9-3.0 volt");
2222 + if (resp & (1 << 18))
2223 + N_MSG(RSP, "[OCR] 3.0-3.1 volt");
2224 + if (resp & (1 << 19))
2225 + N_MSG(RSP, "[OCR] 3.1-3.2 volt");
2226 + if (resp & (1 << 20))
2227 + N_MSG(RSP, "[OCR] 3.2-3.3 volt");
2228 + if (resp & (1 << 21))
2229 + N_MSG(RSP, "[OCR] 3.3-3.4 volt");
2230 + if (resp & (1 << 22))
2231 + N_MSG(RSP, "[OCR] 3.4-3.5 volt");
2232 + if (resp & (1 << 23))
2233 + N_MSG(RSP, "[OCR] 3.5-3.6 volt");
2234 + if (resp & (1 << 24))
2235 + N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
2236 + if (resp & (1 << 30))
2237 + N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
2238 + if (resp & (1 << 31))
2239 + N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
2240 + else
2241 + N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
2242 +}
2243 +
2244 +static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
2245 +{
2246 + u32 status = (((resp >> 15) & 0x1) << 23) |
2247 + (((resp >> 14) & 0x1) << 22) |
2248 + (((resp >> 13) & 0x1) << 19) |
2249 + (resp & 0x1fff);
2250 +
2251 + N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
2252 + msdc_dump_card_status(host, status);
2253 +}
2254 +
2255 +static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
2256 +{
2257 + u32 flags = (resp >> 8) & 0xFF;
2258 + char *state[] = {"DIS", "CMD", "TRN", "RFU"};
2259 +
2260 + if (flags & (1 << 7))
2261 + N_MSG(RSP, "[IO] COM_CRC_ERR");
2262 + if (flags & (1 << 6))
2263 + N_MSG(RSP, "[IO] Illgal command");
2264 + if (flags & (1 << 3))
2265 + N_MSG(RSP, "[IO] Error");
2266 + if (flags & (1 << 2))
2267 + N_MSG(RSP, "[IO] RFU");
2268 + if (flags & (1 << 1))
2269 + N_MSG(RSP, "[IO] Function number error");
2270 + if (flags & (1 << 0))
2271 + N_MSG(RSP, "[IO] Out of range");
2272 +
2273 + N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
2274 +}
2275 +#endif
2276 +
2277 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
2278 +{
2279 + u32 base = host->base;
2280 + u32 timeout, clk_ns;
2281 +
2282 + host->timeout_ns = ns;
2283 + host->timeout_clks = clks;
2284 +
2285 + clk_ns = 1000000000UL / host->sclk;
2286 + timeout = ns / clk_ns + clks;
2287 + timeout = timeout >> 16; /* in 65536 sclk cycle unit */
2288 + timeout = timeout > 1 ? timeout - 1 : 0;
2289 + timeout = timeout > 255 ? 255 : timeout;
2290 +
2291 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
2292 +
2293 + N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
2294 + ns, clks, timeout + 1);
2295 +}
2296 +
2297 +/* msdc_eirq_sdio() will be called when EIRQ(for WIFI) */
2298 +static void msdc_eirq_sdio(void *data)
2299 +{
2300 + struct msdc_host *host = (struct msdc_host *)data;
2301 +
2302 + N_MSG(INT, "SDIO EINT");
2303 +
2304 + mmc_signal_sdio_irq(host->mmc);
2305 +}
2306 +
2307 +/* msdc_eirq_cd will not be used! We not using EINT for card detection. */
2308 +static void msdc_eirq_cd(void *data)
2309 +{
2310 + struct msdc_host *host = (struct msdc_host *)data;
2311 +
2312 + N_MSG(INT, "CD EINT");
2313 +
2314 +#if 0
2315 + tasklet_hi_schedule(&host->card_tasklet);
2316 +#else
2317 + schedule_delayed_work(&host->card_delaywork, HZ);
2318 +#endif
2319 +}
2320 +
2321 +#if 0
2322 +static void msdc_tasklet_card(unsigned long arg)
2323 +{
2324 + struct msdc_host *host = (struct msdc_host *)arg;
2325 +#else
2326 +static void msdc_tasklet_card(struct work_struct *work)
2327 +{
2328 + struct msdc_host *host = (struct msdc_host *)container_of(work,
2329 + struct msdc_host, card_delaywork.work);
2330 +#endif
2331 + struct msdc_hw *hw = host->hw;
2332 + u32 base = host->base;
2333 + u32 inserted;
2334 + u32 status = 0;
2335 + //u32 change = 0;
2336 +
2337 + spin_lock(&host->lock);
2338 +
2339 + if (hw->get_cd_status) { // NULL
2340 + inserted = hw->get_cd_status();
2341 + } else {
2342 + status = sdr_read32(MSDC_PS);
2343 + if (cd_active_low)
2344 + inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
2345 + else
2346 + inserted = (status & MSDC_PS_CDSTS) ? 1 : 0;
2347 + }
2348 + if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
2349 + inserted = 1;
2350 +
2351 +#if 0
2352 + change = host->card_inserted ^ inserted;
2353 + host->card_inserted = inserted;
2354 +
2355 + if (change && !host->suspend) {
2356 + if (inserted) {
2357 + host->mmc->f_max = HOST_MAX_MCLK; // work around
2358 + }
2359 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2360 + }
2361 +#else /* Make sure: handle the last interrupt */
2362 + host->card_inserted = inserted;
2363 +
2364 + if (!host->suspend) {
2365 + host->mmc->f_max = HOST_MAX_MCLK;
2366 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2367 + }
2368 +
2369 + IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
2370 +#endif
2371 +
2372 + spin_unlock(&host->lock);
2373 +}
2374 +
2375 +#if 0 /* --- by chhung */
2376 +/* For E2 only */
2377 +static u8 clk_src_bit[4] = {
2378 + 0, 3, 5, 7
2379 +};
2380 +
2381 +static void msdc_select_clksrc(struct msdc_host* host, unsigned char clksrc)
2382 +{
2383 + u32 val;
2384 + u32 base = host->base;
2385 +
2386 + BUG_ON(clksrc > 3);
2387 + INIT_MSG("set clock source to <%d>", clksrc);
2388 +
2389 + val = sdr_read32(MSDC_CLKSRC_REG);
2390 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2391 + val &= ~(0x3 << clk_src_bit[host->id]);
2392 + val |= clksrc << clk_src_bit[host->id];
2393 + } else {
2394 + val &= ~0x3; val |= clksrc;
2395 + }
2396 + sdr_write32(MSDC_CLKSRC_REG, val);
2397 +
2398 + host->hclk = hclks[clksrc];
2399 + host->hw->clk_src = clksrc;
2400 +}
2401 +#endif /* end of --- */
2402 +
2403 +static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
2404 +{
2405 + //struct msdc_hw *hw = host->hw;
2406 + u32 base = host->base;
2407 + u32 mode;
2408 + u32 flags;
2409 + u32 div;
2410 + u32 sclk;
2411 + u32 hclk = host->hclk;
2412 + //u8 clksrc = hw->clk_src;
2413 +
2414 + if (!hz) { // set mmc system clock to 0 ?
2415 + //ERR_MSG("set mclk to 0!!!");
2416 + msdc_reset();
2417 + return;
2418 + }
2419 +
2420 + msdc_irq_save(flags);
2421 +
2422 +#if defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7628_FPGA)
2423 + mode = 0x0; /* use divisor */
2424 + if (hz >= (hclk >> 1)) {
2425 + div = 0; /* mean div = 1/2 */
2426 + sclk = hclk >> 1; /* sclk = clk / 2 */
2427 + } else {
2428 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2429 + sclk = (hclk >> 2) / div;
2430 + }
2431 +#else
2432 + if (ddr) {
2433 + mode = 0x2; /* ddr mode and use divisor */
2434 + if (hz >= (hclk >> 2)) {
2435 + div = 1; /* mean div = 1/4 */
2436 + sclk = hclk >> 2; /* sclk = clk / 4 */
2437 + } else {
2438 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2439 + sclk = (hclk >> 2) / div;
2440 + }
2441 + } else if (hz >= hclk) { /* bug fix */
2442 + mode = 0x1; /* no divisor and divisor is ignored */
2443 + div = 0;
2444 + sclk = hclk;
2445 + } else {
2446 + mode = 0x0; /* use divisor */
2447 + if (hz >= (hclk >> 1)) {
2448 + div = 0; /* mean div = 1/2 */
2449 + sclk = hclk >> 1; /* sclk = clk / 2 */
2450 + } else {
2451 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2452 + sclk = (hclk >> 2) / div;
2453 + }
2454 + }
2455 +#endif
2456 + /* set clock mode and divisor */
2457 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
2458 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
2459 +
2460 + /* wait clock stable */
2461 + while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
2462 +
2463 + host->sclk = sclk;
2464 + host->mclk = hz;
2465 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
2466 +
2467 + INIT_MSG("================");
2468 + INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz/1000, hclk/1000, sclk/1000);
2469 + INIT_MSG("================");
2470 +
2471 + msdc_irq_restore(flags);
2472 +}
2473 +
2474 +/* Fix me. when need to abort */
2475 +static void msdc_abort_data(struct msdc_host *host)
2476 +{
2477 + u32 base = host->base;
2478 + struct mmc_command *stop = host->mrq->stop;
2479 +
2480 + ERR_MSG("Need to Abort. dma<%d>", host->dma_xfer);
2481 +
2482 + msdc_reset();
2483 + msdc_clr_fifo();
2484 + msdc_clr_int();
2485 +
2486 + // need to check FIFO count 0 ?
2487 +
2488 + if (stop) { /* try to stop, but may not success */
2489 + ERR_MSG("stop when abort CMD<%d>", stop->opcode);
2490 + (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
2491 + }
2492 +
2493 + //if (host->mclk >= 25000000) {
2494 + // msdc_set_mclk(host, 0, host->mclk >> 1);
2495 + //}
2496 +}
2497 +
2498 +#if 0 /* --- by chhung */
2499 +static void msdc_pin_config(struct msdc_host *host, int mode)
2500 +{
2501 + struct msdc_hw *hw = host->hw;
2502 + u32 base = host->base;
2503 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2504 +
2505 + /* Config WP pin */
2506 + if (hw->flags & MSDC_WP_PIN_EN) {
2507 + if (hw->config_gpio_pin) /* NULL */
2508 + hw->config_gpio_pin(MSDC_WP_PIN, pull);
2509 + }
2510 +
2511 + switch (mode) {
2512 + case MSDC_PIN_PULL_UP:
2513 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
2514 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2515 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
2516 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2517 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
2518 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2519 + break;
2520 + case MSDC_PIN_PULL_DOWN:
2521 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2522 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
2523 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2524 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
2525 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2526 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
2527 + break;
2528 + case MSDC_PIN_PULL_NONE:
2529 + default:
2530 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2531 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2532 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2533 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2534 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2535 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2536 + break;
2537 + }
2538 +
2539 + N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
2540 + mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
2541 +}
2542 +
2543 +void msdc_pin_reset(struct msdc_host *host, int mode)
2544 +{
2545 + struct msdc_hw *hw = (struct msdc_hw *)host->hw;
2546 + u32 base = host->base;
2547 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2548 +
2549 + /* Config reset pin */
2550 + if (hw->flags & MSDC_RST_PIN_EN) {
2551 + if (hw->config_gpio_pin) /* NULL */
2552 + hw->config_gpio_pin(MSDC_RST_PIN, pull);
2553 +
2554 + if (mode == MSDC_PIN_PULL_UP) {
2555 + sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2556 + } else {
2557 + sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2558 + }
2559 + }
2560 +}
2561 +
2562 +static void msdc_core_power(struct msdc_host *host, int on)
2563 +{
2564 + N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
2565 + on ? "on" : "off", "core", host->core_power, on);
2566 +
2567 + if (on && host->core_power == 0) {
2568 + msdc_vcore_on(host);
2569 + host->core_power = 1;
2570 + msleep(1);
2571 + } else if (!on && host->core_power == 1) {
2572 + msdc_vcore_off(host);
2573 + host->core_power = 0;
2574 + msleep(1);
2575 + }
2576 +}
2577 +
2578 +static void msdc_host_power(struct msdc_host *host, int on)
2579 +{
2580 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
2581 +
2582 + if (on) {
2583 + //msdc_core_power(host, 1); // need do card detection.
2584 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2585 + } else {
2586 + msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
2587 + //msdc_core_power(host, 0);
2588 + }
2589 +}
2590 +
2591 +static void msdc_card_power(struct msdc_host *host, int on)
2592 +{
2593 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
2594 +
2595 + if (on) {
2596 + msdc_pin_config(host, MSDC_PIN_PULL_UP);
2597 + if (host->hw->ext_power_on) {
2598 + host->hw->ext_power_on();
2599 + } else {
2600 + //msdc_vdd_on(host); // need todo card detection.
2601 + }
2602 + msleep(1);
2603 + } else {
2604 + if (host->hw->ext_power_off) {
2605 + host->hw->ext_power_off();
2606 + } else {
2607 + //msdc_vdd_off(host);
2608 + }
2609 + msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
2610 + msleep(1);
2611 + }
2612 +}
2613 +
2614 +static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
2615 +{
2616 + N_MSG(CFG, "Set power mode(%d)", mode);
2617 +
2618 + if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
2619 + msdc_host_power(host, 1);
2620 + msdc_card_power(host, 1);
2621 + } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
2622 + msdc_card_power(host, 0);
2623 + msdc_host_power(host, 0);
2624 + }
2625 + host->power_mode = mode;
2626 +}
2627 +#endif /* end of --- */
2628 +
2629 +#ifdef CONFIG_PM
2630 +/*
2631 + register as callback function of WIFI(combo_sdio_register_pm) .
2632 + can called by msdc_drv_suspend/resume too.
2633 +*/
2634 +static void msdc_pm(pm_message_t state, void *data)
2635 +{
2636 + struct msdc_host *host = (struct msdc_host *)data;
2637 + int evt = state.event;
2638 +
2639 + if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
2640 + INIT_MSG("USR_%s: suspend<%d> power<%d>",
2641 + evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
2642 + host->suspend, host->power_mode);
2643 + }
2644 +
2645 + if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
2646 + if (host->suspend) /* already suspend */ /* default 0*/
2647 + return;
2648 +
2649 + /* for memory card. already power off by mmc */
2650 + if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
2651 + return;
2652 +
2653 + host->suspend = 1;
2654 + host->pm_state = state; /* default PMSG_RESUME */
2655 +
2656 + INIT_MSG("%s Suspend", evt == PM_EVENT_SUSPEND ? "PM" : "USR");
2657 + if(host->hw->flags & MSDC_SYS_SUSPEND) /* set for card */
2658 + (void)mmc_suspend_host(host->mmc);
2659 + else {
2660 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* just for double confirm */ /* --- by chhung */
2661 + mmc_remove_host(host->mmc);
2662 + }
2663 + } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
2664 + if (!host->suspend){
2665 + //ERR_MSG("warning: already resume");
2666 + return;
2667 + }
2668 +
2669 + /* No PM resume when USR suspend */
2670 + if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
2671 + ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
2672 + return;
2673 + }
2674 +
2675 + host->suspend = 0;
2676 + host->pm_state = state;
2677 +
2678 + INIT_MSG("%s Resume", evt == PM_EVENT_RESUME ? "PM" : "USR");
2679 + if(host->hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
2680 + (void)mmc_resume_host(host->mmc);
2681 + }
2682 + else {
2683 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* --- by chhung */
2684 + mmc_add_host(host->mmc);
2685 + }
2686 + }
2687 +}
2688 +#endif
2689 +
2690 +/*--------------------------------------------------------------------------*/
2691 +/* mmc_host_ops members */
2692 +/*--------------------------------------------------------------------------*/
2693 +static unsigned int msdc_command_start(struct msdc_host *host,
2694 + struct mmc_command *cmd,
2695 + int tune, /* not used */
2696 + unsigned long timeout)
2697 +{
2698 + u32 base = host->base;
2699 + u32 opcode = cmd->opcode;
2700 + u32 rawcmd;
2701 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2702 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2703 + MSDC_INT_ACMD19_DONE;
2704 +
2705 + u32 resp;
2706 + unsigned long tmo;
2707 +
2708 + /* Protocol layer does not provide response type, but our hardware needs
2709 + * to know exact type, not just size!
2710 + */
2711 + if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
2712 + resp = RESP_R3;
2713 + else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
2714 + resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
2715 + else if (opcode == MMC_FAST_IO)
2716 + resp = RESP_R4;
2717 + else if (opcode == MMC_GO_IRQ_STATE)
2718 + resp = RESP_R5;
2719 + else if (opcode == MMC_SELECT_CARD)
2720 + resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
2721 + else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
2722 + resp = RESP_R1; /* SDIO workaround. */
2723 + else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
2724 + resp = RESP_R1;
2725 + else {
2726 + switch (mmc_resp_type(cmd)) {
2727 + case MMC_RSP_R1:
2728 + resp = RESP_R1;
2729 + break;
2730 + case MMC_RSP_R1B:
2731 + resp = RESP_R1B;
2732 + break;
2733 + case MMC_RSP_R2:
2734 + resp = RESP_R2;
2735 + break;
2736 + case MMC_RSP_R3:
2737 + resp = RESP_R3;
2738 + break;
2739 + case MMC_RSP_NONE:
2740 + default:
2741 + resp = RESP_NONE;
2742 + break;
2743 + }
2744 + }
2745 +
2746 + cmd->error = 0;
2747 + /* rawcmd :
2748 + * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
2749 + * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
2750 + */
2751 + rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
2752 +
2753 + if (opcode == MMC_READ_MULTIPLE_BLOCK) {
2754 + rawcmd |= (2 << 11);
2755 + } else if (opcode == MMC_READ_SINGLE_BLOCK) {
2756 + rawcmd |= (1 << 11);
2757 + } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
2758 + rawcmd |= ((2 << 11) | (1 << 13));
2759 + } else if (opcode == MMC_WRITE_BLOCK) {
2760 + rawcmd |= ((1 << 11) | (1 << 13));
2761 + } else if (opcode == SD_IO_RW_EXTENDED) {
2762 + if (cmd->data->flags & MMC_DATA_WRITE)
2763 + rawcmd |= (1 << 13);
2764 + if (cmd->data->blocks > 1)
2765 + rawcmd |= (2 << 11);
2766 + else
2767 + rawcmd |= (1 << 11);
2768 + } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
2769 + rawcmd |= (1 << 14);
2770 + } else if ((opcode == SD_APP_SEND_SCR) ||
2771 + (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
2772 + (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2773 + (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2774 + (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
2775 + rawcmd |= (1 << 11);
2776 + } else if (opcode == MMC_STOP_TRANSMISSION) {
2777 + rawcmd |= (1 << 14);
2778 + rawcmd &= ~(0x0FFF << 16);
2779 + }
2780 +
2781 + N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode , rawcmd, cmd->arg);
2782 +
2783 + tmo = jiffies + timeout;
2784 +
2785 + if (opcode == MMC_SEND_STATUS) {
2786 + for (;;) {
2787 + if (!sdc_is_cmd_busy())
2788 + break;
2789 +
2790 + if (time_after(jiffies, tmo)) {
2791 + ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
2792 + cmd->error = (unsigned int)-ETIMEDOUT;
2793 + msdc_reset();
2794 + goto end;
2795 + }
2796 + }
2797 + }else {
2798 + for (;;) {
2799 + if (!sdc_is_busy())
2800 + break;
2801 + if (time_after(jiffies, tmo)) {
2802 + ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
2803 + cmd->error = (unsigned int)-ETIMEDOUT;
2804 + msdc_reset();
2805 + goto end;
2806 + }
2807 + }
2808 + }
2809 +
2810 + //BUG_ON(in_interrupt());
2811 + host->cmd = cmd;
2812 + host->cmd_rsp = resp;
2813 +
2814 + init_completion(&host->cmd_done);
2815 +
2816 + sdr_set_bits(MSDC_INTEN, wints);
2817 + sdc_send_cmd(rawcmd, cmd->arg);
2818 +
2819 +end:
2820 + return cmd->error;
2821 +}
2822 +
2823 +static unsigned int msdc_command_resp(struct msdc_host *host,
2824 + struct mmc_command *cmd,
2825 + int tune,
2826 + unsigned long timeout)
2827 +{
2828 + u32 base = host->base;
2829 + u32 opcode = cmd->opcode;
2830 + //u32 rawcmd;
2831 + u32 resp;
2832 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2833 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2834 + MSDC_INT_ACMD19_DONE;
2835 +
2836 + resp = host->cmd_rsp;
2837 +
2838 + BUG_ON(in_interrupt());
2839 + //init_completion(&host->cmd_done);
2840 + //sdr_set_bits(MSDC_INTEN, wints);
2841 +
2842 + spin_unlock(&host->lock);
2843 + if(!wait_for_completion_timeout(&host->cmd_done, 10*timeout)){
2844 + ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
2845 + cmd->error = (unsigned int)-ETIMEDOUT;
2846 + msdc_reset();
2847 + }
2848 + spin_lock(&host->lock);
2849 +
2850 + sdr_clr_bits(MSDC_INTEN, wints);
2851 + host->cmd = NULL;
2852 +
2853 +//end:
2854 +#ifdef MT6575_SD_DEBUG
2855 + switch (resp) {
2856 + case RESP_NONE:
2857 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
2858 + break;
2859 + case RESP_R2:
2860 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
2861 + opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
2862 + cmd->resp[2], cmd->resp[3]);
2863 + break;
2864 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2865 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
2866 + opcode, cmd->error, resp, cmd->resp[0]);
2867 + if (cmd->error == 0) {
2868 + switch (resp) {
2869 + case RESP_R1:
2870 + case RESP_R1B:
2871 + msdc_dump_card_status(host, cmd->resp[0]);
2872 + break;
2873 + case RESP_R3:
2874 + msdc_dump_ocr_reg(host, cmd->resp[0]);
2875 + break;
2876 + case RESP_R5:
2877 + msdc_dump_io_resp(host, cmd->resp[0]);
2878 + break;
2879 + case RESP_R6:
2880 + msdc_dump_rca_resp(host, cmd->resp[0]);
2881 + break;
2882 + }
2883 + }
2884 + break;
2885 + }
2886 +#endif
2887 +
2888 + /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
2889 +
2890 + if (!tune) {
2891 + return cmd->error;
2892 + }
2893 +
2894 + /* memory card CRC */
2895 + if(host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
2896 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
2897 + msdc_abort_data(host);
2898 + } else {
2899 + /* do basic: reset*/
2900 + msdc_reset();
2901 + msdc_clr_fifo();
2902 + msdc_clr_int();
2903 + }
2904 + cmd->error = msdc_tune_cmdrsp(host,cmd);
2905 + }
2906 +
2907 + // check DAT0
2908 + /* if (resp == RESP_R1B) {
2909 + while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
2910 + } */
2911 + /* CMD12 Error Handle */
2912 +
2913 + return cmd->error;
2914 +}
2915 +
2916 +static unsigned int msdc_do_command(struct msdc_host *host,
2917 + struct mmc_command *cmd,
2918 + int tune,
2919 + unsigned long timeout)
2920 +{
2921 + if (msdc_command_start(host, cmd, tune, timeout))
2922 + goto end;
2923 +
2924 + if (msdc_command_resp(host, cmd, tune, timeout))
2925 + goto end;
2926 +
2927 +end:
2928 +
2929 + N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
2930 + return cmd->error;
2931 +}
2932 +
2933 +/* The abort condition when PIO read/write
2934 + tmo:
2935 +*/
2936 +static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
2937 +{
2938 + int ret = 0;
2939 + u32 base = host->base;
2940 +
2941 + if (atomic_read(&host->abort)) {
2942 + ret = 1;
2943 + }
2944 +
2945 + if (time_after(jiffies, tmo)) {
2946 + data->error = (unsigned int)-ETIMEDOUT;
2947 + ERR_MSG("XXX PIO Data Timeout: CMD<%d>", host->mrq->cmd->opcode);
2948 + ret = 1;
2949 + }
2950 +
2951 + if(ret) {
2952 + msdc_reset();
2953 + msdc_clr_fifo();
2954 + msdc_clr_int();
2955 + ERR_MSG("msdc pio find abort");
2956 + }
2957 + return ret;
2958 +}
2959 +
2960 +/*
2961 + Need to add a timeout, or WDT timeout, system reboot.
2962 +*/
2963 +// pio mode data read/write
2964 +static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
2965 +{
2966 + struct scatterlist *sg = data->sg;
2967 + u32 base = host->base;
2968 + u32 num = data->sg_len;
2969 + u32 *ptr;
2970 + u8 *u8ptr;
2971 + u32 left = 0;
2972 + u32 count, size = 0;
2973 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
2974 + unsigned long tmo = jiffies + DAT_TIMEOUT;
2975 +
2976 + sdr_set_bits(MSDC_INTEN, wints);
2977 + while (num) {
2978 + left = sg_dma_len(sg);
2979 + ptr = sg_virt(sg);
2980 + while (left) {
2981 + if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
2982 + count = MSDC_FIFO_THD >> 2;
2983 + do {
2984 + *ptr++ = msdc_fifo_read32();
2985 + } while (--count);
2986 + left -= MSDC_FIFO_THD;
2987 + } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
2988 + while (left > 3) {
2989 + *ptr++ = msdc_fifo_read32();
2990 + left -= 4;
2991 + }
2992 +
2993 + u8ptr = (u8 *)ptr;
2994 + while(left) {
2995 + * u8ptr++ = msdc_fifo_read8();
2996 + left--;
2997 + }
2998 + }
2999 +
3000 + if (msdc_pio_abort(host, data, tmo)) {
3001 + goto end;
3002 + }
3003 + }
3004 + size += sg_dma_len(sg);
3005 + sg = sg_next(sg); num--;
3006 + }
3007 +end:
3008 + data->bytes_xfered += size;
3009 + N_MSG(FIO, " PIO Read<%d>bytes", size);
3010 +
3011 + sdr_clr_bits(MSDC_INTEN, wints);
3012 + if(data->error) ERR_MSG("read pio data->error<%d> left<%d> size<%d>", data->error, left, size);
3013 + return data->error;
3014 +}
3015 +
3016 +/* please make sure won't using PIO when size >= 512
3017 + which means, memory card block read/write won't using pio
3018 + then don't need to handle the CMD12 when data error.
3019 +*/
3020 +static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
3021 +{
3022 + u32 base = host->base;
3023 + struct scatterlist *sg = data->sg;
3024 + u32 num = data->sg_len;
3025 + u32 *ptr;
3026 + u8 *u8ptr;
3027 + u32 left;
3028 + u32 count, size = 0;
3029 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3030 + unsigned long tmo = jiffies + DAT_TIMEOUT;
3031 +
3032 + sdr_set_bits(MSDC_INTEN, wints);
3033 + while (num) {
3034 + left = sg_dma_len(sg);
3035 + ptr = sg_virt(sg);
3036 +
3037 + while (left) {
3038 + if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3039 + count = MSDC_FIFO_SZ >> 2;
3040 + do {
3041 + msdc_fifo_write32(*ptr); ptr++;
3042 + } while (--count);
3043 + left -= MSDC_FIFO_SZ;
3044 + } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3045 + while (left > 3) {
3046 + msdc_fifo_write32(*ptr); ptr++;
3047 + left -= 4;
3048 + }
3049 +
3050 + u8ptr = (u8*)ptr;
3051 + while(left){
3052 + msdc_fifo_write8(*u8ptr); u8ptr++;
3053 + left--;
3054 + }
3055 + }
3056 +
3057 + if (msdc_pio_abort(host, data, tmo)) {
3058 + goto end;
3059 + }
3060 + }
3061 + size += sg_dma_len(sg);
3062 + sg = sg_next(sg); num--;
3063 + }
3064 +end:
3065 + data->bytes_xfered += size;
3066 + N_MSG(FIO, " PIO Write<%d>bytes", size);
3067 + if(data->error) ERR_MSG("write pio data->error<%d>", data->error);
3068 +
3069 + sdr_clr_bits(MSDC_INTEN, wints);
3070 + return data->error;
3071 +}
3072 +
3073 +#if 0 /* --- by chhung */
3074 +// DMA resume / start / stop
3075 +static void msdc_dma_resume(struct msdc_host *host)
3076 +{
3077 + u32 base = host->base;
3078 +
3079 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
3080 +
3081 + N_MSG(DMA, "DMA resume");
3082 +}
3083 +#endif /* end of --- */
3084 +
3085 +static void msdc_dma_start(struct msdc_host *host)
3086 +{
3087 + u32 base = host->base;
3088 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3089 +
3090 + sdr_set_bits(MSDC_INTEN, wints);
3091 + //dsb(); /* --- by chhung */
3092 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
3093 +
3094 + N_MSG(DMA, "DMA start");
3095 +}
3096 +
3097 +static void msdc_dma_stop(struct msdc_host *host)
3098 +{
3099 + u32 base = host->base;
3100 + //u32 retries=500;
3101 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3102 +
3103 + N_MSG(DMA, "DMA status: 0x%.8x",sdr_read32(MSDC_DMA_CFG));
3104 + //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3105 +
3106 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
3107 + while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3108 +
3109 + //dsb(); /* --- by chhung */
3110 + sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
3111 +
3112 + N_MSG(DMA, "DMA stop");
3113 +}
3114 +
3115 +#if 0 /* --- by chhung */
3116 +/* dump a gpd list */
3117 +static void msdc_dma_dump(struct msdc_host *host, struct msdc_dma *dma)
3118 +{
3119 + gpd_t *gpd = dma->gpd;
3120 + bd_t *bd = dma->bd;
3121 + bd_t *ptr;
3122 + int i = 0;
3123 + int p_to_v;
3124 +
3125 + if (dma->mode != MSDC_MODE_DMA_DESC) {
3126 + return;
3127 + }
3128 +
3129 + ERR_MSG("try to dump gpd and bd");
3130 +
3131 + /* dump gpd */
3132 + ERR_MSG(".gpd<0x%.8x> gpd_phy<0x%.8x>", (int)gpd, (int)dma->gpd_addr);
3133 + ERR_MSG("...hwo <%d>", gpd->hwo );
3134 + ERR_MSG("...bdp <%d>", gpd->bdp );
3135 + ERR_MSG("...chksum<0x%.8x>", gpd->chksum );
3136 + //ERR_MSG("...intr <0x%.8x>", gpd->intr );
3137 + ERR_MSG("...next <0x%.8x>", (int)gpd->next );
3138 + ERR_MSG("...ptr <0x%.8x>", (int)gpd->ptr );
3139 + ERR_MSG("...buflen<0x%.8x>", gpd->buflen );
3140 + //ERR_MSG("...extlen<0x%.8x>", gpd->extlen );
3141 + //ERR_MSG("...arg <0x%.8x>", gpd->arg );
3142 + //ERR_MSG("...blknum<0x%.8x>", gpd->blknum );
3143 + //ERR_MSG("...cmd <0x%.8x>", gpd->cmd );
3144 +
3145 + /* dump bd */
3146 + ERR_MSG(".bd<0x%.8x> bd_phy<0x%.8x> gpd_ptr<0x%.8x>", (int)bd, (int)dma->bd_addr, (int)gpd->ptr);
3147 + ptr = bd;
3148 + p_to_v = ((u32)bd - (u32)dma->bd_addr);
3149 + while (1) {
3150 + ERR_MSG(".bd[%d]", i); i++;
3151 + ERR_MSG("...eol <%d>", ptr->eol );
3152 + ERR_MSG("...chksum<0x%.8x>", ptr->chksum );
3153 + //ERR_MSG("...blkpad<0x%.8x>", ptr->blkpad );
3154 + //ERR_MSG("...dwpad <0x%.8x>", ptr->dwpad );
3155 + ERR_MSG("...next <0x%.8x>", (int)ptr->next );
3156 + ERR_MSG("...ptr <0x%.8x>", (int)ptr->ptr );
3157 + ERR_MSG("...buflen<0x%.8x>", (int)ptr->buflen );
3158 +
3159 + if (ptr->eol == 1) {
3160 + break;
3161 + }
3162 +
3163 + /* find the next bd, virtual address of ptr->next */
3164 + /* don't need to enable when use malloc */
3165 + //BUG_ON( (ptr->next + p_to_v)!=(ptr+1) );
3166 + //ERR_MSG(".next bd<0x%.8x><0x%.8x>", (ptr->next + p_to_v), (ptr+1));
3167 + ptr++;
3168 + }
3169 +
3170 + ERR_MSG("dump gpd and bd finished");
3171 +}
3172 +#endif /* end of --- */
3173 +
3174 +/* calc checksum */
3175 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
3176 +{
3177 + u32 i, sum = 0;
3178 + for (i = 0; i < len; i++) {
3179 + sum += buf[i];
3180 + }
3181 + return 0xFF - (u8)sum;
3182 +}
3183 +
3184 +/* gpd bd setup + dma registers */
3185 +static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
3186 +{
3187 + u32 base = host->base;
3188 + u32 sglen = dma->sglen;
3189 + //u32 i, j, num, bdlen, arg, xfersz;
3190 + u32 j, num, bdlen;
3191 + u8 blkpad, dwpad, chksum;
3192 + struct scatterlist *sg = dma->sg;
3193 + gpd_t *gpd;
3194 + bd_t *bd;
3195 +
3196 + switch (dma->mode) {
3197 + case MSDC_MODE_DMA_BASIC:
3198 + BUG_ON(dma->xfersz > 65535);
3199 + BUG_ON(dma->sglen != 1);
3200 + sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
3201 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
3202 +//#if defined (CONFIG_RALINK_MT7620)
3203 + if (ralink_soc == MT762X_SOC_MT7620A)
3204 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
3205 +//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3206 + else
3207 + sdr_write32((volatile u32*)(RALINK_MSDC_BASE+0xa8), sg_dma_len(sg));
3208 +//#endif
3209 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3210 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
3211 + break;
3212 + case MSDC_MODE_DMA_DESC:
3213 + blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
3214 + dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
3215 + chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
3216 +
3217 + /* calculate the required number of gpd */
3218 + num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
3219 + BUG_ON(num !=1 );
3220 +
3221 + gpd = dma->gpd;
3222 + bd = dma->bd;
3223 + bdlen = sglen;
3224 +
3225 + /* modify gpd*/
3226 + //gpd->intr = 0;
3227 + gpd->hwo = 1; /* hw will clear it */
3228 + gpd->bdp = 1;
3229 + gpd->chksum = 0; /* need to clear first. */
3230 + gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
3231 +
3232 + /* modify bd*/
3233 + for (j = 0; j < bdlen; j++) {
3234 + msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
3235 + if(j == bdlen - 1) {
3236 + bd[j].eol = 1; /* the last bd */
3237 + } else {
3238 + bd[j].eol = 0;
3239 + }
3240 + bd[j].chksum = 0; /* checksume need to clear first */
3241 + bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
3242 + sg++;
3243 + }
3244 +
3245 + dma->used_gpd += 2;
3246 + dma->used_bd += bdlen;
3247 +
3248 + sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
3249 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3250 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
3251 +
3252 + sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
3253 + break;
3254 +
3255 + default:
3256 + break;
3257 + }
3258 +
3259 + N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3260 + N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3261 + N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3262 +
3263 + return 0;
3264 +}
3265 +
3266 +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
3267 + struct scatterlist *sg, unsigned int sglen)
3268 +{
3269 + BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
3270 +
3271 + dma->sg = sg;
3272 + dma->flags = DMA_FLAG_EN_CHKSUM;
3273 + //dma->flags = DMA_FLAG_NONE; /* CHECKME */
3274 + dma->sglen = sglen;
3275 + dma->xfersz = host->xfer_size;
3276 + dma->burstsz = MSDC_BRUST_64B;
3277 +
3278 + if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
3279 + dma->mode = MSDC_MODE_DMA_BASIC;
3280 + else
3281 + dma->mode = MSDC_MODE_DMA_DESC;
3282 +
3283 + N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, dma->xfersz);
3284 +
3285 + msdc_dma_config(host, dma);
3286 +
3287 + /*if (dma->mode == MSDC_MODE_DMA_DESC) {
3288 + //msdc_dma_dump(host, dma);
3289 + } */
3290 +}
3291 +
3292 +/* set block number before send command */
3293 +static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
3294 +{
3295 + u32 base = host->base;
3296 +
3297 + sdr_write32(SDC_BLK_NUM, blknum);
3298 +}
3299 +
3300 +static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
3301 +{
3302 + struct msdc_host *host = mmc_priv(mmc);
3303 + struct mmc_command *cmd;
3304 + struct mmc_data *data;
3305 + u32 base = host->base;
3306 + //u32 intsts = 0;
3307 + unsigned int left=0;
3308 + int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
3309 +
3310 + #define SND_DAT 0
3311 + #define SND_CMD 1
3312 +
3313 + BUG_ON(mmc == NULL);
3314 + BUG_ON(mrq == NULL);
3315 +
3316 + host->error = 0;
3317 + atomic_set(&host->abort, 0);
3318 +
3319 + cmd = mrq->cmd;
3320 + data = mrq->cmd->data;
3321 +
3322 +#if 0 /* --- by chhung */
3323 + //if(host->id ==1){
3324 + N_MSG(OPS, "enable clock!");
3325 + msdc_ungate_clock(host->id);
3326 + //}
3327 +#endif /* end of --- */
3328 +
3329 + if (!data) {
3330 + send_type=SND_CMD;
3331 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3332 + goto done;
3333 + }
3334 + } else {
3335 + BUG_ON(data->blksz > HOST_MAX_BLKSZ);
3336 + send_type=SND_DAT;
3337 +
3338 + data->error = 0;
3339 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3340 + host->data = data;
3341 + host->xfer_size = data->blocks * data->blksz;
3342 + host->blksz = data->blksz;
3343 +
3344 + /* deside the transfer mode */
3345 + if (drv_mode[host->id] == MODE_PIO) {
3346 + host->dma_xfer = dma = 0;
3347 + } else if (drv_mode[host->id] == MODE_DMA) {
3348 + host->dma_xfer = dma = 1;
3349 + } else if (drv_mode[host->id] == MODE_SIZE_DEP) {
3350 + host->dma_xfer = dma = ((host->xfer_size >= dma_size[host->id]) ? 1 : 0);
3351 + }
3352 +
3353 + if (read) {
3354 + if ((host->timeout_ns != data->timeout_ns) ||
3355 + (host->timeout_clks != data->timeout_clks)) {
3356 + msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
3357 + }
3358 + }
3359 +
3360 + msdc_set_blknum(host, data->blocks);
3361 + //msdc_clr_fifo(); /* no need */
3362 +
3363 + if (dma) {
3364 + msdc_dma_on(); /* enable DMA mode first!! */
3365 + init_completion(&host->xfer_done);
3366 +
3367 + /* start the command first*/
3368 + if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
3369 + goto done;
3370 +
3371 + dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
3372 + (void)dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3373 + msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
3374 +
3375 + /* then wait command done */
3376 + if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
3377 + goto done;
3378 +
3379 + /* for read, the data coming too fast, then CRC error
3380 + start DMA no business with CRC. */
3381 + //init_completion(&host->xfer_done);
3382 + msdc_dma_start(host);
3383 +
3384 + spin_unlock(&host->lock);
3385 + if(!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)){
3386 + ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
3387 + ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3388 + ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
3389 + ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3390 + ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3391 + data->error = (unsigned int)-ETIMEDOUT;
3392 +
3393 + msdc_reset();
3394 + msdc_clr_fifo();
3395 + msdc_clr_int();
3396 + }
3397 + spin_lock(&host->lock);
3398 + msdc_dma_stop(host);
3399 + } else {
3400 + /* Firstly: send command */
3401 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3402 + goto done;
3403 + }
3404 +
3405 + /* Secondly: pio data phase */
3406 + if (read) {
3407 + if (msdc_pio_read(host, data)){
3408 + goto done;
3409 + }
3410 + } else {
3411 + if (msdc_pio_write(host, data)) {
3412 + goto done;
3413 + }
3414 + }
3415 +
3416 + /* For write case: make sure contents in fifo flushed to device */
3417 + if (!read) {
3418 + while (1) {
3419 + left=msdc_txfifocnt();
3420 + if (left == 0) {
3421 + break;
3422 + }
3423 + if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
3424 + break;
3425 + /* Fix me: what about if data error, when stop ? how to? */
3426 + }
3427 + }
3428 + } else {
3429 + /* Fix me: read case: need to check CRC error */
3430 + }
3431 +
3432 + /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
3433 + For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
3434 + */
3435 +
3436 + /* try not to wait xfer_comp interrupt.
3437 + the next command will check SDC_BUSY.
3438 + SDC_BUSY means xfer_comp assert
3439 + */
3440 +
3441 + } // PIO mode
3442 +
3443 + /* Last: stop transfer */
3444 + if (data->stop){
3445 + if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
3446 + goto done;
3447 + }
3448 + }
3449 + }
3450 +
3451 +done:
3452 + if (data != NULL) {
3453 + host->data = NULL;
3454 + host->dma_xfer = 0;
3455 + if (dma != 0) {
3456 + msdc_dma_off();
3457 + host->dma.used_bd = 0;
3458 + host->dma.used_gpd = 0;
3459 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3460 + }
3461 + host->blksz = 0;
3462 +
3463 +#if 0 // don't stop twice!
3464 + if(host->hw->flags & MSDC_REMOVABLE && data->error) {
3465 + msdc_abort_data(host);
3466 + /* reset in IRQ, stop command has issued. -> No need */
3467 + }
3468 +#endif
3469 +
3470 + N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio"),
3471 + (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
3472 + }
3473 +
3474 +#if 0 /* --- by chhung */
3475 +#if 1
3476 + //if(host->id==1) {
3477 + if(send_type==SND_CMD) {
3478 + if(cmd->opcode == MMC_SEND_STATUS) {
3479 + if((cmd->resp[0] & CARD_READY_FOR_DATA) ||(CARD_CURRENT_STATE(cmd->resp[0]) != 7)){
3480 + N_MSG(OPS,"disable clock, CMD13 IDLE");
3481 + msdc_gate_clock(host->id);
3482 + }
3483 + } else {
3484 + N_MSG(OPS,"disable clock, CMD<%d>", cmd->opcode);
3485 + msdc_gate_clock(host->id);
3486 + }
3487 + } else {
3488 + if(read) {
3489 + N_MSG(OPS,"disable clock!!! Read CMD<%d>",cmd->opcode);
3490 + msdc_gate_clock(host->id);
3491 + }
3492 + }
3493 + //}
3494 +#else
3495 + msdc_gate_clock(host->id);
3496 +#endif
3497 +#endif /* end of --- */
3498 +
3499 + if (mrq->cmd->error) host->error = 0x001;
3500 + if (mrq->data && mrq->data->error) host->error |= 0x010;
3501 + if (mrq->stop && mrq->stop->error) host->error |= 0x100;
3502 +
3503 + //if (host->error) ERR_MSG("host->error<%d>", host->error);
3504 +
3505 + return host->error;
3506 +}
3507 +
3508 +static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
3509 +{
3510 + struct mmc_command cmd;
3511 + struct mmc_request mrq;
3512 + u32 err;
3513 +
3514 + memset(&cmd, 0, sizeof(struct mmc_command));
3515 + cmd.opcode = MMC_APP_CMD;
3516 +#if 0 /* bug: we meet mmc->card is null when ACMD6 */
3517 + cmd.arg = mmc->card->rca << 16;
3518 +#else
3519 + cmd.arg = host->app_cmd_arg;
3520 +#endif
3521 + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
3522 +
3523 + memset(&mrq, 0, sizeof(struct mmc_request));
3524 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3525 + cmd.data = NULL;
3526 +
3527 + err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
3528 + return err;
3529 +}
3530 +
3531 +static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
3532 +{
3533 + int result = -1;
3534 + u32 base = host->base;
3535 + u32 rsmpl, cur_rsmpl, orig_rsmpl;
3536 + u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
3537 + u32 skip = 1;
3538 +
3539 + /* ==== don't support 3.0 now ====
3540 + 1: R_SMPL[1]
3541 + 2: PAD_CMD_RESP_RXDLY[26:22]
3542 + ==========================*/
3543 +
3544 + // save the previous tune result
3545 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
3546 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
3547 +
3548 + rrdly = 0;
3549 + do {
3550 + for (rsmpl = 0; rsmpl < 2; rsmpl++) {
3551 + /* Lv1: R_SMPL[1] */
3552 + cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
3553 + if (skip == 1) {
3554 + skip = 0;
3555 + continue;
3556 + }
3557 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
3558 +
3559 + if (host->app_cmd) {
3560 + result = msdc_app_cmd(host->mmc, host);
3561 + if (result) {
3562 + ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
3563 + host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
3564 + continue;
3565 + }
3566 + }
3567 + result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
3568 + ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
3569 + (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
3570 +
3571 + if (result == 0) {
3572 + return 0;
3573 + }
3574 + if (result != (unsigned int)(-EIO)) {
3575 + ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
3576 + return result;
3577 + }
3578 +
3579 + /* should be EIO */
3580 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
3581 + msdc_abort_data(host);
3582 + }
3583 + }
3584 +
3585 + /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
3586 + cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
3587 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
3588 + }while (++rrdly < 32);
3589 +
3590 + return result;
3591 +}
3592 +
3593 +/* Support SD2.0 Only */
3594 +static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
3595 +{
3596 + struct msdc_host *host = mmc_priv(mmc);
3597 + u32 base = host->base;
3598 + u32 ddr=0;
3599 + u32 dcrc=0;
3600 + u32 rxdly, cur_rxdly0, cur_rxdly1;
3601 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3602 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3603 + u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
3604 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3605 + u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
3606 + int result = -1;
3607 + u32 skip = 1;
3608 +
3609 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
3610 +
3611 + /* Tune Method 2. */
3612 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3613 +
3614 + rxdly = 0;
3615 + do {
3616 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3617 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3618 + if (skip == 1) {
3619 + skip = 0;
3620 + continue;
3621 + }
3622 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3623 +
3624 + if (host->app_cmd) {
3625 + result = msdc_app_cmd(host->mmc, host);
3626 + if (result) {
3627 + ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
3628 + continue;
3629 + }
3630 + }
3631 + result = msdc_do_request(mmc,mrq);
3632 +
3633 + sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
3634 + if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
3635 + ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
3636 + (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
3637 + sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
3638 +
3639 + /* Fix me: result is 0, but dcrc is still exist */
3640 + if (result == 0 && dcrc == 0) {
3641 + goto done;
3642 + } else {
3643 + /* there is a case: command timeout, and data phase not processed */
3644 + if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
3645 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3646 + result, mrq->cmd->error, mrq->data->error);
3647 + goto done;
3648 + }
3649 + }
3650 + }
3651 +
3652 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3653 + cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
3654 +
3655 + /* E1 ECO. YD: Reverse */
3656 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3657 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3658 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3659 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3660 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3661 + orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
3662 + orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
3663 + orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
3664 + orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
3665 + } else {
3666 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3667 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3668 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3669 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3670 + orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
3671 + orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
3672 + orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
3673 + orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
3674 + }
3675 +
3676 + if (ddr) {
3677 + cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3678 + cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3679 + cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3680 + cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3681 + } else {
3682 + cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3683 + cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3684 + cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3685 + cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3686 + }
3687 + cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
3688 + cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
3689 + cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
3690 + cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
3691 +
3692 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3693 + cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
3694 +
3695 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3696 + sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
3697 +
3698 + } while (++rxdly < 32);
3699 +
3700 +done:
3701 + return result;
3702 +}
3703 +
3704 +static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
3705 +{
3706 + struct msdc_host *host = mmc_priv(mmc);
3707 + u32 base = host->base;
3708 +
3709 + u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
3710 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3711 + u32 rxdly, cur_rxdly0;
3712 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3713 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3714 + int result = -1;
3715 + u32 skip = 1;
3716 +
3717 + // MSDC_IOCON_DDR50CKD need to check. [Fix me]
3718 +
3719 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
3720 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
3721 +
3722 + /* Tune Method 2. just DAT0 */
3723 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3724 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3725 +
3726 + /* E1 ECO. YD: Reverse */
3727 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3728 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3729 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3730 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3731 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3732 + } else {
3733 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3734 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3735 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3736 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3737 + }
3738 +
3739 + rxdly = 0;
3740 + do {
3741 + wrrdly = 0;
3742 + do {
3743 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3744 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3745 + if (skip == 1) {
3746 + skip = 0;
3747 + continue;
3748 + }
3749 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3750 +
3751 + if (host->app_cmd) {
3752 + result = msdc_app_cmd(host->mmc, host);
3753 + if (result) {
3754 + ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
3755 + continue;
3756 + }
3757 + }
3758 + result = msdc_do_request(mmc,mrq);
3759 +
3760 + ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
3761 + result == 0 ? "PASS" : "FAIL",
3762 + cur_dsmpl, cur_wrrdly, cur_rxdly0);
3763 +
3764 + if (result == 0) {
3765 + goto done;
3766 + }
3767 + else {
3768 + /* there is a case: command timeout, and data phase not processed */
3769 + if (mrq->data->error != (unsigned int)(-EIO)) {
3770 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3771 + result, mrq->cmd->error, mrq->data->error);
3772 + goto done;
3773 + }
3774 + }
3775 + }
3776 + cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
3777 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
3778 + } while (++wrrdly < 32);
3779 +
3780 + cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
3781 + cur_dat1 = orig_dat1;
3782 + cur_dat2 = orig_dat2;
3783 + cur_dat3 = orig_dat3;
3784 +
3785 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3786 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3787 + } while (++rxdly < 32);
3788 +
3789 +done:
3790 + return result;
3791 +}
3792 +
3793 +static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
3794 +{
3795 + struct mmc_command cmd;
3796 + struct mmc_request mrq;
3797 + u32 err;
3798 +
3799 + memset(&cmd, 0, sizeof(struct mmc_command));
3800 + cmd.opcode = MMC_SEND_STATUS;
3801 + if (mmc->card) {
3802 + cmd.arg = mmc->card->rca << 16;
3803 + } else {
3804 + ERR_MSG("cmd13 mmc card is null");
3805 + cmd.arg = host->app_cmd_arg;
3806 + }
3807 + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
3808 +
3809 + memset(&mrq, 0, sizeof(struct mmc_request));
3810 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3811 + cmd.data = NULL;
3812 +
3813 + err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
3814 +
3815 + if (status) {
3816 + *status = cmd.resp[0];
3817 + }
3818 +
3819 + return err;
3820 +}
3821 +
3822 +static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
3823 +{
3824 + u32 err = 0;
3825 + u32 status = 0;
3826 +
3827 + do {
3828 + err = msdc_get_card_status(mmc, host, &status);
3829 + if (err) return err;
3830 + /* need cmd12? */
3831 + ERR_MSG("cmd<13> resp<0x%x>", status);
3832 + } while (R1_CURRENT_STATE(status) == 7);
3833 +
3834 + return err;
3835 +}
3836 +
3837 +/* failed when msdc_do_request */
3838 +static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
3839 +{
3840 + struct msdc_host *host = mmc_priv(mmc);
3841 + struct mmc_command *cmd;
3842 + struct mmc_data *data;
3843 + //u32 base = host->base;
3844 + int ret=0, read;
3845 +
3846 + cmd = mrq->cmd;
3847 + data = mrq->cmd->data;
3848 +
3849 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3850 +
3851 + if (read) {
3852 + if (data->error == (unsigned int)(-EIO)) {
3853 + ret = msdc_tune_bread(mmc,mrq);
3854 + }
3855 + } else {
3856 + ret = msdc_check_busy(mmc, host);
3857 + if (ret){
3858 + ERR_MSG("XXX cmd13 wait program done failed");
3859 + return ret;
3860 + }
3861 + /* CRC and TO */
3862 + /* Fix me: don't care card status? */
3863 + ret = msdc_tune_bwrite(mmc,mrq);
3864 + }
3865 +
3866 + return ret;
3867 +}
3868 +
3869 +/* ops.request */
3870 +static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
3871 +{
3872 + struct msdc_host *host = mmc_priv(mmc);
3873 +
3874 + //=== for sdio profile ===
3875 +#if 0 /* --- by chhung */
3876 + u32 old_H32, old_L32, new_H32, new_L32;
3877 + u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
3878 +#endif /* end of --- */
3879 +
3880 + if(host->mrq){
3881 + ERR_MSG("XXX host->mrq<0x%.8x>", (int)host->mrq);
3882 + BUG();
3883 + }
3884 +
3885 + if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
3886 + ERR_MSG("cmd<%d> card<%d> power<%d>", mrq->cmd->opcode, is_card_present(host), host->power_mode);
3887 + mrq->cmd->error = (unsigned int)-ENOMEDIUM;
3888 +
3889 +#if 1
3890 + mrq->done(mrq); // call done directly.
3891 +#else
3892 + mrq->cmd->retries = 0; // please don't retry.
3893 + mmc_request_done(mmc, mrq);
3894 +#endif
3895 +
3896 + return;
3897 + }
3898 +
3899 + /* start to process */
3900 + spin_lock(&host->lock);
3901 +#if 0 /* --- by chhung */
3902 + if (sdio_pro_enable) { //=== for sdio profile ===
3903 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3904 + GPT_GetCounter64(&old_L32, &old_H32);
3905 + }
3906 + }
3907 +#endif /* end of --- */
3908 +
3909 + host->mrq = mrq;
3910 +
3911 + if (msdc_do_request(mmc,mrq)) {
3912 + if(host->hw->flags & MSDC_REMOVABLE && ralink_soc == MT762X_SOC_MT7621AT && mrq->data && mrq->data->error) {
3913 + msdc_tune_request(mmc,mrq);
3914 + }
3915 + }
3916 +
3917 + /* ==== when request done, check if app_cmd ==== */
3918 + if (mrq->cmd->opcode == MMC_APP_CMD) {
3919 + host->app_cmd = 1;
3920 + host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
3921 + } else {
3922 + host->app_cmd = 0;
3923 + //host->app_cmd_arg = 0;
3924 + }
3925 +
3926 + host->mrq = NULL;
3927 +
3928 +#if 0 /* --- by chhung */
3929 + //=== for sdio profile ===
3930 + if (sdio_pro_enable) {
3931 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3932 + GPT_GetCounter64(&new_L32, &new_H32);
3933 + ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
3934 +
3935 + opcode = mrq->cmd->opcode;
3936 + if (mrq->cmd->data) {
3937 + sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
3938 + bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0 ;
3939 + } else {
3940 + bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
3941 + }
3942 +
3943 + if (!mrq->cmd->error) {
3944 + msdc_performance(opcode, sizes, bRx, ticks);
3945 + }
3946 + }
3947 + }
3948 +#endif /* end of --- */
3949 + spin_unlock(&host->lock);
3950 +
3951 + mmc_request_done(mmc, mrq);
3952 +
3953 + return;
3954 +}
3955 +
3956 +/* called by ops.set_ios */
3957 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
3958 +{
3959 + u32 base = host->base;
3960 + u32 val = sdr_read32(SDC_CFG);
3961 +
3962 + val &= ~SDC_CFG_BUSWIDTH;
3963 +
3964 + switch (width) {
3965 + default:
3966 + case MMC_BUS_WIDTH_1:
3967 + width = 1;
3968 + val |= (MSDC_BUS_1BITS << 16);
3969 + break;
3970 + case MMC_BUS_WIDTH_4:
3971 + val |= (MSDC_BUS_4BITS << 16);
3972 + break;
3973 + case MMC_BUS_WIDTH_8:
3974 + val |= (MSDC_BUS_8BITS << 16);
3975 + break;
3976 + }
3977 +
3978 + sdr_write32(SDC_CFG, val);
3979 +
3980 + N_MSG(CFG, "Bus Width = %d", width);
3981 +}
3982 +
3983 +/* ops.set_ios */
3984 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
3985 +{
3986 + struct msdc_host *host = mmc_priv(mmc);
3987 + struct msdc_hw *hw=host->hw;
3988 + u32 base = host->base;
3989 + u32 ddr = 0;
3990 +
3991 +#ifdef MT6575_SD_DEBUG
3992 + static char *vdd[] = {
3993 + "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
3994 + "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
3995 + "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
3996 + "3.40v", "3.50v", "3.60v"
3997 + };
3998 + static char *power_mode[] = {
3999 + "OFF", "UP", "ON"
4000 + };
4001 + static char *bus_mode[] = {
4002 + "UNKNOWN", "OPENDRAIN", "PUSHPULL"
4003 + };
4004 + static char *timing[] = {
4005 + "LEGACY", "MMC_HS", "SD_HS"
4006 + };
4007 +
4008 + printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
4009 + ios->clock / 1000, bus_mode[ios->bus_mode],
4010 + (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
4011 + power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
4012 +#endif
4013 +
4014 + msdc_set_buswidth(host, ios->bus_width);
4015 +
4016 + /* Power control ??? */
4017 + switch (ios->power_mode) {
4018 + case MMC_POWER_OFF:
4019 + case MMC_POWER_UP:
4020 + // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
4021 + break;
4022 + case MMC_POWER_ON:
4023 + host->power_mode = MMC_POWER_ON;
4024 + break;
4025 + default:
4026 + break;
4027 + }
4028 +
4029 + /* Clock control */
4030 + if (host->mclk != ios->clock) {
4031 + if(ios->clock > 25000000) {
4032 + //if (!(host->hw->flags & MSDC_REMOVABLE)) {
4033 + INIT_MSG("SD data latch edge<%d>", hw->data_edge);
4034 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
4035 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
4036 + //} /* for tuning debug */
4037 + } else { /* default value */
4038 + sdr_write32(MSDC_IOCON, 0x00000000);
4039 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4040 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4041 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4042 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4043 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4044 + }
4045 + msdc_set_mclk(host, ddr, ios->clock);
4046 + }
4047 +}
4048 +
4049 +/* ops.get_ro */
4050 +static int msdc_ops_get_ro(struct mmc_host *mmc)
4051 +{
4052 + struct msdc_host *host = mmc_priv(mmc);
4053 + u32 base = host->base;
4054 + unsigned long flags;
4055 + int ro = 0;
4056 +
4057 + if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
4058 + spin_lock_irqsave(&host->lock, flags);
4059 + ro = (sdr_read32(MSDC_PS) >> 31);
4060 + spin_unlock_irqrestore(&host->lock, flags);
4061 + }
4062 + return ro;
4063 +}
4064 +
4065 +/* ops.get_cd */
4066 +static int msdc_ops_get_cd(struct mmc_host *mmc)
4067 +{
4068 + struct msdc_host *host = mmc_priv(mmc);
4069 + u32 base = host->base;
4070 + unsigned long flags;
4071 + int present = 1;
4072 +
4073 + /* for sdio, MSDC_REMOVABLE not set, always return 1 */
4074 + if (!(host->hw->flags & MSDC_REMOVABLE)) {
4075 + /* For sdio, read H/W always get<1>, but may timeout some times */
4076 +#if 1
4077 + host->card_inserted = 1;
4078 + return 1;
4079 +#else
4080 + host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
4081 + INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
4082 + return host->card_inserted;
4083 +#endif
4084 + }
4085 +
4086 + /* MSDC_CD_PIN_EN set for card */
4087 + if (host->hw->flags & MSDC_CD_PIN_EN) {
4088 + spin_lock_irqsave(&host->lock, flags);
4089 +#if 0
4090 + present = host->card_inserted; /* why not read from H/W: Fix me*/
4091 +#else
4092 + // CD
4093 + if (cd_active_low)
4094 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
4095 + else
4096 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0;
4097 + if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
4098 + present = 1;
4099 + host->card_inserted = present;
4100 +#endif
4101 + spin_unlock_irqrestore(&host->lock, flags);
4102 + } else {
4103 + present = 0; /* TODO? Check DAT3 pins for card detection */
4104 + }
4105 +
4106 + INIT_MSG("ops_get_cd return<%d>", present);
4107 + return present;
4108 +}
4109 +
4110 +/* ops.enable_sdio_irq */
4111 +static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
4112 +{
4113 + struct msdc_host *host = mmc_priv(mmc);
4114 + struct msdc_hw *hw = host->hw;
4115 + u32 base = host->base;
4116 + u32 tmp;
4117 +
4118 + if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
4119 + if (enable) {
4120 + hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
4121 + } else {
4122 + hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
4123 + }
4124 + } else {
4125 + ERR_MSG("XXX "); /* so never enter here */
4126 + tmp = sdr_read32(SDC_CFG);
4127 + /* FIXME. Need to interrupt gap detection */
4128 + if (enable) {
4129 + tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4130 + } else {
4131 + tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4132 + }
4133 + sdr_write32(SDC_CFG, tmp);
4134 + }
4135 +}
4136 +
4137 +static struct mmc_host_ops mt_msdc_ops = {
4138 + .request = msdc_ops_request,
4139 + .set_ios = msdc_ops_set_ios,
4140 + .get_ro = msdc_ops_get_ro,
4141 + .get_cd = msdc_ops_get_cd,
4142 + .enable_sdio_irq = msdc_ops_enable_sdio_irq,
4143 +};
4144 +
4145 +/*--------------------------------------------------------------------------*/
4146 +/* interrupt handler */
4147 +/*--------------------------------------------------------------------------*/
4148 +static irqreturn_t msdc_irq(int irq, void *dev_id)
4149 +{
4150 + struct msdc_host *host = (struct msdc_host *)dev_id;
4151 + struct mmc_data *data = host->data;
4152 + struct mmc_command *cmd = host->cmd;
4153 + u32 base = host->base;
4154 +
4155 + u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
4156 + MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
4157 + MSDC_INT_ACMD19_DONE;
4158 + u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
4159 +
4160 + u32 intsts = sdr_read32(MSDC_INT);
4161 + u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
4162 +
4163 + sdr_write32(MSDC_INT, intsts); /* clear interrupts */
4164 + /* MSG will cause fatal error */
4165 +
4166 + /* card change interrupt */
4167 + if (intsts & MSDC_INT_CDSC){
4168 + if (mtk_sw_poll)
4169 + return IRQ_HANDLED;
4170 + IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
4171 +#if 0 /* ---/+++ by chhung: fix slot mechanical bounce issue */
4172 + tasklet_hi_schedule(&host->card_tasklet);
4173 +#else
4174 + schedule_delayed_work(&host->card_delaywork, HZ);
4175 +#endif
4176 + /* tuning when plug card ? */
4177 + }
4178 +
4179 + /* sdio interrupt */
4180 + if (intsts & MSDC_INT_SDIOIRQ){
4181 + IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
4182 + //mmc_signal_sdio_irq(host->mmc);
4183 + }
4184 +
4185 + /* transfer complete interrupt */
4186 + if (data != NULL) {
4187 + if (inten & MSDC_INT_XFER_COMPL) {
4188 + data->bytes_xfered = host->dma.xfersz;
4189 + complete(&host->xfer_done);
4190 + }
4191 +
4192 + if (intsts & datsts) {
4193 + /* do basic reset, or stop command will sdc_busy */
4194 + msdc_reset();
4195 + msdc_clr_fifo();
4196 + msdc_clr_int();
4197 + atomic_set(&host->abort, 1); /* For PIO mode exit */
4198 +
4199 + if (intsts & MSDC_INT_DATTMO){
4200 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
4201 + data->error = (unsigned int)-ETIMEDOUT;
4202 + }
4203 + else if (intsts & MSDC_INT_DATCRCERR){
4204 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
4205 + data->error = (unsigned int)-EIO;
4206 + }
4207 +
4208 + //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
4209 + if (host->dma_xfer) {
4210 + complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
4211 + } /* PIO mode can't do complete, because not init */
4212 + }
4213 + }
4214 +
4215 + /* command interrupts */
4216 + if ((cmd != NULL) && (intsts & cmdsts)) {
4217 + if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
4218 + (intsts & MSDC_INT_ACMD19_DONE)) {
4219 + u32 *rsp = &cmd->resp[0];
4220 +
4221 + switch (host->cmd_rsp) {
4222 + case RESP_NONE:
4223 + break;
4224 + case RESP_R2:
4225 + *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
4226 + *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
4227 + break;
4228 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
4229 + if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
4230 + *rsp = sdr_read32(SDC_ACMD_RESP);
4231 + } else {
4232 + *rsp = sdr_read32(SDC_RESP0);
4233 + }
4234 + break;
4235 + }
4236 + } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
4237 + if(intsts & MSDC_INT_ACMDCRCERR){
4238 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR",cmd->opcode);
4239 + }
4240 + else {
4241 + IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR",cmd->opcode);
4242 + }
4243 + cmd->error = (unsigned int)-EIO;
4244 + } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
4245 + if(intsts & MSDC_INT_ACMDTMO){
4246 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO",cmd->opcode);
4247 + }
4248 + else {
4249 + IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO",cmd->opcode);
4250 + }
4251 + cmd->error = (unsigned int)-ETIMEDOUT;
4252 + msdc_reset();
4253 + msdc_clr_fifo();
4254 + msdc_clr_int();
4255 + }
4256 + complete(&host->cmd_done);
4257 + }
4258 +
4259 + /* mmc irq interrupts */
4260 + if (intsts & MSDC_INT_MMCIRQ) {
4261 + printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
4262 + }
4263 +
4264 +#ifdef MT6575_SD_DEBUG
4265 + {
4266 + msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
4267 + N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
4268 + intsts,
4269 + int_reg->mmcirq,
4270 + int_reg->cdsc,
4271 + int_reg->atocmdrdy,
4272 + int_reg->atocmdtmo,
4273 + int_reg->atocmdcrc,
4274 + int_reg->atocmd19done);
4275 + N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
4276 + intsts,
4277 + int_reg->sdioirq,
4278 + int_reg->cmdrdy,
4279 + int_reg->cmdtmo,
4280 + int_reg->rspcrc,
4281 + int_reg->csta);
4282 + N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
4283 + intsts,
4284 + int_reg->xfercomp,
4285 + int_reg->dxferdone,
4286 + int_reg->dattmo,
4287 + int_reg->datcrc,
4288 + int_reg->dmaqempty);
4289 +
4290 + }
4291 +#endif
4292 +
4293 + return IRQ_HANDLED;
4294 +}
4295 +
4296 +/*--------------------------------------------------------------------------*/
4297 +/* platform_driver members */
4298 +/*--------------------------------------------------------------------------*/
4299 +/* called by msdc_drv_probe/remove */
4300 +static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
4301 +{
4302 + struct msdc_hw *hw = host->hw;
4303 + u32 base = host->base;
4304 +
4305 + /* for sdio, not set */
4306 + if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
4307 + /* Pull down card detection pin since it is not avaiable */
4308 + /*
4309 + if (hw->config_gpio_pin)
4310 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4311 + */
4312 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4313 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4314 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4315 + return;
4316 + }
4317 +
4318 + N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
4319 +
4320 + if (enable) {
4321 + if (hw->enable_cd_eirq) { /* not set, never enter */
4322 + hw->enable_cd_eirq();
4323 + } else {
4324 + /* card detection circuit relies on the core power so that the core power
4325 + * shouldn't be turned off. Here adds a reference count to keep
4326 + * the core power alive.
4327 + */
4328 + //msdc_vcore_on(host); //did in msdc_init_hw()
4329 +
4330 + if (hw->config_gpio_pin) /* NULL */
4331 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
4332 +
4333 + sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
4334 + sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
4335 + sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4336 + sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
4337 + }
4338 + } else {
4339 + if (hw->disable_cd_eirq) {
4340 + hw->disable_cd_eirq();
4341 + } else {
4342 + if (hw->config_gpio_pin) /* NULL */
4343 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4344 +
4345 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4346 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4347 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4348 +
4349 + /* Here decreases a reference count to core power since card
4350 + * detection circuit is shutdown.
4351 + */
4352 + //msdc_vcore_off(host);
4353 + }
4354 + }
4355 +}
4356 +
4357 +/* called by msdc_drv_probe */
4358 +static void msdc_init_hw(struct msdc_host *host)
4359 +{
4360 + u32 base = host->base;
4361 + struct msdc_hw *hw = host->hw;
4362 +
4363 +#ifdef MT6575_SD_DEBUG
4364 + msdc_reg[host->id] = (struct msdc_regs *)host->base;
4365 +#endif
4366 +
4367 + /* Power on */
4368 +#if 0 /* --- by chhung */
4369 + msdc_vcore_on(host);
4370 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
4371 + msdc_select_clksrc(host, hw->clk_src);
4372 + enable_clock(PERI_MSDC0_PDN + host->id, "SD");
4373 + msdc_vdd_on(host);
4374 +#endif /* end of --- */
4375 + /* Configure to MMC/SD mode */
4376 + sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
4377 +
4378 + /* Reset */
4379 + msdc_reset();
4380 + msdc_clr_fifo();
4381 +
4382 + /* Disable card detection */
4383 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4384 +
4385 + /* Disable and clear all interrupts */
4386 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4387 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4388 +
4389 +#if 1
4390 + /* reset tuning parameter */
4391 + sdr_write32(MSDC_PAD_CTL0, 0x00090000);
4392 + sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
4393 + sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
4394 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4395 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4396 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4397 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4398 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4399 + sdr_write32(MSDC_IOCON, 0x00000000);
4400 +#if 0 // use MT7620 default value: 0x403c004f
4401 + sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
4402 +#endif
4403 +
4404 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
4405 + if (host->id == 1) {
4406 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
4407 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
4408 +
4409 + /* internal clock: latch read data */
4410 + sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
4411 + }
4412 + }
4413 +#endif
4414 +
4415 + /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
4416 + pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
4417 + set when kernel driver wants to use SDIO bus interrupt */
4418 + /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
4419 + sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
4420 +
4421 + /* disable detect SDIO device interupt function */
4422 + sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
4423 +
4424 + /* eneable SMT for glitch filter */
4425 + sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
4426 + sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
4427 + sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
4428 +
4429 +#if 1
4430 + /* set clk, cmd, dat pad driving */
4431 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
4432 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
4433 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
4434 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
4435 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
4436 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
4437 +#else
4438 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
4439 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
4440 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
4441 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
4442 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
4443 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
4444 +#endif
4445 +
4446 + /* set sampling edge */
4447 +
4448 + /* write crc timeout detection */
4449 + sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
4450 +
4451 + /* Configure to default data timeout */
4452 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
4453 +
4454 + msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
4455 +
4456 + N_MSG(FUC, "init hardware done!");
4457 +}
4458 +
4459 +/* called by msdc_drv_remove */
4460 +static void msdc_deinit_hw(struct msdc_host *host)
4461 +{
4462 + u32 base = host->base;
4463 +
4464 + /* Disable and clear all interrupts */
4465 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4466 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4467 +
4468 + /* Disable card detection */
4469 + msdc_enable_cd_irq(host, 0);
4470 + // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
4471 +}
4472 +
4473 +/* init gpd and bd list in msdc_drv_probe */
4474 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
4475 +{
4476 + gpd_t *gpd = dma->gpd;
4477 + bd_t *bd = dma->bd;
4478 + bd_t *ptr, *prev;
4479 +
4480 + /* we just support one gpd */
4481 + int bdlen = MAX_BD_PER_GPD;
4482 +
4483 + /* init the 2 gpd */
4484 + memset(gpd, 0, sizeof(gpd_t) * 2);
4485 + //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
4486 + //gpd->next = (dma->gpd_addr + 1); /* bug */
4487 + gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
4488 +
4489 + //gpd->intr = 0;
4490 + gpd->bdp = 1; /* hwo, cs, bd pointer */
4491 + //gpd->ptr = (void*)virt_to_phys(bd);
4492 + gpd->ptr = (void *)dma->bd_addr; /* physical address */
4493 +
4494 + memset(bd, 0, sizeof(bd_t) * bdlen);
4495 + ptr = bd + bdlen - 1;
4496 + //ptr->eol = 1; /* 0 or 1 [Fix me]*/
4497 + //ptr->next = 0;
4498 +
4499 + while (ptr != bd) {
4500 + prev = ptr - 1;
4501 + prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
4502 + ptr = prev;
4503 + }
4504 +}
4505 +
4506 +static int msdc_drv_probe(struct platform_device *pdev)
4507 +{
4508 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4509 + __iomem void *base;
4510 + struct mmc_host *mmc;
4511 + struct resource *mem;
4512 + struct msdc_host *host;
4513 + struct msdc_hw *hw;
4514 + int ret, irq;
4515 +
4516 + pdev->dev.platform_data = &msdc0_hw;
4517 +
4518 + if (of_property_read_bool(pdev->dev.of_node, "mtk,wp-en"))
4519 + msdc0_hw.flags |= MSDC_WP_PIN_EN;
4520 +
4521 + /* Allocate MMC host for this device */
4522 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
4523 + if (!mmc) return -ENOMEM;
4524 +
4525 + hw = (struct msdc_hw*)pdev->dev.platform_data;
4526 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4527 + irq = platform_get_irq(pdev, 0);
4528 +
4529 + //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
4530 +
4531 + base = devm_ioremap_resource(&pdev->dev, res);
4532 + if (IS_ERR(base))
4533 + return PTR_ERR(base);
4534 +
4535 + /* Set host parameters to mmc */
4536 + mmc->ops = &mt_msdc_ops;
4537 + mmc->f_min = HOST_MIN_MCLK;
4538 + mmc->f_max = HOST_MAX_MCLK;
4539 + mmc->ocr_avail = MSDC_OCR_AVAIL;
4540 +
4541 + /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
4542 + For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
4543 + if (hw->flags & MSDC_HIGHSPEED) {
4544 + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
4545 + }
4546 + if (hw->data_pins == 4) { /* current data_pins are all 4*/
4547 + mmc->caps |= MMC_CAP_4_BIT_DATA;
4548 + } else if (hw->data_pins == 8) {
4549 + mmc->caps |= MMC_CAP_8_BIT_DATA;
4550 + }
4551 + if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
4552 + mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
4553 +
4554 + cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high");
4555 + mtk_sw_poll = of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll");
4556 +
4557 + if (mtk_sw_poll)
4558 + mmc->caps |= MMC_CAP_NEEDS_POLL;
4559 +
4560 + /* MMC core transfer sizes tunable parameters */
4561 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
4562 + mmc->max_segs = MAX_HW_SGMTS;
4563 +#else
4564 + mmc->max_hw_segs = MAX_HW_SGMTS;
4565 + mmc->max_phys_segs = MAX_PHY_SGMTS;
4566 +#endif
4567 + mmc->max_seg_size = MAX_SGMT_SZ;
4568 + mmc->max_blk_size = HOST_MAX_BLKSZ;
4569 + mmc->max_req_size = MAX_REQ_SZ;
4570 + mmc->max_blk_count = mmc->max_req_size;
4571 +
4572 + host = mmc_priv(mmc);
4573 + host->hw = hw;
4574 + host->mmc = mmc;
4575 + host->id = pdev->id;
4576 + host->error = 0;
4577 + host->irq = irq;
4578 + host->base = (unsigned long) base;
4579 + host->mclk = 0; /* mclk: the request clock of mmc sub-system */
4580 + host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
4581 + host->sclk = 0; /* sclk: the really clock after divition */
4582 + host->pm_state = PMSG_RESUME;
4583 + host->suspend = 0;
4584 + host->core_clkon = 0;
4585 + host->card_clkon = 0;
4586 + host->core_power = 0;
4587 + host->power_mode = MMC_POWER_OFF;
4588 +// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
4589 + host->timeout_ns = 0;
4590 + host->timeout_clks = DEFAULT_DTOC * 65536;
4591 +
4592 + host->mrq = NULL;
4593 + //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
4594 +
4595 + host->dma.used_gpd = 0;
4596 + host->dma.used_bd = 0;
4597 +
4598 + /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
4599 + host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
4600 + host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
4601 + BUG_ON((!host->dma.gpd) || (!host->dma.bd));
4602 + msdc_init_gpd_bd(host, &host->dma);
4603 + /*for emmc*/
4604 + msdc_6575_host[pdev->id] = host;
4605 +
4606 +#if 0
4607 + tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
4608 +#else
4609 + INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
4610 +#endif
4611 + spin_lock_init(&host->lock);
4612 + msdc_init_hw(host);
4613 +
4614 + if (ralink_soc == MT762X_SOC_MT7621AT)
4615 + ret = request_irq((unsigned int)irq, msdc_irq, 0, dev_name(&pdev->dev), host);
4616 + else
4617 + ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
4618 +
4619 + if (ret) goto release;
4620 + // mt65xx_irq_unmask(irq); /* --- by chhung */
4621 +
4622 + if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
4623 + if (hw->request_cd_eirq) { /* not set for MT6575 */
4624 + hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
4625 + }
4626 + }
4627 +
4628 + if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
4629 + hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
4630 +
4631 + if (hw->register_pm) {/* yes for sdio */
4632 +#ifdef CONFIG_PM
4633 + hw->register_pm(msdc_pm, (void*)host); /* combo_sdio_register_pm() */
4634 +#endif
4635 + if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
4636 + ERR_MSG("MSDC_SYS_SUSPEND and register_pm both set");
4637 + }
4638 + //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
4639 + }
4640 +
4641 + platform_set_drvdata(pdev, mmc);
4642 +
4643 + ret = mmc_add_host(mmc);
4644 + if (ret) goto free_irq;
4645 +
4646 + /* Config card detection pin and enable interrupts */
4647 + if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
4648 + msdc_enable_cd_irq(host, 1);
4649 + } else {
4650 + msdc_enable_cd_irq(host, 0);
4651 + }
4652 +
4653 + return 0;
4654 +
4655 +free_irq:
4656 + free_irq(irq, host);
4657 +release:
4658 + platform_set_drvdata(pdev, NULL);
4659 + msdc_deinit_hw(host);
4660 +
4661 +#if 0
4662 + tasklet_kill(&host->card_tasklet);
4663 +#else
4664 + cancel_delayed_work_sync(&host->card_delaywork);
4665 +#endif
4666 +
4667 + if (mem)
4668 + release_mem_region(mem->start, mem->end - mem->start + 1);
4669 +
4670 + mmc_free_host(mmc);
4671 +
4672 + return ret;
4673 +}
4674 +
4675 +/* 4 device share one driver, using "drvdata" to show difference */
4676 +static int msdc_drv_remove(struct platform_device *pdev)
4677 +{
4678 + struct mmc_host *mmc;
4679 + struct msdc_host *host;
4680 + struct resource *mem;
4681 +
4682 + mmc = platform_get_drvdata(pdev);
4683 + BUG_ON(!mmc);
4684 +
4685 + host = mmc_priv(mmc);
4686 + BUG_ON(!host);
4687 +
4688 + ERR_MSG("removed !!!");
4689 +
4690 + platform_set_drvdata(pdev, NULL);
4691 + mmc_remove_host(host->mmc);
4692 + msdc_deinit_hw(host);
4693 +
4694 +#if 0
4695 + tasklet_kill(&host->card_tasklet);
4696 +#else
4697 + cancel_delayed_work_sync(&host->card_delaywork);
4698 +#endif
4699 + free_irq(host->irq, host);
4700 +
4701 + dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
4702 + dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
4703 +
4704 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4705 +
4706 + if (mem)
4707 + release_mem_region(mem->start, mem->end - mem->start + 1);
4708 +
4709 + mmc_free_host(host->mmc);
4710 +
4711 + return 0;
4712 +}
4713 +
4714 +/* Fix me: Power Flow */
4715 +#ifdef CONFIG_PM
4716 +static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
4717 +{
4718 + int ret = 0;
4719 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4720 + struct msdc_host *host = mmc_priv(mmc);
4721 +
4722 + if (mmc && state.event == PM_EVENT_SUSPEND && (host->hw->flags & MSDC_SYS_SUSPEND)) { /* will set for card */
4723 + msdc_pm(state, (void*)host);
4724 + }
4725 +
4726 + return ret;
4727 +}
4728 +
4729 +static int msdc_drv_resume(struct platform_device *pdev)
4730 +{
4731 + int ret = 0;
4732 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4733 + struct msdc_host *host = mmc_priv(mmc);
4734 + struct pm_message state;
4735 +
4736 + state.event = PM_EVENT_RESUME;
4737 + if (mmc && (host->hw->flags & MSDC_SYS_SUSPEND)) {/* will set for card */
4738 + msdc_pm(state, (void*)host);
4739 + }
4740 +
4741 + /* This mean WIFI not controller by PM */
4742 +
4743 + return ret;
4744 +}
4745 +#endif
4746 +
4747 +static const struct of_device_id mt7620_sdhci_match[] = {
4748 + { .compatible = "ralink,mt7620-sdhci" },
4749 + {},
4750 +};
4751 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
4752 +
4753 +static struct platform_driver mt_msdc_driver = {
4754 + .probe = msdc_drv_probe,
4755 + .remove = msdc_drv_remove,
4756 +#ifdef CONFIG_PM
4757 + .suspend = msdc_drv_suspend,
4758 + .resume = msdc_drv_resume,
4759 +#endif
4760 + .driver = {
4761 + .name = DRV_NAME,
4762 + .of_match_table = mt7620_sdhci_match,
4763 + },
4764 +};
4765 +
4766 +/*--------------------------------------------------------------------------*/
4767 +/* module init/exit */
4768 +/*--------------------------------------------------------------------------*/
4769 +static int __init mt_msdc_init(void)
4770 +{
4771 + int ret;
4772 +/* +++ by chhung */
4773 + u32 reg;
4774 +
4775 +#if defined (CONFIG_MTD_ANY_RALINK)
4776 + extern int ra_check_flash_type(void);
4777 + if(ra_check_flash_type() == 2) { /* NAND */
4778 + printk("%s: !!!!! SDXC Module Initialize Fail !!!!!", __func__);
4779 + return 0;
4780 + }
4781 +#endif
4782 + printk("MTK MSDC device init.\n");
4783 + mtk_sd_device.dev.platform_data = &msdc0_hw;
4784 +if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
4785 +//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
4786 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<18);
4787 +//#if defined (CONFIG_RALINK_MT7620)
4788 + if (ralink_soc == MT762X_SOC_MT7620A)
4789 + reg |= 0x1<<18;
4790 +//#endif
4791 +} else {
4792 +//#elif defined (CONFIG_RALINK_MT7628)
4793 + /* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
4794 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c));
4795 + reg |= 0x1e << 16;
4796 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c), reg);
4797 +
4798 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<10);
4799 +#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
4800 + reg |= 0x3<<26 | 0x3<<28 | 0x3<<30;
4801 + msdc0_hw.data_pins = 8,
4802 +#endif
4803 +//#endif
4804 +}
4805 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60), reg);
4806 + //platform_device_register(&mtk_sd_device);
4807 +/* end of +++ */
4808 +
4809 + ret = platform_driver_register(&mt_msdc_driver);
4810 + if (ret) {
4811 + printk(KERN_ERR DRV_NAME ": Can't register driver");
4812 + return ret;
4813 + }
4814 + printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
4815 +
4816 +#if defined (MT6575_SD_DEBUG)
4817 + msdc_debug_proc_init();
4818 +#endif
4819 + return 0;
4820 +}
4821 +
4822 +static void __exit mt_msdc_exit(void)
4823 +{
4824 +// platform_device_unregister(&mtk_sd_device);
4825 + platform_driver_unregister(&mt_msdc_driver);
4826 +}
4827 +
4828 +module_init(mt_msdc_init);
4829 +module_exit(mt_msdc_exit);
4830 +MODULE_LICENSE("GPL");
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