target/linux/ramips/patches-4.9/101-mt7621-timer.patch

   1 --- a/arch/mips/ralink/mt7621.c
   2 +++ b/arch/mips/ralink/mt7621.c
   3 @@ -18,6 +18,7 @@
   4  #include <asm/mach-ralink/ralink_regs.h>
   5  #include <asm/mach-ralink/mt7621.h>
   6  #include <asm/mips-boards/launch.h>
   7 +#include <asm/delay.h>
   8
   9  #include <pinmux.h>
  10
  11 @@ -179,6 +180,58 @@ bool plat_cpu_core_present(int core)
  12         return true;
  13  }
  14
  15 +#define LPS_PREC 8
  16 +/*
  17 +*  Re-calibration lpj(loop-per-jiffy).
  18 +*  (derived from kernel/calibrate.c)
  19 +*/
  20 +static int udelay_recal(void)
  21 +{
  22 +       unsigned int i, lpj = 0;
  23 +       unsigned long ticks, loopbit;
  24 +       int lps_precision = LPS_PREC;
  25 +
  26 +       lpj = (1<<12);
  27 +
  28 +       while ((lpj <<= 1) != 0) {
  29 +               /* wait for "start of" clock tick */
  30 +               ticks = jiffies;
  31 +               while (ticks == jiffies)
  32 +                       /* nothing */;
  33 +
  34 +               /* Go .. */
  35 +               ticks = jiffies;
  36 +               __delay(lpj);
  37 +               ticks = jiffies - ticks;
  38 +               if (ticks)
  39 +                       break;
  40 +       }
  41 +
  42 +       /*
  43 +        * Do a binary approximation to get lpj set to
  44 +        * equal one clock (up to lps_precision bits)
  45 +        */
  46 +       lpj >>= 1;
  47 +       loopbit = lpj;
  48 +       while (lps_precision-- && (loopbit >>= 1)) {
  49 +               lpj |= loopbit;
  50 +               ticks = jiffies;
  51 +               while (ticks == jiffies)
  52 +                       /* nothing */;
  53 +               ticks = jiffies;
  54 +               __delay(lpj);
  55 +               if (jiffies != ticks)   /* longer than 1 tick */
  56 +                       lpj &= ~loopbit;
  57 +       }
  58 +       printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
  59 +
  60 +       for(i=0; i< NR_CPUS; i++)
  61 +               cpu_data[i].udelay_val = lpj;
  62 +
  63 +       return 0;
  64 +}
  65 +device_initcall(udelay_recal);
  66 +
  67  void prom_soc_init(struct ralink_soc_info *soc_info)
  68  {
  69         void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
  70 --- a/arch/mips/ralink/Kconfig
  71 +++ b/arch/mips/ralink/Kconfig
  72 @@ -57,6 +57,7 @@ choice
  73                 select CLKSRC_MIPS_GIC
  74                 select HW_HAS_PCI
  75                 select WEAK_REORDERING_BEYOND_LLSC
  76 +               select GENERIC_CLOCKEVENTS_BROADCAST
  77  endchoice
  78
  79  choice
  80 --- a/arch/mips/ralink/timer-gic.c
  81 +++ b/arch/mips/ralink/timer-gic.c
  82 @@ -12,6 +12,7 @@
  83  #include <linux/of.h>
  84  #include <linux/clk-provider.h>
  85  #include <linux/clocksource.h>
  86 +#include <asm/time.h>
  87
  88  #include "common.h"
  89
  90 @@ -19,6 +20,8 @@ void __init plat_time_init(void)
  91  {
  92         ralink_of_remap();
  93
  94 +       mips_hpt_frequency = 880000000 / 2;
  95 +
  96         of_clk_init(NULL);
  97         clocksource_probe();
  98  }