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ramips: mt7620: Add support for the devolo WiFi Repeater ac (MT 2767, 2779)
[openwrt/openwrt.git] / target / linux / realtek / files-6.6 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/etherdevice.h>
5 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7
8 #include "rtl83xx.h"
9
10 extern struct rtl83xx_soc_info soc_info;
11
12 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
13 {
14 mutex_lock(&priv->reg_mutex);
15
16 /* Enable statistics module: all counters plus debug.
17 * On RTL839x all counters are enabled by default
18 */
19 if (priv->family_id == RTL8380_FAMILY_ID)
20 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
21
22 /* Reset statistics counters */
23 sw_w32_mask(0, 1, priv->r->stat_rst);
24
25 mutex_unlock(&priv->reg_mutex);
26 }
27
28 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
29 {
30 u64 v = 0;
31
32 msleep(1000);
33 /* Enable all ports with a PHY, including the SFP-ports */
34 for (int i = 0; i < priv->cpu_port; i++) {
35 if (priv->ports[i].phy)
36 v |= BIT_ULL(i);
37 }
38
39 pr_info("%s: %16llx\n", __func__, v);
40 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
41
42 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
43 if (priv->family_id == RTL8390_FAMILY_ID)
44 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
45 else if(priv->family_id == RTL9300_FAMILY_ID)
46 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
47 }
48
49 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
50 MIB_DESC(2, 0xf8, "ifInOctets"),
51 MIB_DESC(2, 0xf0, "ifOutOctets"),
52 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
53 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
54 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
55 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
56 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
57 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
58 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
59 MIB_DESC(1, 0xd0, "ifOutDiscards"),
60 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
61 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
62 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
63 MIB_DESC(1, 0xc0, ".3LateCollisions"),
64 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
65 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
66 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
67 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
68 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
69 MIB_DESC(1, 0xa8, "DropEvents"),
70 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
71 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
72 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
73 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
74 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
75 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
76 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
77 MIB_DESC(1, 0x88, "rx_OversizePkts"),
78 MIB_DESC(1, 0x84, "Fragments"),
79 MIB_DESC(1, 0x80, "Jabbers"),
80 MIB_DESC(1, 0x7c, "Collisions"),
81 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
82 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
83 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
85 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
87 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
89 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
91 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
92 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
93 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
95 MIB_DESC(1, 0x40, "rxMacDiscards")
96 };
97
98
99 /* DSA callbacks */
100
101
102 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
103 int port,
104 enum dsa_tag_protocol mprot)
105 {
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
108 */
109 return DSA_TAG_PROTO_TRAILER;
110 }
111
112 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
113 int port, int pvid)
114 {
115 /* Set both inner and outer PVID of the port */
116 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
117 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
118 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
119 PBVLAN_MODE_UNTAG_AND_PRITAG);
120 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
121 PBVLAN_MODE_UNTAG_AND_PRITAG);
122
123 priv->ports[port].pvid = pvid;
124 }
125
126 /* Initialize all VLANS */
127 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
128 {
129 struct rtl838x_vlan_info info;
130
131 pr_info("In %s\n", __func__);
132
133 priv->r->vlan_profile_setup(0);
134 priv->r->vlan_profile_setup(1);
135 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
136 priv->r->vlan_profile_dump(0);
137
138 info.fid = 0; /* Default Forwarding ID / MSTI */
139 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
140 info.hash_mc_fid = false; /* Do the same for Multicast packets */
141 info.profile_id = 0; /* Use default Vlan Profile 0 */
142 info.tagged_ports = 0; /* Initially no port members */
143 if (priv->family_id == RTL9310_FAMILY_ID) {
144 info.if_id = 0;
145 info.multicast_grp_mask = 0;
146 info.l2_tunnel_list_id = -1;
147 }
148
149 /* Initialize normal VLANs 1-4095 */
150 for (int i = 1; i < MAX_VLANS; i ++)
151 priv->r->vlan_set_tagged(i, &info);
152
153 /*
154 * Initialize the special VLAN 0 and reset PVIDs. The CPU port PVID
155 * is applied to packets from the CPU for untagged destinations,
156 * regardless if the actual ingress VID. Any port with untagged
157 * egress VLAN(s) must therefore be a member of VLAN 0 to support
158 * CPU port as ingress when VLAN filtering is enabled.
159 */
160 for (int i = 0; i <= priv->cpu_port; i++) {
161 rtl83xx_vlan_set_pvid(priv, i, 0);
162 info.tagged_ports |= BIT_ULL(i);
163 }
164 priv->r->vlan_set_tagged(0, &info);
165
166 /* Set forwarding action based on inner VLAN tag */
167 for (int i = 0; i < priv->cpu_port; i++)
168 priv->r->vlan_fwd_on_inner(i, true);
169 }
170
171 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
172 {
173 for (int i = 0; i < priv->cpu_port; i++)
174 priv->r->set_receive_management_action(i, BPDU, TRAP2CPU);
175 }
176
177 static void rtl83xx_setup_lldp_traps(struct rtl838x_switch_priv *priv)
178 {
179 for (int i = 0; i < priv->cpu_port; i++)
180 priv->r->set_receive_management_action(i, LLDP, TRAP2CPU);
181 }
182
183 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
184 int port, bool enable)
185 {
186 int shift = SALRN_PORT_SHIFT(port);
187 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
188
189 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
190 priv->r->l2_port_new_salrn(port));
191 }
192
193 static int rtl83xx_setup(struct dsa_switch *ds)
194 {
195 struct rtl838x_switch_priv *priv = ds->priv;
196
197 pr_debug("%s called\n", __func__);
198
199 /* Disable MAC polling the PHY so that we can start configuration */
200 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
201
202 for (int i = 0; i < ds->num_ports; i++)
203 priv->ports[i].enable = false;
204 priv->ports[priv->cpu_port].enable = true;
205
206 /* Configure ports so they are disabled by default, but once enabled
207 * they will work in isolated mode (only traffic between port and CPU).
208 */
209 for (int i = 0; i < priv->cpu_port; i++) {
210 if (priv->ports[i].phy) {
211 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
212 priv->r->traffic_set(i, BIT_ULL(i));
213 }
214 }
215 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
216
217 /* For standalone ports, forward packets even if a static fdb
218 * entry for the source address exists on another port.
219 */
220 if (priv->r->set_static_move_action) {
221 for (int i = 0; i <= priv->cpu_port; i++)
222 priv->r->set_static_move_action(i, true);
223 }
224
225 if (priv->family_id == RTL8380_FAMILY_ID)
226 rtl838x_print_matrix();
227 else
228 rtl839x_print_matrix();
229
230 rtl83xx_init_stats(priv);
231
232 rtl83xx_vlan_setup(priv);
233
234 rtl83xx_setup_bpdu_traps(priv);
235 rtl83xx_setup_lldp_traps(priv);
236
237 ds->configure_vlan_while_not_filtering = true;
238
239 priv->r->l2_learning_setup();
240
241 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
242 ds->assisted_learning_on_cpu_port = true;
243
244 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
245 * 0: FWD, 1: DROP, 2: TRAP2CPU
246 */
247 if (priv->family_id == RTL8380_FAMILY_ID)
248 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
249 else
250 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
251
252 /* Enable MAC Polling PHY again */
253 rtl83xx_enable_phy_polling(priv);
254 pr_debug("Please wait until PHY is settled\n");
255 msleep(1000);
256 priv->r->pie_init(priv);
257
258 return 0;
259 }
260
261 static int rtl93xx_setup(struct dsa_switch *ds)
262 {
263 struct rtl838x_switch_priv *priv = ds->priv;
264
265 pr_info("%s called\n", __func__);
266
267 /* Disable MAC polling the PHY so that we can start configuration */
268 if (priv->family_id == RTL9300_FAMILY_ID)
269 sw_w32(0, RTL930X_SMI_POLL_CTRL);
270
271 if (priv->family_id == RTL9310_FAMILY_ID) {
272 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
273 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
274 }
275
276 /* Disable all ports except CPU port */
277 for (int i = 0; i < ds->num_ports; i++)
278 priv->ports[i].enable = false;
279 priv->ports[priv->cpu_port].enable = true;
280
281 /* Configure ports so they are disabled by default, but once enabled
282 * they will work in isolated mode (only traffic between port and CPU).
283 */
284 for (int i = 0; i < priv->cpu_port; i++) {
285 if (priv->ports[i].phy) {
286 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
287 priv->r->traffic_set(i, BIT_ULL(i));
288 }
289 }
290 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
291
292 rtl930x_print_matrix();
293
294 /* TODO: Initialize statistics */
295
296 rtl83xx_vlan_setup(priv);
297
298 ds->configure_vlan_while_not_filtering = true;
299
300 priv->r->l2_learning_setup();
301
302 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
303 ds->assisted_learning_on_cpu_port = true;
304
305 rtl83xx_enable_phy_polling(priv);
306
307 priv->r->pie_init(priv);
308
309 priv->r->led_init(priv);
310
311 return 0;
312 }
313
314 static int rtl93xx_get_sds(struct phy_device *phydev)
315 {
316 struct device *dev = &phydev->mdio.dev;
317 struct device_node *dn;
318 u32 sds_num;
319
320 if (!dev)
321 return -1;
322 if (dev->of_node) {
323 dn = dev->of_node;
324 if (of_property_read_u32(dn, "sds", &sds_num))
325 sds_num = -1;
326 } else {
327 dev_err(dev, "No DT node.\n");
328 return -1;
329 }
330
331 return sds_num;
332 }
333
334 static int rtl83xx_pcs_validate(struct phylink_pcs *pcs,
335 unsigned long *supported,
336 const struct phylink_link_state *state)
337 {
338 struct rtl838x_pcs *rtpcs = container_of(pcs, struct rtl838x_pcs, pcs);
339 struct rtl838x_switch_priv *priv = rtpcs->priv;
340 int port = rtpcs->port;
341 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
342
343 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
344
345 if (!phy_interface_mode_is_rgmii(state->interface) &&
346 state->interface != PHY_INTERFACE_MODE_NA &&
347 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
348 state->interface != PHY_INTERFACE_MODE_MII &&
349 state->interface != PHY_INTERFACE_MODE_REVMII &&
350 state->interface != PHY_INTERFACE_MODE_GMII &&
351 state->interface != PHY_INTERFACE_MODE_QSGMII &&
352 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
353 state->interface != PHY_INTERFACE_MODE_SGMII) {
354 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
355 dev_err(priv->ds->dev,
356 "Unsupported interface: %d for port %d\n",
357 state->interface, port);
358 return -EINVAL;
359 }
360
361 /* Allow all the expected bits */
362 phylink_set(mask, Autoneg);
363 phylink_set_port_modes(mask);
364 phylink_set(mask, Pause);
365 phylink_set(mask, Asym_Pause);
366
367 /* With the exclusion of MII and Reverse MII, we support Gigabit,
368 * including Half duplex
369 */
370 if (state->interface != PHY_INTERFACE_MODE_MII &&
371 state->interface != PHY_INTERFACE_MODE_REVMII) {
372 phylink_set(mask, 1000baseT_Full);
373 phylink_set(mask, 1000baseT_Half);
374 }
375
376 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
377 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
378 phylink_set(mask, 1000baseX_Full);
379
380 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
381 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
382 phylink_set(mask, 1000baseX_Full);
383
384 phylink_set(mask, 10baseT_Half);
385 phylink_set(mask, 10baseT_Full);
386 phylink_set(mask, 100baseT_Half);
387 phylink_set(mask, 100baseT_Full);
388
389 bitmap_and(supported, supported, mask,
390 __ETHTOOL_LINK_MODE_MASK_NBITS);
391
392 return 0;
393 }
394
395 static int rtl93xx_pcs_validate(struct phylink_pcs *pcs,
396 unsigned long *supported,
397 const struct phylink_link_state *state)
398 {
399 struct rtl838x_pcs *rtpcs = container_of(pcs, struct rtl838x_pcs, pcs);
400 struct rtl838x_switch_priv *priv = rtpcs->priv;
401 int port = rtpcs->port;
402 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
403
404 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
405 phy_modes(state->interface));
406
407 if (!phy_interface_mode_is_rgmii(state->interface) &&
408 state->interface != PHY_INTERFACE_MODE_NA &&
409 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
410 state->interface != PHY_INTERFACE_MODE_MII &&
411 state->interface != PHY_INTERFACE_MODE_REVMII &&
412 state->interface != PHY_INTERFACE_MODE_GMII &&
413 state->interface != PHY_INTERFACE_MODE_QSGMII &&
414 state->interface != PHY_INTERFACE_MODE_XGMII &&
415 state->interface != PHY_INTERFACE_MODE_HSGMII &&
416 state->interface != PHY_INTERFACE_MODE_10GBASER &&
417 state->interface != PHY_INTERFACE_MODE_10GKR &&
418 state->interface != PHY_INTERFACE_MODE_USXGMII &&
419 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
420 state->interface != PHY_INTERFACE_MODE_SGMII) {
421 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
422 dev_err(priv->ds->dev,
423 "Unsupported interface: %d for port %d\n",
424 state->interface, port);
425 return -EINVAL;
426 }
427
428 /* Allow all the expected bits */
429 phylink_set(mask, Autoneg);
430 phylink_set_port_modes(mask);
431 phylink_set(mask, Pause);
432 phylink_set(mask, Asym_Pause);
433
434 /* With the exclusion of MII and Reverse MII, we support Gigabit,
435 * including Half duplex
436 */
437 if (state->interface != PHY_INTERFACE_MODE_MII &&
438 state->interface != PHY_INTERFACE_MODE_REVMII) {
439 phylink_set(mask, 1000baseT_Full);
440 phylink_set(mask, 1000baseT_Half);
441 }
442
443 /* Internal phys of the RTL93xx family provide 10G */
444 if (priv->ports[port].phy_is_integrated &&
445 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
446 phylink_set(mask, 1000baseX_Full);
447 } else if (priv->ports[port].phy_is_integrated) {
448 phylink_set(mask, 1000baseX_Full);
449 phylink_set(mask, 10000baseKR_Full);
450 phylink_set(mask, 10000baseSR_Full);
451 phylink_set(mask, 10000baseCR_Full);
452 }
453 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
454 phylink_set(mask, 1000baseX_Full);
455 phylink_set(mask, 1000baseT_Full);
456 phylink_set(mask, 10000baseKR_Full);
457 phylink_set(mask, 10000baseT_Full);
458 phylink_set(mask, 10000baseSR_Full);
459 phylink_set(mask, 10000baseCR_Full);
460 }
461
462 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
463 phylink_set(mask, 2500baseT_Full);
464 phylink_set(mask, 5000baseT_Full);
465 phylink_set(mask, 10000baseT_Full);
466 }
467
468 phylink_set(mask, 10baseT_Half);
469 phylink_set(mask, 10baseT_Full);
470 phylink_set(mask, 100baseT_Half);
471 phylink_set(mask, 100baseT_Full);
472
473 bitmap_and(supported, supported, mask,
474 __ETHTOOL_LINK_MODE_MASK_NBITS);
475 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
476
477 return 0;
478 }
479
480 static void rtl83xx_pcs_get_state(struct phylink_pcs *pcs,
481 struct phylink_link_state *state)
482 {
483 struct rtl838x_pcs *rtpcs = container_of(pcs, struct rtl838x_pcs, pcs);
484 struct rtl838x_switch_priv *priv = rtpcs->priv;
485 int port = rtpcs->port;
486 u64 speed;
487 u64 link;
488
489 if (port < 0 || port > priv->cpu_port) {
490 state->link = false;
491 return;
492 }
493
494 state->link = 0;
495 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
496 if (link & BIT_ULL(port))
497 state->link = 1;
498 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
499
500 state->duplex = 0;
501 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
502 state->duplex = 1;
503
504 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
505 speed >>= (port % 16) << 1;
506 switch (speed & 0x3) {
507 case 0:
508 state->speed = SPEED_10;
509 break;
510 case 1:
511 state->speed = SPEED_100;
512 break;
513 case 2:
514 state->speed = SPEED_1000;
515 break;
516 case 3:
517 if (priv->family_id == RTL9300_FAMILY_ID
518 && (port == 24 || port == 26)) /* Internal serdes */
519 state->speed = SPEED_2500;
520 else
521 state->speed = SPEED_100; /* Is in fact 500Mbit */
522 }
523
524 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
525 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
526 state->pause |= MLO_PAUSE_RX;
527 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
528 state->pause |= MLO_PAUSE_TX;
529 }
530
531 static void rtl93xx_pcs_get_state(struct phylink_pcs *pcs,
532 struct phylink_link_state *state)
533 {
534 struct rtl838x_pcs *rtpcs = container_of(pcs, struct rtl838x_pcs, pcs);
535 struct rtl838x_switch_priv *priv = rtpcs->priv;
536 int port = rtpcs->port;
537 u64 speed;
538 u64 link;
539 u64 media;
540
541 if (port < 0 || port > priv->cpu_port) {
542 state->link = false;
543 return;
544 }
545
546 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
547 * state needs to be read twice in order to read a correct result.
548 * This would not be necessary for ports connected e.g. to RTL8218D
549 * PHYs.
550 */
551 state->link = 0;
552 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
553 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
554 if (link & BIT_ULL(port))
555 state->link = 1;
556
557 if (priv->family_id == RTL9310_FAMILY_ID)
558 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
559
560 if (priv->family_id == RTL9300_FAMILY_ID)
561 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
562
563 if (media & BIT_ULL(port))
564 state->link = 1;
565
566 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
567 link & BIT_ULL(port), media);
568
569 state->duplex = 0;
570 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
571 state->duplex = 1;
572
573 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
574 speed >>= (port % 8) << 2;
575 switch (speed & 0xf) {
576 case 0:
577 state->speed = SPEED_10;
578 break;
579 case 1:
580 state->speed = SPEED_100;
581 break;
582 case 2:
583 case 7:
584 state->speed = SPEED_1000;
585 break;
586 case 4:
587 state->speed = SPEED_10000;
588 break;
589 case 5:
590 case 8:
591 state->speed = SPEED_2500;
592 break;
593 case 6:
594 state->speed = SPEED_5000;
595 break;
596 default:
597 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
598 }
599
600 if (priv->family_id == RTL9310_FAMILY_ID
601 && (port >= 52 && port <= 55)) { /* Internal serdes */
602 state->speed = SPEED_10000;
603 state->link = 1;
604 state->duplex = 1;
605 }
606
607 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
608 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
609 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
610 state->pause |= MLO_PAUSE_RX;
611 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
612 state->pause |= MLO_PAUSE_TX;
613 }
614
615 static int rtl83xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
616 phy_interface_t interface,
617 const unsigned long *advertising,
618 bool permit_pause_to_mac)
619 {
620 return 0;
621 }
622
623 static void rtl83xx_pcs_an_restart(struct phylink_pcs *pcs)
624 {
625 /* No restart functionality existed before we migrated to pcs */
626 }
627
628 static struct phylink_pcs *rtl83xx_phylink_mac_select_pcs(struct dsa_switch *ds,
629 int port,
630 phy_interface_t interface)
631 {
632 struct rtl838x_switch_priv *priv = ds->priv;
633
634 return &priv->pcs[port].pcs;
635 }
636
637 static void rtl83xx_config_interface(int port, phy_interface_t interface)
638 {
639 u32 old, int_shift, sds_shift;
640
641 switch (port) {
642 case 24:
643 int_shift = 0;
644 sds_shift = 5;
645 break;
646 case 26:
647 int_shift = 3;
648 sds_shift = 0;
649 break;
650 default:
651 return;
652 }
653
654 old = sw_r32(RTL838X_SDS_MODE_SEL);
655 switch (interface) {
656 case PHY_INTERFACE_MODE_1000BASEX:
657 if ((old >> sds_shift & 0x1f) == 4)
658 return;
659 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
660 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
661 break;
662 case PHY_INTERFACE_MODE_SGMII:
663 if ((old >> sds_shift & 0x1f) == 2)
664 return;
665 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
666 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
667 break;
668 default:
669 return;
670 }
671 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
672 }
673
674 static void rtl83xx_phylink_get_caps(struct dsa_switch *ds, int port,
675 struct phylink_config *config)
676 {
677 /*
678 * This capability check will need some love. Depending on the model and the port
679 * different link modes are supported. For now just enable all required values
680 * so that we can make use of the ports.
681 */
682 __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces);
683 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
684 __set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces);
685 __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
686 __set_bit(PHY_INTERFACE_MODE_XGMII, config->supported_interfaces);
687 __set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces);
688 __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
689 __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);
690 }
691
692 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
693 unsigned int mode,
694 const struct phylink_link_state *state)
695 {
696 struct dsa_port *dp = dsa_to_port(ds, port);
697 struct rtl838x_switch_priv *priv = ds->priv;
698 u32 mcr;
699
700 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
701
702 /* currently only needed for RTL8380 */
703 if (priv->family_id != RTL8380_FAMILY_ID)
704 return;
705
706 if (dsa_port_is_cpu(dp)) {
707 /* allow CRC errors on CPU-port */
708 sw_w32_mask(0, 0x8, priv->r->mac_port_ctrl(port));
709 return;
710 }
711
712 mcr = sw_r32(priv->r->mac_force_mode_ctrl(port));
713 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
714 pr_debug("port %d PHY autonegotiates\n", port);
715 rtl83xx_config_interface(port, state->interface);
716 mcr |= RTL838X_NWAY_EN;
717 } else {
718 mcr &= ~RTL838X_NWAY_EN;
719 }
720 sw_w32(mcr, priv->r->mac_force_mode_ctrl(port));
721 }
722
723 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
724 unsigned int mode,
725 const struct phylink_link_state *state)
726 {
727 struct rtl838x_switch_priv *priv = ds->priv;
728 int sds_num;
729 u32 reg, band;
730
731 sds_num = priv->ports[port].sds_num;
732 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
733
734 switch (state->interface) {
735 case PHY_INTERFACE_MODE_HSGMII:
736 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
737 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
738 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
739 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
740 break;
741 case PHY_INTERFACE_MODE_1000BASEX:
742 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
743 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
744 break;
745 case PHY_INTERFACE_MODE_XGMII:
746 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
747 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
748 break;
749 case PHY_INTERFACE_MODE_10GBASER:
750 case PHY_INTERFACE_MODE_10GKR:
751 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
752 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
753 break;
754 case PHY_INTERFACE_MODE_USXGMII:
755 /* Translates to MII_USXGMII_10GSXGMII */
756 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
757 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
758 break;
759 case PHY_INTERFACE_MODE_SGMII:
760 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
761 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
762 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
763 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
764 break;
765 case PHY_INTERFACE_MODE_QSGMII:
766 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
767 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
768 break;
769 default:
770 pr_err("%s: unknown serdes mode: %s\n",
771 __func__, phy_modes(state->interface));
772 return;
773 }
774
775 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
776 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
777
778 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
779
780 reg &= ~(0xf << 12);
781 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
782
783 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
784
785 if (priv->lagmembers & BIT_ULL(port))
786 reg |= RTL931X_DUPLEX_MODE;
787
788 if (state->duplex == DUPLEX_FULL)
789 reg |= RTL931X_DUPLEX_MODE;
790
791 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
792
793 }
794
795 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
796 unsigned int mode,
797 const struct phylink_link_state *state)
798 {
799 struct rtl838x_switch_priv *priv = ds->priv;
800 int sds_num;
801 u32 reg;
802
803 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
804 port, mode, phy_modes(state->interface), state->speed, state->link);
805
806 /* Nothing to be done for the CPU-port */
807 if (port == priv->cpu_port)
808 return;
809
810 if (priv->family_id == RTL9310_FAMILY_ID)
811 return rtl931x_phylink_mac_config(ds, port, mode, state);
812
813 sds_num = priv->ports[port].sds_num;
814 pr_info("%s SDS is %d\n", __func__, sds_num);
815 if (sds_num >= 0 &&
816 (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
817 state->interface == PHY_INTERFACE_MODE_10GBASER))
818 rtl9300_serdes_setup(port, sds_num, state->interface);
819
820 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
821 reg &= ~(0xf << 3);
822
823 switch (state->speed) {
824 case SPEED_10000:
825 reg |= 4 << 3;
826 break;
827 case SPEED_5000:
828 reg |= 6 << 3;
829 break;
830 case SPEED_2500:
831 reg |= 5 << 3;
832 break;
833 case SPEED_1000:
834 reg |= 2 << 3;
835 break;
836 case SPEED_100:
837 reg |= 1 << 3;
838 break;
839 default:
840 /* Also covers 10M */
841 break;
842 }
843
844 if (state->link)
845 reg |= RTL930X_FORCE_LINK_EN;
846
847 if (priv->lagmembers & BIT_ULL(port))
848 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
849
850 if (state->duplex == DUPLEX_FULL)
851 reg |= RTL930X_DUPLEX_MODE;
852 else
853 reg &= ~RTL930X_DUPLEX_MODE; /* Clear duplex bit otherwise */
854
855 if (priv->ports[port].phy_is_integrated)
856 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
857 else
858 reg |= RTL930X_FORCE_EN;
859
860 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
861 }
862
863 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
864 unsigned int mode,
865 phy_interface_t interface)
866 {
867 struct rtl838x_switch_priv *priv = ds->priv;
868 int mask = 0;
869
870 /* Stop TX/RX to port */
871 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
872
873 /* No longer force link */
874 mask = RTL83XX_FORCE_EN | RTL83XX_FORCE_LINK_EN;
875 sw_w32_mask(mask, 0, priv->r->mac_force_mode_ctrl(port));
876 }
877
878 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
879 unsigned int mode,
880 phy_interface_t interface)
881 {
882 struct rtl838x_switch_priv *priv = ds->priv;
883 u32 v = 0;
884
885 /* Stop TX/RX to port */
886 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
887
888 /* No longer force link */
889 if (priv->family_id == RTL9300_FAMILY_ID)
890 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
891 else if (priv->family_id == RTL9310_FAMILY_ID)
892 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
893 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
894 }
895
896 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
897 unsigned int mode,
898 phy_interface_t interface,
899 struct phy_device *phydev,
900 int speed, int duplex,
901 bool tx_pause, bool rx_pause)
902 {
903 struct dsa_port *dp = dsa_to_port(ds, port);
904 struct rtl838x_switch_priv *priv = ds->priv;
905 u32 mcr, spdsel;
906
907 if (speed == SPEED_1000)
908 spdsel = RTL_SPEED_1000;
909 else if (speed == SPEED_100)
910 spdsel = RTL_SPEED_100;
911 else
912 spdsel = RTL_SPEED_10;
913
914 mcr = sw_r32(priv->r->mac_force_mode_ctrl(port));
915
916 if (priv->family_id == RTL8380_FAMILY_ID) {
917 mcr &= ~RTL838X_RX_PAUSE_EN;
918 mcr &= ~RTL838X_TX_PAUSE_EN;
919 mcr &= ~RTL838X_DUPLEX_MODE;
920 mcr &= ~RTL838X_SPEED_MASK;
921 mcr |= RTL83XX_FORCE_LINK_EN;
922 mcr |= spdsel << RTL838X_SPEED_SHIFT;
923
924 if (tx_pause)
925 mcr |= RTL838X_TX_PAUSE_EN;
926 if (rx_pause)
927 mcr |= RTL838X_RX_PAUSE_EN;
928 if (duplex == DUPLEX_FULL || priv->lagmembers & BIT_ULL(port))
929 mcr |= RTL838X_DUPLEX_MODE;
930 if (dsa_port_is_cpu(dp))
931 mcr |= RTL83XX_FORCE_EN;
932
933 } else if (priv->family_id == RTL8390_FAMILY_ID) {
934 mcr &= ~RTL839X_RX_PAUSE_EN;
935 mcr &= ~RTL839X_TX_PAUSE_EN;
936 mcr &= ~RTL839X_DUPLEX_MODE;
937 mcr &= ~RTL839X_SPEED_MASK;
938 mcr |= RTL83XX_FORCE_LINK_EN;
939 mcr |= spdsel << RTL839X_SPEED_SHIFT;
940
941 if (tx_pause)
942 mcr |= RTL839X_TX_PAUSE_EN;
943 if (rx_pause)
944 mcr |= RTL839X_RX_PAUSE_EN;
945 if (duplex == DUPLEX_FULL || priv->lagmembers & BIT_ULL(port))
946 mcr |= RTL839X_DUPLEX_MODE;
947 if (dsa_port_is_cpu(dp))
948 mcr |= RTL83XX_FORCE_EN;
949 }
950
951 pr_debug("%s port %d, mode %x, speed %d, duplex %d, txpause %d, rxpause %d: set mcr=%08x\n",
952 __func__, port, mode, speed, duplex, tx_pause, rx_pause, mcr);
953 sw_w32(mcr, priv->r->mac_force_mode_ctrl(port));
954
955 /* Restart TX/RX to port */
956 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
957 }
958
959 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
960 unsigned int mode,
961 phy_interface_t interface,
962 struct phy_device *phydev,
963 int speed, int duplex,
964 bool tx_pause, bool rx_pause)
965 {
966 struct rtl838x_switch_priv *priv = ds->priv;
967
968 /* Restart TX/RX to port */
969 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
970 /* TODO: Set speed/duplex/pauses */
971 }
972
973 static void rtl83xx_get_strings(struct dsa_switch *ds,
974 int port, u32 stringset, u8 *data)
975 {
976 if (stringset != ETH_SS_STATS)
977 return;
978
979 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
980 ethtool_puts(&data, rtl83xx_mib[i].name);
981 }
982
983 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
984 uint64_t *data)
985 {
986 struct rtl838x_switch_priv *priv = ds->priv;
987 const struct rtl83xx_mib_desc *mib;
988 u64 h;
989
990 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
991 mib = &rtl83xx_mib[i];
992
993 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
994 if (mib->size == 2) {
995 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
996 data[i] |= h << 32;
997 }
998 }
999 }
1000
1001 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1002 {
1003 if (sset != ETH_SS_STATS)
1004 return 0;
1005
1006 return ARRAY_SIZE(rtl83xx_mib);
1007 }
1008
1009 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
1010 {
1011 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
1012 u64 portmask;
1013
1014 if (mc_group >= MAX_MC_GROUPS - 1)
1015 return -1;
1016
1017 set_bit(mc_group, priv->mc_group_bm);
1018 portmask = BIT_ULL(port);
1019 priv->r->write_mcast_pmask(mc_group, portmask);
1020
1021 return mc_group;
1022 }
1023
1024 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1025 {
1026 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1027
1028 pr_debug("%s: %d\n", __func__, port);
1029
1030 portmask |= BIT_ULL(port);
1031 priv->r->write_mcast_pmask(mc_group, portmask);
1032
1033 return portmask;
1034 }
1035
1036 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1037 {
1038 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1039
1040 pr_debug("%s: %d\n", __func__, port);
1041
1042 portmask &= ~BIT_ULL(port);
1043 priv->r->write_mcast_pmask(mc_group, portmask);
1044 if (!portmask)
1045 clear_bit(mc_group, priv->mc_group_bm);
1046
1047 return portmask;
1048 }
1049
1050 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1051 struct phy_device *phydev)
1052 {
1053 struct rtl838x_switch_priv *priv = ds->priv;
1054 u64 v;
1055
1056 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1057 priv->ports[port].enable = true;
1058
1059 /* enable inner tagging on egress, do not keep any tags */
1060 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1061
1062 if (dsa_is_cpu_port(ds, port))
1063 return 0;
1064
1065 /* add port to switch mask of CPU_PORT */
1066 priv->r->traffic_enable(priv->cpu_port, port);
1067
1068 if (priv->is_lagmember[port]) {
1069 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1070 return 0;
1071 }
1072
1073 /* add all other ports in the same bridge to switch mask of port */
1074 v = priv->r->traffic_get(port);
1075 v |= priv->ports[port].pm;
1076 priv->r->traffic_set(port, v);
1077
1078 /* TODO: Figure out if this is necessary */
1079 if (priv->family_id == RTL9300_FAMILY_ID) {
1080 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1081 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1082 }
1083
1084 if (priv->ports[port].sds_num < 0)
1085 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1086
1087 return 0;
1088 }
1089
1090 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1091 {
1092 struct rtl838x_switch_priv *priv = ds->priv;
1093 u64 v;
1094
1095 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1096 /* you can only disable user ports */
1097 if (!dsa_is_user_port(ds, port))
1098 return;
1099
1100 /* BUG: This does not work on RTL931X */
1101 /* remove port from switch mask of CPU_PORT */
1102 priv->r->traffic_disable(priv->cpu_port, port);
1103
1104 /* remove all other ports in the same bridge from switch mask of port */
1105 v = priv->r->traffic_get(port);
1106 v &= ~priv->ports[port].pm;
1107 priv->r->traffic_set(port, v);
1108
1109 priv->ports[port].enable = false;
1110 }
1111
1112 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1113 struct ethtool_eee *e)
1114 {
1115 struct rtl838x_switch_priv *priv = ds->priv;
1116
1117 if (e->eee_enabled && !priv->eee_enabled) {
1118 pr_info("Globally enabling EEE\n");
1119 priv->r->init_eee(priv, true);
1120 }
1121
1122 priv->r->port_eee_set(priv, port, e->eee_enabled);
1123
1124 if (e->eee_enabled)
1125 pr_info("Enabled EEE for port %d\n", port);
1126 else
1127 pr_info("Disabled EEE for port %d\n", port);
1128
1129 return 0;
1130 }
1131
1132 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1133 struct ethtool_eee *e)
1134 {
1135 struct rtl838x_switch_priv *priv = ds->priv;
1136
1137 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1138
1139 priv->r->eee_port_ability(priv, e, port);
1140
1141 e->eee_enabled = priv->ports[port].eee_enabled;
1142
1143 e->eee_active = !!(e->advertised & e->lp_advertised);
1144
1145 return 0;
1146 }
1147
1148 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1149 struct ethtool_eee *e)
1150 {
1151 struct rtl838x_switch_priv *priv = ds->priv;
1152
1153 e->supported = SUPPORTED_100baseT_Full |
1154 SUPPORTED_1000baseT_Full |
1155 SUPPORTED_2500baseX_Full;
1156
1157 priv->r->eee_port_ability(priv, e, port);
1158
1159 e->eee_enabled = priv->ports[port].eee_enabled;
1160
1161 e->eee_active = !!(e->advertised & e->lp_advertised);
1162
1163 return 0;
1164 }
1165
1166 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1167 {
1168 struct rtl838x_switch_priv *priv = ds->priv;
1169
1170 priv->r->set_ageing_time(msec);
1171
1172 return 0;
1173 }
1174
1175 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1176 struct dsa_bridge bridge,
1177 bool *tx_fwd_offload,
1178 struct netlink_ext_ack *extack)
1179 {
1180 struct rtl838x_switch_priv *priv = ds->priv;
1181 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1182
1183 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1184
1185 if (priv->is_lagmember[port]) {
1186 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1187 return 0;
1188 }
1189
1190 mutex_lock(&priv->reg_mutex);
1191 for (int i = 0; i < ds->num_ports; i++) {
1192 /* Add this port to the port matrix of the other ports in the
1193 * same bridge. If the port is disabled, port matrix is kept
1194 * and not being setup until the port becomes enabled.
1195 */
1196 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1197 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1198 continue;
1199 if (priv->ports[i].enable)
1200 priv->r->traffic_enable(i, port);
1201
1202 priv->ports[i].pm |= BIT_ULL(port);
1203 port_bitmap |= BIT_ULL(i);
1204 }
1205 }
1206
1207 /* Add all other ports to this port matrix. */
1208 if (priv->ports[port].enable) {
1209 priv->r->traffic_enable(priv->cpu_port, port);
1210 v = priv->r->traffic_get(port);
1211 v |= port_bitmap;
1212 priv->r->traffic_set(port, v);
1213 }
1214 priv->ports[port].pm |= port_bitmap;
1215
1216 if (priv->r->set_static_move_action)
1217 priv->r->set_static_move_action(port, false);
1218
1219 mutex_unlock(&priv->reg_mutex);
1220
1221 return 0;
1222 }
1223
1224 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1225 struct dsa_bridge bridge)
1226 {
1227 struct rtl838x_switch_priv *priv = ds->priv;
1228 u64 port_bitmap = 0, v;
1229
1230 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1231 mutex_lock(&priv->reg_mutex);
1232 for (int i = 0; i < ds->num_ports; i++) {
1233 /* Remove this port from the port matrix of the other ports
1234 * in the same bridge. If the port is disabled, port matrix
1235 * is kept and not being setup until the port becomes enabled.
1236 * And the other port's port matrix cannot be broken when the
1237 * other port is still a VLAN-aware port.
1238 */
1239 if (dsa_is_user_port(ds, i) && i != port) {
1240 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1241 continue;
1242 if (priv->ports[i].enable)
1243 priv->r->traffic_disable(i, port);
1244
1245 priv->ports[i].pm &= ~BIT_ULL(port);
1246 port_bitmap |= BIT_ULL(i);
1247 }
1248 }
1249
1250 /* Remove all other ports from this port matrix. */
1251 if (priv->ports[port].enable) {
1252 v = priv->r->traffic_get(port);
1253 v &= ~port_bitmap;
1254 priv->r->traffic_set(port, v);
1255 }
1256 priv->ports[port].pm &= ~port_bitmap;
1257
1258 if (priv->r->set_static_move_action)
1259 priv->r->set_static_move_action(port, true);
1260
1261 mutex_unlock(&priv->reg_mutex);
1262 }
1263
1264 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1265 {
1266 u32 msti = 0;
1267 u32 port_state[4];
1268 int index, bit;
1269 int pos = port;
1270 struct rtl838x_switch_priv *priv = ds->priv;
1271 int n = priv->port_width << 1;
1272
1273 /* Ports above or equal CPU port can never be configured */
1274 if (port >= priv->cpu_port)
1275 return;
1276
1277 mutex_lock(&priv->reg_mutex);
1278
1279 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1280 * have 64 bit fields, 839x and 931x have 128 bit fields
1281 */
1282 if (priv->family_id == RTL8390_FAMILY_ID)
1283 pos += 12;
1284 if (priv->family_id == RTL9300_FAMILY_ID)
1285 pos += 3;
1286 if (priv->family_id == RTL9310_FAMILY_ID)
1287 pos += 8;
1288
1289 index = n - (pos >> 4) - 1;
1290 bit = (pos << 1) % 32;
1291
1292 priv->r->stp_get(priv, msti, port_state);
1293
1294 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1295 port_state[index] &= ~(3 << bit);
1296
1297 switch (state) {
1298 case BR_STATE_DISABLED: /* 0 */
1299 port_state[index] |= (0 << bit);
1300 break;
1301 case BR_STATE_BLOCKING: /* 4 */
1302 case BR_STATE_LISTENING: /* 1 */
1303 port_state[index] |= (1 << bit);
1304 break;
1305 case BR_STATE_LEARNING: /* 2 */
1306 port_state[index] |= (2 << bit);
1307 break;
1308 case BR_STATE_FORWARDING: /* 3 */
1309 port_state[index] |= (3 << bit);
1310 default:
1311 break;
1312 }
1313
1314 priv->r->stp_set(priv, msti, port_state);
1315
1316 mutex_unlock(&priv->reg_mutex);
1317 }
1318
1319 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1320 {
1321 struct rtl838x_switch_priv *priv = ds->priv;
1322 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1323
1324 pr_debug("FAST AGE port %d\n", port);
1325 mutex_lock(&priv->reg_mutex);
1326 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1327 * port fields:
1328 * 0-4: Replacing port
1329 * 5-9: Flushed/replaced port
1330 * 10-21: FVID
1331 * 22: Entry types: 1: dynamic, 0: also static
1332 * 23: Match flush port
1333 * 24: Match FVID
1334 * 25: Flush (0) or replace (1) L2 entries
1335 * 26: Status of action (1: Start, 0: Done)
1336 */
1337 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1338
1339 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1340
1341 mutex_unlock(&priv->reg_mutex);
1342 }
1343
1344 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1345 {
1346 struct rtl838x_switch_priv *priv = ds->priv;
1347
1348 pr_info("%s port %d\n", __func__, port);
1349 mutex_lock(&priv->reg_mutex);
1350 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1351
1352 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1353
1354 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1355
1356 mutex_unlock(&priv->reg_mutex);
1357 }
1358
1359 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1360 {
1361 struct rtl838x_switch_priv *priv = ds->priv;
1362
1363 if (priv->family_id == RTL9310_FAMILY_ID)
1364 return rtl931x_fast_age(ds, port);
1365
1366 pr_debug("FAST AGE port %d\n", port);
1367 mutex_lock(&priv->reg_mutex);
1368 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1369
1370 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1371
1372 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1373
1374 mutex_unlock(&priv->reg_mutex);
1375 }
1376
1377 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1378 bool vlan_filtering,
1379 struct netlink_ext_ack *extack)
1380 {
1381 struct rtl838x_switch_priv *priv = ds->priv;
1382
1383 pr_debug("%s: port %d\n", __func__, port);
1384 mutex_lock(&priv->reg_mutex);
1385
1386 if (vlan_filtering) {
1387 /* Enable ingress and egress filtering
1388 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1389 * the filter action:
1390 * 0: Always Forward
1391 * 1: Drop packet
1392 * 2: Trap packet to CPU port
1393 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1394 */
1395 if (port != priv->cpu_port) {
1396 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1397 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1398 }
1399 else {
1400 priv->r->set_vlan_igr_filter(port, IGR_TRAP);
1401 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1402 }
1403
1404 } else {
1405 /* Disable ingress and egress filtering */
1406 if (port != priv->cpu_port)
1407 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1408
1409 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1410 }
1411
1412 /* Do we need to do something to the CPU-Port, too? */
1413 mutex_unlock(&priv->reg_mutex);
1414
1415 return 0;
1416 }
1417
1418 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1419 const struct switchdev_obj_port_vlan *vlan)
1420 {
1421 struct rtl838x_vlan_info info;
1422 struct rtl838x_switch_priv *priv = ds->priv;
1423
1424 priv->r->vlan_tables_read(0, &info);
1425
1426 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1427 info.tagged_ports, info.untagged_ports, info.profile_id,
1428 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1429
1430 priv->r->vlan_tables_read(1, &info);
1431 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1432 info.tagged_ports, info.untagged_ports, info.profile_id,
1433 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1434 priv->r->vlan_set_untagged(1, info.untagged_ports);
1435 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1436
1437 priv->r->vlan_set_tagged(1, &info);
1438 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1439
1440 return 0;
1441 }
1442
1443 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1444 const struct switchdev_obj_port_vlan *vlan,
1445 struct netlink_ext_ack *extack)
1446 {
1447 struct rtl838x_vlan_info info;
1448 struct rtl838x_switch_priv *priv = ds->priv;
1449 int err;
1450
1451 pr_debug("%s port %d, vid %d, flags %x\n",
1452 __func__, port, vlan->vid, vlan->flags);
1453
1454 /* Let no one mess with our special VLAN 0 */
1455 if (!vlan->vid) return 0;
1456
1457 if (vlan->vid > 4095) {
1458 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1459 return -ENOTSUPP;
1460 }
1461
1462 err = rtl83xx_vlan_prepare(ds, port, vlan);
1463 if (err)
1464 return err;
1465
1466 mutex_lock(&priv->reg_mutex);
1467
1468 /*
1469 * Realtek switches copy frames as-is to/from the CPU. For a proper
1470 * VLAN handling the 12 bit RVID field (= VLAN id) for incoming traffic
1471 * and the 1 bit RVID_SEL field (0 = use inner tag, 1 = use outer tag)
1472 * for outgoing traffic of the CPU tag structure need to be handled. As
1473 * of now no such logic is in place. So for the CPU port keep the fixed
1474 * PVID=0 from initial setup in place and ignore all subsequent settings.
1475 */
1476 if (port != priv->cpu_port) {
1477 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1478 rtl83xx_vlan_set_pvid(priv, port, vlan->vid);
1479 else if (priv->ports[port].pvid == vlan->vid)
1480 rtl83xx_vlan_set_pvid(priv, port, 0);
1481 }
1482
1483 /* Get port memberships of this vlan */
1484 priv->r->vlan_tables_read(vlan->vid, &info);
1485
1486 /* new VLAN? */
1487 if (!info.tagged_ports) {
1488 info.fid = 0;
1489 info.hash_mc_fid = false;
1490 info.hash_uc_fid = false;
1491 info.profile_id = 0;
1492 }
1493
1494 /* sanitize untagged_ports - must be a subset */
1495 if (info.untagged_ports & ~info.tagged_ports)
1496 info.untagged_ports = 0;
1497
1498 info.tagged_ports |= BIT_ULL(port);
1499 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1500 info.untagged_ports |= BIT_ULL(port);
1501 else
1502 info.untagged_ports &= ~BIT_ULL(port);
1503
1504 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1505 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1506
1507 priv->r->vlan_set_tagged(vlan->vid, &info);
1508 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1509
1510 mutex_unlock(&priv->reg_mutex);
1511
1512 return 0;
1513 }
1514
1515 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1516 const struct switchdev_obj_port_vlan *vlan)
1517 {
1518 struct rtl838x_vlan_info info;
1519 struct rtl838x_switch_priv *priv = ds->priv;
1520 u16 pvid;
1521
1522 pr_debug("%s: port %d, vid %d, flags %x\n",
1523 __func__, port, vlan->vid, vlan->flags);
1524
1525 /* Let no one mess with our special VLAN 0 */
1526 if (!vlan->vid) return 0;
1527
1528 if (vlan->vid > 4095) {
1529 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1530 return -ENOTSUPP;
1531 }
1532
1533 mutex_lock(&priv->reg_mutex);
1534 pvid = priv->ports[port].pvid;
1535
1536 /* Reset to default if removing the current PVID */
1537 if (vlan->vid == pvid) {
1538 rtl83xx_vlan_set_pvid(priv, port, 0);
1539 }
1540 /* Get port memberships of this vlan */
1541 priv->r->vlan_tables_read(vlan->vid, &info);
1542
1543 /* remove port from both tables */
1544 info.untagged_ports &= (~BIT_ULL(port));
1545 info.tagged_ports &= (~BIT_ULL(port));
1546
1547 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1548 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1549
1550 priv->r->vlan_set_tagged(vlan->vid, &info);
1551 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1552
1553 mutex_unlock(&priv->reg_mutex);
1554
1555 return 0;
1556 }
1557
1558 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1559 {
1560 memset(e, 0, sizeof(*e));
1561
1562 e->type = L2_UNICAST;
1563 e->valid = true;
1564
1565 e->age = 3;
1566 e->is_static = true;
1567
1568 e->port = port;
1569
1570 e->rvid = e->vid = vid;
1571 e->is_ip_mc = e->is_ipv6_mc = false;
1572 u64_to_ether_addr(mac, e->mac);
1573 }
1574
1575 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1576 {
1577 memset(e, 0, sizeof(*e));
1578
1579 e->type = L2_MULTICAST;
1580 e->valid = true;
1581
1582 e->mc_portmask_index = mc_group;
1583
1584 e->rvid = e->vid = vid;
1585 e->is_ip_mc = e->is_ipv6_mc = false;
1586 u64_to_ether_addr(mac, e->mac);
1587 }
1588
1589 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1590 * over the entries in the bucket until either a matching entry is found or an empty slot
1591 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1592 * when an empty slot was found and must exist is false, the index of the slot is returned
1593 * when no slots are available returns -1
1594 */
1595 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1596 bool must_exist, struct rtl838x_l2_entry *e)
1597 {
1598 int idx = -1;
1599 u32 key = priv->r->l2_hash_key(priv, seed);
1600 u64 entry;
1601
1602 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1603 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1604 for (int i = 0; i < priv->l2_bucket_size; i++) {
1605 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1606 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1607 if (must_exist && !e->valid)
1608 continue;
1609 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1610 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1611 break;
1612 }
1613 }
1614
1615 return idx;
1616 }
1617
1618 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1619 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1620 * when an empty slot was found the index of the slot is returned
1621 * when no slots are available returns -1
1622 */
1623 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1624 bool must_exist, struct rtl838x_l2_entry *e)
1625 {
1626 int idx = -1;
1627 u64 entry;
1628
1629 for (int i = 0; i < 64; i++) {
1630 entry = priv->r->read_cam(i, e);
1631 if (!must_exist && !e->valid) {
1632 if (idx < 0) /* First empty entry? */
1633 idx = i;
1634 break;
1635 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1636 pr_debug("Found entry in CAM\n");
1637 idx = i;
1638 break;
1639 }
1640 }
1641
1642 return idx;
1643 }
1644
1645 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1646 const unsigned char *addr, u16 vid,
1647 const struct dsa_db db)
1648 {
1649 struct rtl838x_switch_priv *priv = ds->priv;
1650 u64 mac = ether_addr_to_u64(addr);
1651 struct rtl838x_l2_entry e;
1652 int err = 0, idx;
1653 u64 seed = priv->r->l2_hash_seed(mac, vid);
1654
1655 if (priv->is_lagmember[port]) {
1656 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1657 return 0;
1658 }
1659
1660 mutex_lock(&priv->reg_mutex);
1661
1662 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1663
1664 /* Found an existing or empty entry */
1665 if (idx >= 0) {
1666 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1667 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1668 goto out;
1669 }
1670
1671 /* Hash buckets full, try CAM */
1672 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1673
1674 if (idx >= 0) {
1675 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1676 priv->r->write_cam(idx, &e);
1677 goto out;
1678 }
1679
1680 err = -ENOTSUPP;
1681
1682 out:
1683 mutex_unlock(&priv->reg_mutex);
1684
1685 return err;
1686 }
1687
1688 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1689 const unsigned char *addr, u16 vid,
1690 const struct dsa_db db)
1691 {
1692 struct rtl838x_switch_priv *priv = ds->priv;
1693 u64 mac = ether_addr_to_u64(addr);
1694 struct rtl838x_l2_entry e;
1695 int err = 0, idx;
1696 u64 seed = priv->r->l2_hash_seed(mac, vid);
1697
1698 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1699 mutex_lock(&priv->reg_mutex);
1700
1701 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1702
1703 if (idx >= 0) {
1704 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1705 e.valid = false;
1706 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1707 goto out;
1708 }
1709
1710 /* Check CAM for spillover from hash buckets */
1711 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1712
1713 if (idx >= 0) {
1714 e.valid = false;
1715 priv->r->write_cam(idx, &e);
1716 goto out;
1717 }
1718 err = -ENOENT;
1719
1720 out:
1721 mutex_unlock(&priv->reg_mutex);
1722
1723 return err;
1724 }
1725
1726 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1727 dsa_fdb_dump_cb_t *cb, void *data)
1728 {
1729 struct rtl838x_l2_entry e;
1730 struct rtl838x_switch_priv *priv = ds->priv;
1731
1732 mutex_lock(&priv->reg_mutex);
1733
1734 for (int i = 0; i < priv->fib_entries; i++) {
1735 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1736
1737 if (!e.valid)
1738 continue;
1739
1740 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1741 cb(e.mac, e.vid, e.is_static, data);
1742
1743 if (!((i + 1) % 64))
1744 cond_resched();
1745 }
1746
1747 for (int i = 0; i < 64; i++) {
1748 priv->r->read_cam(i, &e);
1749
1750 if (!e.valid)
1751 continue;
1752
1753 if (e.port == port)
1754 cb(e.mac, e.vid, e.is_static, data);
1755 }
1756
1757 mutex_unlock(&priv->reg_mutex);
1758
1759 return 0;
1760 }
1761
1762 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1763 const struct switchdev_obj_port_mdb *mdb,
1764 const struct dsa_db db)
1765 {
1766 struct rtl838x_switch_priv *priv = ds->priv;
1767 u64 mac = ether_addr_to_u64(mdb->addr);
1768 struct rtl838x_l2_entry e;
1769 int err = 0, idx;
1770 int vid = mdb->vid;
1771 u64 seed = priv->r->l2_hash_seed(mac, vid);
1772 int mc_group;
1773
1774 if (priv->id >= 0x9300)
1775 return -EOPNOTSUPP;
1776
1777 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1778
1779 if (priv->is_lagmember[port]) {
1780 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1781 return -EINVAL;
1782 }
1783
1784 mutex_lock(&priv->reg_mutex);
1785
1786 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1787
1788 /* Found an existing or empty entry */
1789 if (idx >= 0) {
1790 if (e.valid) {
1791 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1792 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1793 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1794 } else {
1795 pr_debug("New entry for seed %016llx\n", seed);
1796 mc_group = rtl83xx_mc_group_alloc(priv, port);
1797 if (mc_group < 0) {
1798 err = -ENOTSUPP;
1799 goto out;
1800 }
1801 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1802 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1803 }
1804 goto out;
1805 }
1806
1807 /* Hash buckets full, try CAM */
1808 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1809
1810 if (idx >= 0) {
1811 if (e.valid) {
1812 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1813 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1814 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1815 } else {
1816 pr_debug("New entry\n");
1817 mc_group = rtl83xx_mc_group_alloc(priv, port);
1818 if (mc_group < 0) {
1819 err = -ENOTSUPP;
1820 goto out;
1821 }
1822 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1823 priv->r->write_cam(idx, &e);
1824 }
1825 goto out;
1826 }
1827
1828 err = -ENOTSUPP;
1829
1830 out:
1831 mutex_unlock(&priv->reg_mutex);
1832 if (err)
1833 dev_err(ds->dev, "failed to add MDB entry\n");
1834
1835 return err;
1836 }
1837
1838 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1839 const struct switchdev_obj_port_mdb *mdb,
1840 const struct dsa_db db)
1841 {
1842 struct rtl838x_switch_priv *priv = ds->priv;
1843 u64 mac = ether_addr_to_u64(mdb->addr);
1844 struct rtl838x_l2_entry e;
1845 int err = 0, idx;
1846 int vid = mdb->vid;
1847 u64 seed = priv->r->l2_hash_seed(mac, vid);
1848 u64 portmask;
1849
1850 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1851
1852 if (priv->is_lagmember[port]) {
1853 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1854 return 0;
1855 }
1856
1857 mutex_lock(&priv->reg_mutex);
1858
1859 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1860
1861 if (idx >= 0) {
1862 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1863 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1864 if (!portmask) {
1865 e.valid = false;
1866 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1867 }
1868 goto out;
1869 }
1870
1871 /* Check CAM for spillover from hash buckets */
1872 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1873
1874 if (idx >= 0) {
1875 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1876 if (!portmask) {
1877 e.valid = false;
1878 priv->r->write_cam(idx, &e);
1879 }
1880 goto out;
1881 }
1882 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1883
1884 out:
1885 mutex_unlock(&priv->reg_mutex);
1886
1887 return err;
1888 }
1889
1890 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1891 struct dsa_mall_mirror_tc_entry *mirror,
1892 bool ingress, struct netlink_ext_ack *extack)
1893 {
1894 /* We support 4 mirror groups, one destination port per group */
1895 int group;
1896 struct rtl838x_switch_priv *priv = ds->priv;
1897 int ctrl_reg, dpm_reg, spm_reg;
1898
1899 pr_debug("In %s\n", __func__);
1900
1901 for (group = 0; group < 4; group++) {
1902 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1903 break;
1904 }
1905 if (group >= 4) {
1906 for (group = 0; group < 4; group++) {
1907 if (priv->mirror_group_ports[group] < 0)
1908 break;
1909 }
1910 }
1911
1912 if (group >= 4)
1913 return -ENOSPC;
1914
1915 ctrl_reg = priv->r->mir_ctrl + group * 4;
1916 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1917 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1918
1919 pr_debug("Using group %d\n", group);
1920 mutex_lock(&priv->reg_mutex);
1921
1922 if (priv->family_id == RTL8380_FAMILY_ID) {
1923 /* Enable mirroring to port across VLANs (bit 11) */
1924 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1925 } else {
1926 /* Enable mirroring to destination port */
1927 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1928 }
1929
1930 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1931 mutex_unlock(&priv->reg_mutex);
1932 return -EEXIST;
1933 }
1934 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1935 mutex_unlock(&priv->reg_mutex);
1936 return -EEXIST;
1937 }
1938
1939 if (ingress)
1940 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1941 else
1942 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1943
1944 priv->mirror_group_ports[group] = mirror->to_local_port;
1945 mutex_unlock(&priv->reg_mutex);
1946
1947 return 0;
1948 }
1949
1950 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1951 struct dsa_mall_mirror_tc_entry *mirror)
1952 {
1953 int group = 0;
1954 struct rtl838x_switch_priv *priv = ds->priv;
1955 int ctrl_reg, dpm_reg, spm_reg;
1956
1957 pr_debug("In %s\n", __func__);
1958 for (group = 0; group < 4; group++) {
1959 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1960 break;
1961 }
1962 if (group >= 4)
1963 return;
1964
1965 ctrl_reg = priv->r->mir_ctrl + group * 4;
1966 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1967 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1968
1969 mutex_lock(&priv->reg_mutex);
1970 if (mirror->ingress) {
1971 /* Ingress, clear source port matrix */
1972 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1973 } else {
1974 /* Egress, clear destination port matrix */
1975 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1976 }
1977
1978 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1979 priv->mirror_group_ports[group] = -1;
1980 sw_w32(0, ctrl_reg);
1981 }
1982
1983 mutex_unlock(&priv->reg_mutex);
1984 }
1985
1986 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1987 {
1988 struct rtl838x_switch_priv *priv = ds->priv;
1989 unsigned long features = 0;
1990 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1991 if (priv->r->enable_learning)
1992 features |= BR_LEARNING;
1993 if (priv->r->enable_flood)
1994 features |= BR_FLOOD;
1995 if (priv->r->enable_mcast_flood)
1996 features |= BR_MCAST_FLOOD;
1997 if (priv->r->enable_bcast_flood)
1998 features |= BR_BCAST_FLOOD;
1999 if (flags.mask & ~(features))
2000 return -EINVAL;
2001
2002 return 0;
2003 }
2004
2005 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
2006 {
2007 struct rtl838x_switch_priv *priv = ds->priv;
2008
2009 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
2010 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
2011 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
2012
2013 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
2014 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
2015
2016 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
2017 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
2018
2019 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
2020 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
2021
2022 return 0;
2023 }
2024
2025 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
2026 struct net_device *lag,
2027 struct netdev_lag_upper_info *info)
2028 {
2029 int id;
2030
2031 id = dsa_lag_id(ds->dst, lag);
2032 if (id < 0 || id >= ds->num_lag_ids)
2033 return false;
2034
2035 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2036 return false;
2037 }
2038 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2039 return false;
2040
2041 return true;
2042 }
2043
2044 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2045 {
2046 pr_debug("%s: %d\n", __func__, port);
2047 /* Nothing to be done... */
2048
2049 return 0;
2050 }
2051
2052 static int rtl83xx_port_lag_join(struct dsa_switch *ds,
2053 int port,
2054 struct dsa_lag lag,
2055 struct netdev_lag_upper_info *info,
2056 struct netlink_ext_ack *extack)
2057 {
2058 struct rtl838x_switch_priv *priv = ds->priv;
2059 int i, err = 0;
2060
2061 if (!rtl83xx_lag_can_offload(ds, lag.dev, info))
2062 return -EOPNOTSUPP;
2063
2064 mutex_lock(&priv->reg_mutex);
2065
2066 for (i = 0; i < priv->n_lags; i++) {
2067 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag.dev))
2068 break;
2069 }
2070 if (port >= priv->cpu_port) {
2071 err = -EINVAL;
2072 goto out;
2073 }
2074 pr_info("port_lag_join: group %d, port %d\n",i, port);
2075 if (!priv->lag_devs[i])
2076 priv->lag_devs[i] = lag.dev;
2077
2078 if (priv->lag_primary[i] == -1) {
2079 priv->lag_primary[i] = port;
2080 } else
2081 priv->is_lagmember[port] = 1;
2082
2083 priv->lagmembers |= (1ULL << port);
2084
2085 pr_debug("lag_members = %llX\n", priv->lagmembers);
2086 err = rtl83xx_lag_add(priv->ds, i, port, info);
2087 if (err) {
2088 err = -EINVAL;
2089 goto out;
2090 }
2091
2092 out:
2093 mutex_unlock(&priv->reg_mutex);
2094
2095 return err;
2096 }
2097
2098 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2099 struct dsa_lag lag)
2100 {
2101 int i, group = -1, err;
2102 struct rtl838x_switch_priv *priv = ds->priv;
2103
2104 mutex_lock(&priv->reg_mutex);
2105 for (i = 0; i < priv->n_lags; i++) {
2106 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2107 group = i;
2108 break;
2109 }
2110 }
2111
2112 if (group == -1) {
2113 pr_info("port_lag_leave: port %d is not a member\n", port);
2114 err = -EINVAL;
2115 goto out;
2116 }
2117
2118 if (port >= priv->cpu_port) {
2119 err = -EINVAL;
2120 goto out;
2121 }
2122 pr_info("port_lag_del: group %d, port %d\n",group, port);
2123 priv->lagmembers &=~ (1ULL << port);
2124 priv->lag_primary[i] = -1;
2125 priv->is_lagmember[port] = 0;
2126 pr_debug("lag_members = %llX\n", priv->lagmembers);
2127 err = rtl83xx_lag_del(priv->ds, group, port);
2128 if (err) {
2129 err = -EINVAL;
2130 goto out;
2131 }
2132 if (!priv->lags_port_members[i])
2133 priv->lag_devs[i] = NULL;
2134
2135 out:
2136 mutex_unlock(&priv->reg_mutex);
2137 return 0;
2138 }
2139
2140 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2141 {
2142 u32 val;
2143 u32 offset = 0;
2144 struct rtl838x_switch_priv *priv = ds->priv;
2145
2146 if ((phy_addr >= 24) &&
2147 (phy_addr <= 27) &&
2148 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2149 if (phy_addr == 26)
2150 offset = 0x100;
2151 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2152 return val;
2153 }
2154
2155 read_phy(phy_addr, 0, phy_reg, &val);
2156 return val;
2157 }
2158
2159 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2160 {
2161 u32 offset = 0;
2162 struct rtl838x_switch_priv *priv = ds->priv;
2163
2164 if ((phy_addr >= 24) &&
2165 (phy_addr <= 27) &&
2166 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2167 if (phy_addr == 26)
2168 offset = 0x100;
2169 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2170 return 0;
2171 }
2172 return write_phy(phy_addr, 0, phy_reg, val);
2173 }
2174
2175 const struct phylink_pcs_ops rtl83xx_pcs_ops = {
2176 .pcs_an_restart = rtl83xx_pcs_an_restart,
2177 .pcs_validate = rtl83xx_pcs_validate,
2178 .pcs_get_state = rtl83xx_pcs_get_state,
2179 .pcs_config = rtl83xx_pcs_config,
2180 };
2181
2182 const struct dsa_switch_ops rtl83xx_switch_ops = {
2183 .get_tag_protocol = rtl83xx_get_tag_protocol,
2184 .setup = rtl83xx_setup,
2185
2186 .phy_read = dsa_phy_read,
2187 .phy_write = dsa_phy_write,
2188
2189 .phylink_get_caps = rtl83xx_phylink_get_caps,
2190 .phylink_mac_config = rtl83xx_phylink_mac_config,
2191 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2192 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2193 .phylink_mac_select_pcs = rtl83xx_phylink_mac_select_pcs,
2194
2195 .get_strings = rtl83xx_get_strings,
2196 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2197 .get_sset_count = rtl83xx_get_sset_count,
2198
2199 .port_enable = rtl83xx_port_enable,
2200 .port_disable = rtl83xx_port_disable,
2201
2202 .get_mac_eee = rtl83xx_get_mac_eee,
2203 .set_mac_eee = rtl83xx_set_mac_eee,
2204
2205 .set_ageing_time = rtl83xx_set_ageing_time,
2206 .port_bridge_join = rtl83xx_port_bridge_join,
2207 .port_bridge_leave = rtl83xx_port_bridge_leave,
2208 .port_stp_state_set = rtl83xx_port_stp_state_set,
2209 .port_fast_age = rtl83xx_fast_age,
2210
2211 .port_vlan_filtering = rtl83xx_vlan_filtering,
2212 .port_vlan_add = rtl83xx_vlan_add,
2213 .port_vlan_del = rtl83xx_vlan_del,
2214
2215 .port_fdb_add = rtl83xx_port_fdb_add,
2216 .port_fdb_del = rtl83xx_port_fdb_del,
2217 .port_fdb_dump = rtl83xx_port_fdb_dump,
2218
2219 .port_mdb_add = rtl83xx_port_mdb_add,
2220 .port_mdb_del = rtl83xx_port_mdb_del,
2221
2222 .port_mirror_add = rtl83xx_port_mirror_add,
2223 .port_mirror_del = rtl83xx_port_mirror_del,
2224
2225 .port_lag_change = rtl83xx_port_lag_change,
2226 .port_lag_join = rtl83xx_port_lag_join,
2227 .port_lag_leave = rtl83xx_port_lag_leave,
2228
2229 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2230 .port_bridge_flags = rtl83xx_port_bridge_flags,
2231 };
2232
2233 const struct phylink_pcs_ops rtl93xx_pcs_ops = {
2234 .pcs_an_restart = rtl83xx_pcs_an_restart,
2235 .pcs_validate = rtl93xx_pcs_validate,
2236 .pcs_get_state = rtl93xx_pcs_get_state,
2237 .pcs_config = rtl83xx_pcs_config,
2238 };
2239
2240 const struct dsa_switch_ops rtl930x_switch_ops = {
2241 .get_tag_protocol = rtl83xx_get_tag_protocol,
2242 .setup = rtl93xx_setup,
2243
2244 .phy_read = dsa_phy_read,
2245 .phy_write = dsa_phy_write,
2246
2247 .phylink_get_caps = rtl83xx_phylink_get_caps,
2248 .phylink_mac_config = rtl93xx_phylink_mac_config,
2249 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2250 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2251 .phylink_mac_select_pcs = rtl83xx_phylink_mac_select_pcs,
2252
2253 .get_strings = rtl83xx_get_strings,
2254 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2255 .get_sset_count = rtl83xx_get_sset_count,
2256
2257 .port_enable = rtl83xx_port_enable,
2258 .port_disable = rtl83xx_port_disable,
2259
2260 .get_mac_eee = rtl93xx_get_mac_eee,
2261 .set_mac_eee = rtl83xx_set_mac_eee,
2262
2263 .set_ageing_time = rtl83xx_set_ageing_time,
2264 .port_bridge_join = rtl83xx_port_bridge_join,
2265 .port_bridge_leave = rtl83xx_port_bridge_leave,
2266 .port_stp_state_set = rtl83xx_port_stp_state_set,
2267 .port_fast_age = rtl930x_fast_age,
2268
2269 .port_vlan_filtering = rtl83xx_vlan_filtering,
2270 .port_vlan_add = rtl83xx_vlan_add,
2271 .port_vlan_del = rtl83xx_vlan_del,
2272
2273 .port_fdb_add = rtl83xx_port_fdb_add,
2274 .port_fdb_del = rtl83xx_port_fdb_del,
2275 .port_fdb_dump = rtl83xx_port_fdb_dump,
2276
2277 .port_mdb_add = rtl83xx_port_mdb_add,
2278 .port_mdb_del = rtl83xx_port_mdb_del,
2279
2280 .port_lag_change = rtl83xx_port_lag_change,
2281 .port_lag_join = rtl83xx_port_lag_join,
2282 .port_lag_leave = rtl83xx_port_lag_leave,
2283
2284 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2285 .port_bridge_flags = rtl83xx_port_bridge_flags,
2286 };
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