add support for target 3c24xx (more known as Openmoko GTA02 "Freerunner") and merge...
[openwrt/openwrt.git] / target / linux / s3c24xx / patches / 0212-introduce-BANKCON-meddling-sysfs.patch.patch
1 From 3db422fde610960fdca8bd2a2b882015a62860ca Mon Sep 17 00:00:00 2001
2 From: Andy Green <andy@openmoko.com>
3 Date: Fri, 25 Jul 2008 23:06:20 +0100
4 Subject: [PATCH] introduce-BANKCON-meddling-sysfs.patch
5
6 A few questions have been flying around about how optimal
7 our waitstates are for various things including Glamo.
8
9 This patch introduces new sysfs nodes
10
11 /sys/devices/platform/neo1973-memconfig.0/BANKCON0
12 ...
13 /sys/devices/platform/neo1973-memconfig.0/BANKCON7
14
15 If you cat them you get translated info about bus speed on
16 that chip select, eg,
17
18 # cat /sys/devices/platform/neo1973-memconfig.0/BANKCON1
19 BANKCON1 = 0x00000A40
20 Type = ROM / SRAM
21 PMC = normal (1 data)
22 Tacp = 2 clocks
23 Tcah = 0 clocks
24 Tcoh = 1 clock
25 Tacc = 3 clocks
26 Tcos = 1 clock
27 Tacs = 0 clocks
28
29 You can write them in hex too
30
31 # echo 0x200 > /sys/devices/platform/neo1973-memconfig.0/BANKCON1
32
33 The write format for BANKCON0 - 5 looks like this
34
35 b1..b0 PMC Page Mode Config
36 b3..b2 Tacp Page Mode Access Cycle
37 b5..b4 Tcah Address hold after CS deasserted
38 b7..b6 Tcoh CS hold after OE deasserted
39 b10..b8 Tacc Access Cycle Period
40 b12..b11 Tcos CS setup before OE asserted
41 b14..b13 Tacs Address setup before CS asserted
42
43 BANKCON 6 and 7 have two extra bits
44
45 b16..b15 MT Memory type (00=ROM/SRAM, 11=DRAM)
46
47 If it's ROM/SRAM, the rest of the bits are as described above.
48 For DRAM
49
50 b1..b0 SCAN Column address number
51 b3..b2 RAS to CAS delay
52
53 The patch is intended to let people experiement on their own. But
54 of course you will crash things for sure if the timing is wrong, and
55 you can also trash SD Card data if you make Glamo unstable, so remove
56 it or remount ro first. Other horrible things are possible, but
57 because the settings aren't sticky, you should always be able to
58 recover by either normal reboot usually or at worst NOR boot and then
59 dfu. Most likely you will just crash your session and have to reboot
60 if your settings are bad, but consider yourself warned bad things are
61 possible. :-)
62
63 Signed-off-by: Andy Green <andy@openmoko.com>
64 ---
65 arch/arm/mach-s3c2440/mach-gta02.c | 6 +
66 arch/arm/plat-s3c24xx/Makefile | 3 +-
67 arch/arm/plat-s3c24xx/neo1973_memconfig.c | 186 +++++++++++++++++++++++++++++
68 3 files changed, 194 insertions(+), 1 deletions(-)
69 create mode 100644 arch/arm/plat-s3c24xx/neo1973_memconfig.c
70
71 diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
72 index b3d3797..f30abb6 100644
73 --- a/arch/arm/mach-s3c2440/mach-gta02.c
74 +++ b/arch/arm/mach-s3c2440/mach-gta02.c
75 @@ -412,6 +412,11 @@ struct platform_device gta02_resume_reason_device = {
76 .num_resources = 0,
77 };
78
79 +struct platform_device gta02_memconfig_device = {
80 + .name = "neo1973-memconfig",
81 + .num_resources = 0,
82 +};
83 +
84 static struct map_desc gta02_iodesc[] __initdata = {
85 {
86 .virtual = 0xe0000000,
87 @@ -829,6 +834,7 @@ static struct platform_device *gta02_devices[] __initdata = {
88 &gta02_nor_flash,
89 &sc32440_fiq_device,
90 &gta02_version_device,
91 + &gta02_memconfig_device,
92 &gta02_resume_reason_device,
93 &s3c24xx_pwm_device,
94
95 diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
96 index f60dc5f..baae831 100644
97 --- a/arch/arm/plat-s3c24xx/Makefile
98 +++ b/arch/arm/plat-s3c24xx/Makefile
99 @@ -35,4 +35,5 @@ obj-$(CONFIG_MACH_NEO1973) += neo1973_version.o \
100 neo1973_pm_gps.o \
101 neo1973_pm_bt.o \
102 neo1973_shadow.o \
103 - neo1973_pm_resume_reason.o
104 + neo1973_pm_resume_reason.o \
105 + neo1973_memconfig.o
106 diff --git a/arch/arm/plat-s3c24xx/neo1973_memconfig.c b/arch/arm/plat-s3c24xx/neo1973_memconfig.c
107 new file mode 100644
108 index 0000000..55d85fc
109 --- /dev/null
110 +++ b/arch/arm/plat-s3c24xx/neo1973_memconfig.c
111 @@ -0,0 +1,186 @@
112 +/*
113 + * Memory access timing control sysfs for the s3c24xx based device
114 + *
115 + * (C) 2008 by Openmoko Inc.
116 + * Author: Andy Green <andy@openmoko.com>
117 + * All rights reserved.
118 + *
119 + * This program is free software; you can redistribute it and/or modify
120 + * it under the terms of the GNU General Public License version 2 as
121 + * published by the Free Software Foundation
122 + *
123 + */
124 +
125 +#include <linux/module.h>
126 +#include <linux/init.h>
127 +#include <linux/kernel.h>
128 +#include <linux/platform_device.h>
129 +
130 +#include <asm/hardware.h>
131 +#include <asm/mach-types.h>
132 +#include <asm/arch/regs-mem.h>
133 +
134 +static ssize_t neo1973_memconfig_read(struct device *dev,
135 + struct device_attribute *attr, char *buf)
136 +{
137 + int index = attr->attr.name[strlen(attr->attr.name) - 1] - '0';
138 + u32 reg = *((u32 *)(S3C2410_MEMREG(((index + 1) << 2))));
139 + static const char *meaning[][8] = {
140 + {
141 + [0] = "normal (1 data)",
142 + [1] = "4 data",
143 + [2] = "8 data",
144 + [3] = "16 data",
145 + }, {
146 + [0] = "2 clocks",
147 + [1] = "3 clocks",
148 + [2] = "4 clocks",
149 + [3] = "6 clocks",
150 + }, {
151 + [0] = "0 clocks",
152 + [1] = "1 clock",
153 + [2] = "2 clocks",
154 + [3] = "4 clocks",
155 + }, {
156 + [0] = "1 clock",
157 + [1] = "2 clocks",
158 + [2] = "3 clocks",
159 + [3] = "4 clocks",
160 + [4] = "6 clocks",
161 + [5] = "8 clocks",
162 + [6] = "10 clocks",
163 + [7] = "14 clocks",
164 + }, { /* after this, only for CS6 and CS7 */
165 + [0] = "ROM / SRAM",
166 + [1] = "(illegal)",
167 + [2] = "(illegal)",
168 + [3] = "Sync DRAM",
169 + }, {
170 + [0] = "8 Column bits",
171 + [1] = "9 Column bits",
172 + [2] = "10 Column bits",
173 + [3] = "(illegal)",
174 + }, {
175 + [0] = "2 clocks",
176 + [1] = "3 clocks",
177 + [2] = "4 clocks",
178 + [3] = "(illegal)",
179 + }
180 + };
181 +
182 + if (index >= 6)
183 + if (((reg >> 15) & 3) == 3) /* DRAM */
184 + return sprintf(buf, "BANKCON%d = 0x%08X\n DRAM:\n"
185 + " Trcd = %s\n SCAN = %s\n", index,
186 + reg, meaning[5][reg & 3],
187 + meaning[1][(reg >> 2) & 3]);
188 +
189 + return sprintf(buf, "BANKCON%d = 0x%08X\n Type = %s\n PMC = %s\n"
190 + " Tacp = %s\n Tcah = %s\n Tcoh = %s\n Tacc = %s\n"
191 + " Tcos = %s\n Tacs = %s\n",
192 + index, reg, meaning[4][(reg >> 15) & 3],
193 + meaning[0][reg & 3],
194 + meaning[1][(reg >> 2) & 3],
195 + meaning[2][(reg >> 4) & 3],
196 + meaning[2][(reg >> 6) & 3],
197 + meaning[3][(reg >> 8) & 7],
198 + meaning[2][(reg >> 11) & 3],
199 + meaning[2][(reg >> 13) & 3]);
200 +}
201 +
202 +static ssize_t neo1973_memconfig_write(struct device *dev,
203 + struct device_attribute *attr, const char *buf, size_t count)
204 +{
205 + int index = attr->attr.name[strlen(attr->attr.name) - 1] - '0';
206 + unsigned long val = simple_strtoul(buf, NULL, 16);
207 +
208 + dev_info(dev, "setting BANKCON%d <- 0x%08X\n", index, (u32)val);
209 +
210 + *((u32 *)(S3C2410_MEMREG(((index + 1) << 2)))) = (u32)val;
211 +
212 + return count;
213 +}
214 +
215 +
216 +static DEVICE_ATTR(BANKCON0, 0644, neo1973_memconfig_read,
217 + neo1973_memconfig_write);
218 +static DEVICE_ATTR(BANKCON1, 0644, neo1973_memconfig_read,
219 + neo1973_memconfig_write);
220 +static DEVICE_ATTR(BANKCON2, 0644, neo1973_memconfig_read,
221 + neo1973_memconfig_write);
222 +static DEVICE_ATTR(BANKCON3, 0644, neo1973_memconfig_read,
223 + neo1973_memconfig_write);
224 +static DEVICE_ATTR(BANKCON4, 0644, neo1973_memconfig_read,
225 + neo1973_memconfig_write);
226 +static DEVICE_ATTR(BANKCON5, 0644, neo1973_memconfig_read,
227 + neo1973_memconfig_write);
228 +static DEVICE_ATTR(BANKCON6, 0644, neo1973_memconfig_read,
229 + neo1973_memconfig_write);
230 +static DEVICE_ATTR(BANKCON7, 0644, neo1973_memconfig_read,
231 + neo1973_memconfig_write);
232 +
233 +static struct attribute *neo1973_memconfig_sysfs_entries[] = {
234 + &dev_attr_BANKCON0.attr,
235 + &dev_attr_BANKCON1.attr,
236 + &dev_attr_BANKCON2.attr,
237 + &dev_attr_BANKCON3.attr,
238 + &dev_attr_BANKCON4.attr,
239 + &dev_attr_BANKCON5.attr,
240 + &dev_attr_BANKCON6.attr,
241 + &dev_attr_BANKCON7.attr,
242 + NULL
243 +};
244 +
245 +static struct attribute_group neo1973_memconfig_attr_group = {
246 + .name = NULL,
247 + .attrs = neo1973_memconfig_sysfs_entries,
248 +};
249 +
250 +static int __init neo1973_memconfig_probe(struct platform_device *pdev)
251 +{
252 + dev_info(&pdev->dev, "starting\n");
253 +
254 + switch (machine_arch_type) {
255 +#ifdef CONFIG_MACH_NEO1973_GTA01
256 + case MACH_TYPE_NEO1973_GTA01:
257 + return -EINVAL;
258 +#endif /* CONFIG_MACH_NEO1973_GTA01 */
259 + default:
260 + break;
261 + }
262 +
263 + return sysfs_create_group(&pdev->dev.kobj,
264 + &neo1973_memconfig_attr_group);
265 +}
266 +
267 +static int neo1973_memconfig_remove(struct platform_device *pdev)
268 +{
269 + sysfs_remove_group(&pdev->dev.kobj, &neo1973_memconfig_attr_group);
270 + return 0;
271 +}
272 +
273 +static struct platform_driver neo1973_memconfig_driver = {
274 + .probe = neo1973_memconfig_probe,
275 + .remove = neo1973_memconfig_remove,
276 + .driver = {
277 + .name = "neo1973-memconfig",
278 + },
279 +};
280 +
281 +static int __devinit neo1973_memconfig_init(void)
282 +{
283 + return platform_driver_register(&neo1973_memconfig_driver);
284 +}
285 +
286 +static void neo1973_memconfig_exit(void)
287 +{
288 + platform_driver_unregister(&neo1973_memconfig_driver);
289 +}
290 +
291 +module_init(neo1973_memconfig_init);
292 +module_exit(neo1973_memconfig_exit);
293 +
294 +MODULE_LICENSE("GPL");
295 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
296 +MODULE_DESCRIPTION("neo1973 memconfig");
297 +
298 --
299 1.5.6.3
300