1 From 4f40ad1587e9435a2085703fa2a7d7c9245306b2 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Sun, 26 May 2013 14:08:59 -0300
4 Subject: [PATCH] ARM: sunxi: add PLL5 and PLL6 support
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
14 arch/arm/boot/dts/sun4i-a10.dtsi | 19 +++++++++++++++++--
15 arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++--
16 arch/arm/boot/dts/sun5i-a13.dtsi | 19 +++++++++++++++++--
17 arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++------------
18 4 files changed, 67 insertions(+), 18 deletions(-)
20 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
21 index a6c1cae..5e2fc45 100644
22 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
23 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
28 + pll5: pll5@01c20020 {
30 + compatible = "allwinner,sun4i-pll5-clk";
31 + reg = <0x01c20020 0x4>;
33 + clock-output-names = "pll5_ddr", "pll5_other";
36 + pll6: pll6@01c20028 {
38 + compatible = "allwinner,sun4i-pll6-clk";
39 + reg = <0x01c20028 0x4>;
41 + clock-output-names = "pll6_sata", "pll6_other", "pll6";
48 "apb0_ir1", "apb0_keypad";
51 - /* dummy is pll62 */
52 apb1_mux: apb1_mux@01c20058 {
54 compatible = "allwinner,sun4i-apb1-mux-clk";
55 reg = <0x01c20058 0x4>;
56 - clocks = <&osc24M>, <&dummy>, <&osc32k>;
57 + clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
61 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
62 index c3f4eed..b29412a 100644
63 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
64 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
69 + pll5: pll5@01c20020 {
71 + compatible = "allwinner,sun4i-pll5-clk";
72 + reg = <0x01c20020 0x4>;
74 + clock-output-names = "pll5_ddr", "pll5_other";
77 + pll6: pll6@01c20028 {
79 + compatible = "allwinner,sun4i-pll6-clk";
80 + reg = <0x01c20028 0x4>;
82 + clock-output-names = "pll6_sata", "pll6_other", "pll6";
89 "apb0_ir", "apb0_keypad";
92 - /* dummy is pll62 */
93 apb1_mux: apb1_mux@01c20058 {
95 compatible = "allwinner,sun4i-apb1-mux-clk";
96 reg = <0x01c20058 0x4>;
97 - clocks = <&osc24M>, <&dummy>, <&osc32k>;
98 + clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
101 apb1: apb1@01c20058 {
102 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
103 index 8c4a9c3..cded3c7 100644
104 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
105 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
110 + pll5: pll5@01c20020 {
111 + #clock-cells = <1>;
112 + compatible = "allwinner,sun4i-pll5-clk";
113 + reg = <0x01c20020 0x4>;
114 + clocks = <&osc24M>;
115 + clock-output-names = "pll5_ddr", "pll5_other";
118 + pll6: pll6@01c20028 {
119 + #clock-cells = <1>;
120 + compatible = "allwinner,sun4i-pll6-clk";
121 + reg = <0x01c20028 0x4>;
122 + clocks = <&osc24M>;
123 + clock-output-names = "pll6_sata", "pll6_other", "pll6";
129 @@ -132,12 +148,11 @@
130 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
133 - /* dummy is pll6 */
134 apb1_mux: apb1_mux@01c20058 {
136 compatible = "allwinner,sun4i-apb1-mux-clk";
137 reg = <0x01c20058 0x4>;
138 - clocks = <&osc24M>, <&dummy>, <&osc32k>;
139 + clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
142 apb1: apb1@01c20058 {
143 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
144 index 21bf143..2e39ed9 100644
145 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
146 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
152 - * This is a dummy clock, to be used as placeholder on
153 - * other mux clocks when a specific parent clock is not
154 - * yet implemented. It should be dropped when the driver
158 - #clock-cells = <0>;
159 - compatible = "fixed-clock";
160 - clock-frequency = <0>;
161 + pll5: pll5@01c20020 {
162 + #clock-cells = <1>;
163 + compatible = "allwinner,sun4i-pll5-clk";
164 + reg = <0x01c20020 0x4>;
165 + clocks = <&osc24M>;
166 + clock-output-names = "pll5_ddr", "pll5_other";
169 + pll6: pll6@01c20028 {
170 + #clock-cells = <1>;
171 + compatible = "allwinner,sun4i-pll6-clk";
172 + reg = <0x01c20028 0x4>;
173 + clocks = <&osc24M>;
174 + clock-output-names = "pll6_sata", "pll6_other", "pll6";
179 compatible = "allwinner,sun4i-cpu-clk";
180 reg = <0x01c20054 0x4>;
181 - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
182 + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
188 compatible = "allwinner,sun4i-apb1-mux-clk";
189 reg = <0x01c20058 0x4>;
190 - clocks = <&osc24M>, <&pll6>, <&osc32k>;
191 + clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
194 apb1: apb1@01c20058 {