target/linux/sunxi/patches-3.12/175-sunxi-rtc.patch

   1 From 9b6e3291426efc69d1e8bf257721997f3eeb3009 Mon Sep 17 00:00:00 2001
   2 From: Carlo Caione <carlo.caione@gmail.com>
   3 Date: Wed, 16 Oct 2013 20:30:27 +0200
   4 Subject: [PATCH] ARM: sun4i/sun7i: RTC driver
   5
   6 This patch introduces the driver for the RTC in the Allwinner A10 and
   7 A20 SoCs.
   8
   9 Signed-off-by: Carlo Caione <carlo.caione@gmail.com>
  10 ---
  11  drivers/rtc/Kconfig     |   7 +
  12  drivers/rtc/Makefile    |   1 +
  13  drivers/rtc/rtc-sunxi.c | 487 ++++++++++++++++++++++++++++++++++++++++++++++++
  14  3 files changed, 495 insertions(+)
  15  create mode 100644 drivers/rtc/rtc-sunxi.c
  16
  17 diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
  18 index 9654aa3..ef45e0b 100644
  19 --- a/drivers/rtc/Kconfig
  20 +++ b/drivers/rtc/Kconfig
  21 @@ -1076,6 +1076,13 @@ config RTC_DRV_SUN4V
  22           If you say Y here you will get support for the Hypervisor
  23           based RTC on SUN4V systems.
  24
  25 +config RTC_DRV_SUNXI
  26 +       tristate "Allwinner sun4i/sun7i RTC"
  27 +       depends on ARCH_SUNXI
  28 +       help
  29 +         If you say Y here you will get support for the RTC found on
  30 +         Allwinner A10/A20.
  31 +
  32  config RTC_DRV_STARFIRE
  33         bool "Starfire RTC"
  34         depends on SPARC64
  35 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
  36 index 2dff3d2..8b52b5a 100644
  37 --- a/drivers/rtc/Makefile
  38 +++ b/drivers/rtc/Makefile
  39 @@ -115,6 +115,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE)      += rtc-starfire.o
  40  obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
  41  obj-$(CONFIG_RTC_DRV_STMP)     += rtc-stmp3xxx.o
  42  obj-$(CONFIG_RTC_DRV_SUN4V)    += rtc-sun4v.o
  43 +obj-$(CONFIG_RTC_DRV_SUNXI)    += rtc-sunxi.o
  44  obj-$(CONFIG_RTC_DRV_TEGRA)    += rtc-tegra.o
  45  obj-$(CONFIG_RTC_DRV_TEST)     += rtc-test.o
  46  obj-$(CONFIG_RTC_DRV_TILE)     += rtc-tile.o
  47 diff --git a/drivers/rtc/rtc-sunxi.c b/drivers/rtc/rtc-sunxi.c
  48 new file mode 100644
  49 index 0000000..ccd48ae
  50 --- /dev/null
  51 +++ b/drivers/rtc/rtc-sunxi.c
  52 @@ -0,0 +1,487 @@
  53 +/*
  54 + * An RTC driver for Allwinner A10/A20
  55 + *
  56 + * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  57 + *
  58 + * This program is free software; you can redistribute it and/or modify
  59 + * it under the terms of the GNU General Public License as published by
  60 + * the Free Software Foundation; either version 2 of the License, or
  61 + * (at your option) any later version.
  62 + *
  63 + * This program is distributed in the hope that it will be useful, but WITHOUT
  64 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  65 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  66 + * more details.
  67 + *
  68 + * You should have received a copy of the GNU General Public License along
  69 + * with this program; if not, write to the Free Software Foundation, Inc.,
  70 + * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  71 + */
  72 +
  73 +#include <linux/delay.h>
  74 +#include <linux/err.h>
  75 +#include <linux/fs.h>
  76 +#include <linux/init.h>
  77 +#include <linux/interrupt.h>
  78 +#include <linux/io.h>
  79 +#include <linux/kernel.h>
  80 +#include <linux/module.h>
  81 +#include <linux/of.h>
  82 +#include <linux/of_address.h>
  83 +#include <linux/of_device.h>
  84 +#include <linux/platform_device.h>
  85 +#include <linux/rtc.h>
  86 +#include <linux/types.h>
  87 +
  88 +#define SUNXI_LOSC_CTRL                                0x0000
  89 +#define SUNXI_LOSC_CTRL_RTC_HMS_ACC            BIT(8)
  90 +#define SUNXI_LOSC_CTRL_RTC_YMD_ACC            BIT(7)
  91 +
  92 +#define SUNXI_RTC_YMD                          0x0004
  93 +
  94 +#define SUNXI_RTC_HMS                          0x0008
  95 +
  96 +#define SUNXI_ALRM_DHMS                                0x000c
  97 +
  98 +#define SUNXI_ALRM_EN                          0x0014
  99 +#define SUNXI_ALRM_EN_CNT_EN                   BIT(8)
 100 +
 101 +#define SUNXI_ALRM_IRQ_EN                      0x0018
 102 +#define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN           BIT(0)
 103 +
 104 +#define SUNXI_ALRM_IRQ_STA                     0x001c
 105 +#define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND                BIT(0)
 106 +
 107 +#define SUNXI_LOSC_CTRL_RTC_ACC \
 108 +       (SUNXI_LOSC_CTRL_RTC_HMS_ACC | SUNXI_LOSC_CTRL_RTC_YMD_ACC)
 109 +
 110 +#define SUNXI_MASK_DH                          0x0000001f
 111 +#define SUNXI_MASK_SM                          0x0000003f
 112 +#define SUNXI_MASK_M                           0x0000000f
 113 +#define SUNXI_MASK_LY                          0x00000001
 114 +#define SUNXI_MASK_D                           0x00000ffe
 115 +#define SUNXI_MASK_M                           0x0000000f
 116 +
 117 +#define SUNXI_GET(x, mask, shift)              (((x) & ((mask) << (shift))) \
 118 +                                                       >> (shift))
 119 +
 120 +#define SUNXI_SET(x, mask, shift)              (((x) & (mask)) << (shift))
 121 +
 122 +/* Get date values */
 123 +#define SUNXI_DATE_GET_DAY_VALUE(x)            SUNXI_GET(x, SUNXI_MASK_DH, 0)
 124 +#define SUNXI_DATE_GET_MON_VALUE(x)            SUNXI_GET(x, SUNXI_MASK_M, 8)
 125 +#define SUNXI_DATE_GET_YEAR_VALUE(x, mask)     SUNXI_GET(x, mask, 16)
 126 +
 127 +/* Get time values */
 128 +#define SUNXI_TIME_GET_SEC_VALUE(x)            SUNXI_GET(x, SUNXI_MASK_SM, 0)
 129 +#define SUNXI_TIME_GET_MIN_VALUE(x)            SUNXI_GET(x, SUNXI_MASK_SM, 8)
 130 +#define SUNXI_TIME_GET_HOUR_VALUE(x)           SUNXI_GET(x, SUNXI_MASK_DH, 16)
 131 +
 132 +/* Get alarm values */
 133 +#define SUNXI_ALRM_GET_SEC_VALUE(x)            SUNXI_GET(x, SUNXI_MASK_SM, 0)
 134 +#define SUNXI_ALRM_GET_MIN_VALUE(x)            SUNXI_GET(x, SUNXI_MASK_SM, 8)
 135 +#define SUNXI_ALRM_GET_HOUR_VALUE(x)           SUNXI_GET(x, SUNXI_MASK_DH, 16)
 136 +
 137 +/* Set date values */
 138 +#define SUNXI_DATE_SET_DAY_VALUE(x)            SUNXI_DATE_GET_DAY_VALUE(x)
 139 +#define SUNXI_DATE_SET_MON_VALUE(x)            SUNXI_SET(x, SUNXI_MASK_M, 8)
 140 +#define SUNXI_DATE_SET_YEAR_VALUE(x, mask)     SUNXI_SET(x, mask, 16)
 141 +#define SUNXI_LEAP_SET_VALUE(x, shift)         SUNXI_SET(x, SUNXI_MASK_LY, shift)
 142 +
 143 +/* Set time values */
 144 +#define SUNXI_TIME_SET_SEC_VALUE(x)            SUNXI_TIME_GET_SEC_VALUE(x)
 145 +#define SUNXI_TIME_SET_MIN_VALUE(x)            SUNXI_SET(x, SUNXI_MASK_SM, 8)
 146 +#define SUNXI_TIME_SET_HOUR_VALUE(x)           SUNXI_SET(x, SUNXI_MASK_DH, 16)
 147 +
 148 +/* set alarm values */
 149 +#define SUNXI_ALRM_SET_SEC_VALUE(x)            SUNXI_ALRM_GET_SEC_VALUE(x)
 150 +#define SUNXI_ALRM_SET_MIN_VALUE(x)            SUNXI_SET(x, SUNXI_MASK_SM, 8)
 151 +#define SUNXI_ALRM_SET_HOUR_VALUE(x)           SUNXI_SET(x, SUNXI_MASK_DH, 16)
 152 +#define SUNXI_ALRM_SET_DAY_VALUE(x)            SUNXI_SET(x, SUNXI_MASK_D, 21)
 153 +
 154 +/* time unit conversions */
 155 +#define SEC_IN_MIN                             60
 156 +#define SEC_IN_HOUR                            (60 * SEC_IN_MIN)
 157 +#define SEC_IN_DAY                             (24 * SEC_IN_HOUR)
 158 +
 159 +struct sunxi_rtc_data_year {
 160 +       unsigned int min;               /* min year allowed */
 161 +       unsigned int max;               /* max year allowed */
 162 +       unsigned int off;               /* data year offset */
 163 +       unsigned int mask;
 164 +       unsigned char leap_shift;       /* bit shift to get the leap year */
 165 +};
 166 +
 167 +static struct sunxi_rtc_data_year data_year_param[] = {
 168 +       [0] = {
 169 +               .min            = 1970,
 170 +               .max            = 2100,
 171 +               .off            = 0,
 172 +               .mask           = 0x000000ff,
 173 +               .leap_shift     = 24,
 174 +       },
 175 +       [1] = {
 176 +               .min            = 2010,
 177 +               .max            = 2073,
 178 +               .off            = 110,
 179 +               .mask           = 0x0000003f,
 180 +               .leap_shift     = 22,
 181 +       },
 182 +};
 183 +
 184 +struct sunxi_rtc_dev {
 185 +       struct rtc_device *rtc;
 186 +       struct device *dev;
 187 +       struct sunxi_rtc_data_year *data_year;
 188 +       void __iomem *base;
 189 +       int irq;
 190 +};
 191 +
 192 +static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
 193 +{
 194 +       struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
 195 +       u32 val;
 196 +
 197 +       val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
 198 +
 199 +       if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
 200 +               val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
 201 +               writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
 202 +
 203 +               rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
 204 +
 205 +               return IRQ_HANDLED;
 206 +       }
 207 +
 208 +       return IRQ_NONE;
 209 +}
 210 +
 211 +static void sunxi_rtc_setaie(int to, struct sunxi_rtc_dev *chip)
 212 +{
 213 +       u32 alarm_val = 0;
 214 +       u32 alarm_irq_val = 0;
 215 +
 216 +       if (to) {
 217 +               alarm_val = readl(chip->base + SUNXI_ALRM_EN);
 218 +               alarm_val |= SUNXI_ALRM_EN_CNT_EN;
 219 +
 220 +               alarm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
 221 +               alarm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
 222 +       } else {
 223 +               writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
 224 +                               chip->base + SUNXI_ALRM_IRQ_STA);
 225 +       }
 226 +
 227 +       writel(alarm_val, chip->base + SUNXI_ALRM_EN);
 228 +       writel(alarm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
 229 +}
 230 +
 231 +static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
 232 +{
 233 +       struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
 234 +       struct rtc_time *alrm_tm = &alrm->time;
 235 +       u32 alarm;
 236 +       u32 alarm_en;
 237 +       u32 date;
 238 +
 239 +       alarm = readl(chip->base + SUNXI_ALRM_DHMS);
 240 +       date = readl(chip->base + SUNXI_RTC_YMD);
 241 +
 242 +       alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alarm);
 243 +       alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alarm);
 244 +       alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alarm);
 245 +
 246 +       alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
 247 +       alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
 248 +       alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
 249 +                       chip->data_year->mask);
 250 +
 251 +       alrm_tm->tm_year += chip->data_year->off;
 252 +       alrm_tm->tm_mon -= 1;
 253 +
 254 +       alarm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
 255 +       if (alarm_en & SUNXI_ALRM_EN_CNT_EN)
 256 +               alrm->enabled = 1;
 257 +
 258 +       return 0;
 259 +}
 260 +
 261 +static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
 262 +{
 263 +       struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
 264 +       u32 date, time;
 265 +       int t;
 266 +
 267 +       /* read again if the system was mid-updated
 268 +        */
 269 +       for (t = 0; t < 2; t++) {
 270 +               date = readl(chip->base + SUNXI_RTC_YMD);
 271 +               time = readl(chip->base + SUNXI_RTC_HMS);
 272 +
 273 +               rtc_tm->tm_sec  = SUNXI_TIME_GET_SEC_VALUE(time);
 274 +               rtc_tm->tm_min  = SUNXI_TIME_GET_MIN_VALUE(time);
 275 +               rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
 276 +
 277 +               rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
 278 +               rtc_tm->tm_mon  = SUNXI_DATE_GET_MON_VALUE(date);
 279 +               rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
 280 +                               chip->data_year->mask);
 281 +
 282 +               if (rtc_tm->tm_sec == 0)
 283 +                       msleep(500);
 284 +               else
 285 +                       break;
 286 +       }
 287 +
 288 +       rtc_tm->tm_year += chip->data_year->off;
 289 +       rtc_tm->tm_mon  -= 1;
 290 +
 291 +       return rtc_valid_tm(rtc_tm);
 292 +}
 293 +
 294 +static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 295 +{
 296 +       struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
 297 +       struct rtc_time *alrm_tm = &alrm->time;
 298 +       struct rtc_time tm_now;
 299 +       u32 alarm = 0;
 300 +       unsigned long time_now = 0;
 301 +       unsigned long time_set = 0;
 302 +       unsigned long time_gap = 0;
 303 +       unsigned long time_gap_day = 0;
 304 +       unsigned long time_gap_hour = 0;
 305 +       unsigned long time_gap_min = 0;
 306 +       int ret = 0;
 307 +
 308 +       ret = sunxi_rtc_gettime(dev, &tm_now);
 309 +       if (ret < 0) {
 310 +               dev_err(dev, "Error in getting time\n");
 311 +               return -EINVAL;
 312 +       }
 313 +
 314 +       rtc_tm_to_time(alrm_tm, &time_set);
 315 +       rtc_tm_to_time(&tm_now, &time_now);
 316 +       if (time_set <= time_now) {
 317 +               dev_err(dev, "Date to set in the past\n");
 318 +               return -EINVAL;
 319 +       }
 320 +
 321 +       time_gap = time_set - time_now;
 322 +       time_gap_day = time_gap / SEC_IN_DAY;
 323 +       time_gap -= time_gap_day * SEC_IN_DAY;
 324 +       time_gap_hour = time_gap / SEC_IN_HOUR;
 325 +       time_gap -= time_gap_hour * SEC_IN_HOUR;
 326 +       time_gap_min = time_gap / SEC_IN_MIN;
 327 +       time_gap -= time_gap_min * SEC_IN_MIN;
 328 +
 329 +       if (time_gap_day > 255) {
 330 +               dev_err(dev, "Day must be in the range 0 - 255\n");
 331 +               return -EINVAL;
 332 +       }
 333 +
 334 +       sunxi_rtc_setaie(0, chip);
 335 +       writel(0, chip->base + SUNXI_ALRM_DHMS);
 336 +       usleep_range(100, 300);
 337 +
 338 +       alarm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
 339 +               SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
 340 +               SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
 341 +               SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
 342 +       writel(alarm, chip->base + SUNXI_ALRM_DHMS);
 343 +
 344 +       writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
 345 +       writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
 346 +
 347 +       sunxi_rtc_setaie(alrm->enabled, chip);
 348 +
 349 +       return 0;
 350 +}
 351 +
 352 +static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
 353 +{
 354 +       struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
 355 +       u32 date = 0;
 356 +       u32 time = 0;
 357 +       int year;
 358 +       int t;
 359 +
 360 +       year = rtc_tm->tm_year + 1900;
 361 +       if (year < chip->data_year->min || year > chip->data_year->max) {
 362 +               dev_err(dev, "rtc only supports year in range %d - %d\n",
 363 +                               chip->data_year->min, chip->data_year->max);
 364 +               return -EINVAL;
 365 +       }
 366 +
 367 +       rtc_tm->tm_year -= chip->data_year->off;
 368 +       rtc_tm->tm_mon += 1;
 369 +
 370 +       date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
 371 +               SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
 372 +               SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
 373 +                               chip->data_year->mask);
 374 +
 375 +       if (is_leap_year(year))
 376 +               date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
 377 +
 378 +       time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
 379 +               SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min)  |
 380 +               SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
 381 +
 382 +       writel(0, chip->base + SUNXI_RTC_HMS);
 383 +       writel(0, chip->base + SUNXI_RTC_YMD);
 384 +
 385 +       writel(time, chip->base + SUNXI_RTC_HMS);
 386 +
 387 +       /* After writing the RCT HH-MM-SS register, the
 388 +        * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will be cleared until
 389 +        * the real writing operation is finished
 390 +        */
 391 +       for (t = 0; t < 3; t++) {
 392 +               if ((readl(chip->base + SUNXI_LOSC_CTRL) &
 393 +                       SUNXI_LOSC_CTRL_RTC_HMS_ACC) && --t)
 394 +                       break;
 395 +               else
 396 +                       msleep(50);
 397 +       }
 398 +       if (t == 0) {
 399 +               dev_err(dev, "Failed to set rtc time.\n");
 400 +               return -1;
 401 +       }
 402 +
 403 +       writel(date, chip->base + SUNXI_RTC_YMD);
 404 +
 405 +       /* After writing the RCT YY-MM-DD register, the
 406 +        * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will be cleared until
 407 +        * the real writing operation is finished
 408 +        */
 409 +       for (t = 0; t < 3; t++) {
 410 +               if ((readl(chip->base + SUNXI_LOSC_CTRL) &
 411 +                       SUNXI_LOSC_CTRL_RTC_YMD_ACC) && --t)
 412 +                       break;
 413 +               else
 414 +                       msleep(50);
 415 +       }
 416 +       if (t == 0) {
 417 +               dev_err(dev, "Failed to set rtc date.\n");
 418 +               return -1;
 419 +       }
 420 +
 421 +       /* wait about 70us to make sure the the time is really written into
 422 +        * target */
 423 +       usleep_range(70, 100);
 424 +
 425 +       return 0;
 426 +}
 427 +
 428 +static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 429 +{
 430 +       struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
 431 +
 432 +       if (!enabled)
 433 +               sunxi_rtc_setaie(enabled, chip);
 434 +
 435 +       return 0;
 436 +}
 437 +
 438 +static const struct rtc_class_ops sunxi_rtc_ops = {
 439 +       .read_time              = sunxi_rtc_gettime,
 440 +       .set_time               = sunxi_rtc_settime,
 441 +       .read_alarm             = sunxi_rtc_getalarm,
 442 +       .set_alarm              = sunxi_rtc_setalarm,
 443 +       .alarm_irq_enable       = sunxi_rtc_alarm_irq_enable
 444 +};
 445 +
 446 +static const struct of_device_id sunxi_rtc_dt_ids[] = {
 447 +       { .compatible = "allwinner,sun4i-rtc", .data = &data_year_param[0] },
 448 +       { .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
 449 +       { /* sentinel */ },
 450 +};
 451 +MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
 452 +
 453 +
 454 +static int sunxi_rtc_probe(struct platform_device *pdev)
 455 +{
 456 +       struct sunxi_rtc_dev *chip;
 457 +       struct resource *res;
 458 +       const struct of_device_id *of_id;
 459 +       int ret;
 460 +
 461 +       chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
 462 +       if (!chip)
 463 +               return -ENOMEM;
 464 +
 465 +       platform_set_drvdata(pdev, chip);
 466 +       chip->dev = &pdev->dev;
 467 +
 468 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 469 +       chip->base = devm_ioremap_resource(&pdev->dev, res);
 470 +       if (IS_ERR(chip->base))
 471 +               return PTR_ERR(chip->base);
 472 +
 473 +       chip->irq = platform_get_irq(pdev, 0);
 474 +       if (chip->irq < 0) {
 475 +               dev_err(&pdev->dev, "No IRQ resource\n");
 476 +               return chip->irq;
 477 +       }
 478 +       ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
 479 +                       0, dev_name(&pdev->dev), chip);
 480 +       if (ret) {
 481 +               dev_err(&pdev->dev, "Could not request IRQ\n");
 482 +               return ret;
 483 +       }
 484 +
 485 +       of_id = of_match_device(sunxi_rtc_dt_ids, &pdev->dev);
 486 +       if (!of_id) {
 487 +               dev_err(&pdev->dev, "Unable to setup RTC data\n");
 488 +               return -ENODEV;
 489 +       }
 490 +       chip->data_year = (struct sunxi_rtc_data_year *) of_id->data;
 491 +
 492 +       /* clear the alarm count value */
 493 +       writel(0, chip->base + SUNXI_ALRM_DHMS);
 494 +
 495 +       /* disable alarm, not generate irq pending */
 496 +       writel(0, chip->base + SUNXI_ALRM_EN);
 497 +
 498 +       /* disable alarm week/cnt irq, unset to cpu */
 499 +       writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
 500 +
 501 +       /* clear alarm week/cnt irq pending */
 502 +       writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base + SUNXI_ALRM_IRQ_STA);
 503 +
 504 +       chip->rtc = rtc_device_register("rtc-sunxi", &pdev->dev,
 505 +                       &sunxi_rtc_ops, THIS_MODULE);
 506 +       if (IS_ERR(chip->rtc)) {
 507 +               dev_err(&pdev->dev, "unable to register device\n");
 508 +               return PTR_ERR(chip->rtc);
 509 +       }
 510 +
 511 +       dev_info(&pdev->dev, "RTC enabled\n");
 512 +
 513 +       return 0;
 514 +}
 515 +
 516 +static int sunxi_rtc_remove(struct platform_device *pdev)
 517 +{
 518 +       struct sunxi_rtc_dev *chip = platform_get_drvdata(pdev);
 519 +
 520 +       rtc_device_unregister(chip->rtc);
 521 +
 522 +       return 0;
 523 +}
 524 +
 525 +static struct platform_driver sunxi_rtc_driver = {
 526 +       .probe          = sunxi_rtc_probe,
 527 +       .remove         = sunxi_rtc_remove,
 528 +       .driver         = {
 529 +               .name           = "sunxi-rtc",
 530 +               .owner          = THIS_MODULE,
 531 +               .of_match_table = sunxi_rtc_dt_ids,
 532 +       },
 533 +};
 534 +
 535 +module_platform_driver(sunxi_rtc_driver);
 536 +
 537 +MODULE_DESCRIPTION("sunxi RTC driver");
 538 +MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
 539 +MODULE_LICENSE("GPL");
 540 --
 541 1.8.4
 542