target/linux/sunxi/patches-3.13/119-dt-sunxi-add-pll5-pll6.patch

   1 From 6d3ca59232090bff1b5e1abfd3417a3859e47425 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:38 -0300
   4 Subject: [PATCH] ARM: sunxi: add PLL5 and PLL6 support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
  10 device trees.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  14 ---
  15  arch/arm/boot/dts/sun4i-a10.dtsi  | 19 +++++++++++++++++--
  16  arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++--
  17  arch/arm/boot/dts/sun5i-a13.dtsi  | 19 +++++++++++++++++--
  18  arch/arm/boot/dts/sun7i-a20.dtsi  | 28 ++++++++++++++++------------
  19  4 files changed, 67 insertions(+), 18 deletions(-)
  20
  21 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
  22 index 1d6346c..07564e9e 100644
  23 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  24 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  25 @@ -77,6 +77,22 @@
  26                         clocks = <&osc24M>;
  27                 };
  28
  29 +               pll5: pll5@01c20020 {
  30 +                       #clock-cells = <1>;
  31 +                       compatible = "allwinner,sun4i-pll5-clk";
  32 +                       reg = <0x01c20020 0x4>;
  33 +                       clocks = <&osc24M>;
  34 +                       clock-output-names = "pll5_ddr", "pll5_other";
  35 +               };
  36 +
  37 +               pll6: pll6@01c20028 {
  38 +                       #clock-cells = <1>;
  39 +                       compatible = "allwinner,sun4i-pll6-clk";
  40 +                       reg = <0x01c20028 0x4>;
  41 +                       clocks = <&osc24M>;
  42 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
  43 +               };
  44 +
  45                 /* dummy is 200M */
  46                 cpu: cpu@01c20054 {
  47                         #clock-cells = <0>;
  48 @@ -142,12 +158,11 @@
  49                                 "apb0_ir1", "apb0_keypad";
  50                 };
  51
  52 -               /* dummy is pll62 */
  53                 apb1_mux: apb1_mux@01c20058 {
  54                         #clock-cells = <0>;
  55                         compatible = "allwinner,sun4i-apb1-mux-clk";
  56                         reg = <0x01c20058 0x4>;
  57 -                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
  58 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
  59                 };
  60
  61                 apb1: apb1@01c20058 {
  62 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
  63 index 64d6d75..ca19362 100644
  64 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  65 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  66 @@ -74,6 +74,22 @@
  67                         clocks = <&osc24M>;
  68                 };
  69
  70 +               pll5: pll5@01c20020 {
  71 +                       #clock-cells = <1>;
  72 +                       compatible = "allwinner,sun4i-pll5-clk";
  73 +                       reg = <0x01c20020 0x4>;
  74 +                       clocks = <&osc24M>;
  75 +                       clock-output-names = "pll5_ddr", "pll5_other";
  76 +               };
  77 +
  78 +               pll6: pll6@01c20028 {
  79 +                       #clock-cells = <1>;
  80 +                       compatible = "allwinner,sun4i-pll6-clk";
  81 +                       reg = <0x01c20028 0x4>;
  82 +                       clocks = <&osc24M>;
  83 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
  84 +               };
  85 +
  86                 /* dummy is 200M */
  87                 cpu: cpu@01c20054 {
  88                         #clock-cells = <0>;
  89 @@ -134,12 +150,11 @@
  90                                 "apb0_ir", "apb0_keypad";
  91                 };
  92
  93 -               /* dummy is pll62 */
  94                 apb1_mux: apb1_mux@01c20058 {
  95                         #clock-cells = <0>;
  96                         compatible = "allwinner,sun4i-apb1-mux-clk";
  97                         reg = <0x01c20058 0x4>;
  98 -                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
  99 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 100                 };
 101
 102                 apb1: apb1@01c20058 {
 103 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
 104 index 2c355c8..9ac706a 100644
 105 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
 106 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
 107 @@ -74,6 +74,22 @@
 108                         clocks = <&osc24M>;
 109                 };
 110
 111 +               pll5: pll5@01c20020 {
 112 +                       #clock-cells = <1>;
 113 +                       compatible = "allwinner,sun4i-pll5-clk";
 114 +                       reg = <0x01c20020 0x4>;
 115 +                       clocks = <&osc24M>;
 116 +                       clock-output-names = "pll5_ddr", "pll5_other";
 117 +               };
 118 +
 119 +               pll6: pll6@01c20028 {
 120 +                       #clock-cells = <1>;
 121 +                       compatible = "allwinner,sun4i-pll6-clk";
 122 +                       reg = <0x01c20028 0x4>;
 123 +                       clocks = <&osc24M>;
 124 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
 125 +               };
 126 +
 127                 /* dummy is 200M */
 128                 cpu: cpu@01c20054 {
 129                         #clock-cells = <0>;
 130 @@ -132,12 +148,11 @@
 131                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
 132                 };
 133
 134 -               /* dummy is pll6 */
 135                 apb1_mux: apb1_mux@01c20058 {
 136                         #clock-cells = <0>;
 137                         compatible = "allwinner,sun4i-apb1-mux-clk";
 138                         reg = <0x01c20058 0x4>;
 139 -                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
 140 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 141                 };
 142
 143                 apb1: apb1@01c20058 {
 144 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
 145 index 18144f0..9176ed0 100644
 146 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
 147 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
 148 @@ -73,23 +73,27 @@
 149                         clocks = <&osc24M>;
 150                 };
 151
 152 -               /*
 153 -                * This is a dummy clock, to be used as placeholder on
 154 -                * other mux clocks when a specific parent clock is not
 155 -                * yet implemented. It should be dropped when the driver
 156 -                * is complete.
 157 -                */
 158 -               pll6: pll6 {
 159 -                       #clock-cells = <0>;
 160 -                       compatible = "fixed-clock";
 161 -                       clock-frequency = <0>;
 162 +               pll5: pll5@01c20020 {
 163 +                       #clock-cells = <1>;
 164 +                       compatible = "allwinner,sun4i-pll5-clk";
 165 +                       reg = <0x01c20020 0x4>;
 166 +                       clocks = <&osc24M>;
 167 +                       clock-output-names = "pll5_ddr", "pll5_other";
 168 +               };
 169 +
 170 +               pll6: pll6@01c20028 {
 171 +                       #clock-cells = <1>;
 172 +                       compatible = "allwinner,sun4i-pll6-clk";
 173 +                       reg = <0x01c20028 0x4>;
 174 +                       clocks = <&osc24M>;
 175 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
 176                 };
 177
 178                 cpu: cpu@01c20054 {
 179                         #clock-cells = <0>;
 180                         compatible = "allwinner,sun4i-cpu-clk";
 181                         reg = <0x01c20054 0x4>;
 182 -                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
 183 +                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 184                 };
 185
 186                 axi: axi@01c20054 {
 187 @@ -148,7 +152,7 @@
 188                         #clock-cells = <0>;
 189                         compatible = "allwinner,sun4i-apb1-mux-clk";
 190                         reg = <0x01c20058 0x4>;
 191 -                       clocks = <&osc24M>, <&pll6>, <&osc32k>;
 192 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 193                 };
 194
 195                 apb1: apb1@01c20058 {
 196 --
 197 1.8.5.1
 198