target/linux/sunxi/patches-3.13/145-clksrc-add-hstimer.patch

   1 From 3bf30f6381f9287eb99ce096bf2fa327a69c8a71 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Thu, 7 Nov 2013 12:01:48 +0100
   4 Subject: [PATCH] clocksource: Add Allwinner SoCs HS timers driver
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Most of the Allwinner SoCs (at this time, all but the A10) also have a
  10 High Speed timers that are not using the 24MHz oscillator as a source
  11 but rather the AHB clock running much faster.
  12
  13 The IP is slightly different between the A10s/A13 and the one used in
  14 the A20/A31, since the latter have 4 timers available, while the former
  15 have only 2 of them.
  16
  17 [dlezcano] : Fixed conflict with b788beda "Order Kconfig options
  18                 alphabetically"
  19
  20 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  21 Tested-by: Emilio López <emilio@elopez.com.ar>
  22 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
  23 ---
  24  .../bindings/timer/allwinner,sun5i-a13-hstimer.txt |  22 +++
  25  arch/arm/mach-sunxi/Kconfig                        |   1 +
  26  drivers/clocksource/Kconfig                        |   4 +
  27  drivers/clocksource/Makefile                       |   1 +
  28  drivers/clocksource/timer-sun5i.c                  | 192 +++++++++++++++++++++
  29  5 files changed, 220 insertions(+)
  30  create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  31  create mode 100644 drivers/clocksource/timer-sun5i.c
  32
  33 diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  34 new file mode 100644
  35 index 0000000..7c26154
  36 --- /dev/null
  37 +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  38 @@ -0,0 +1,22 @@
  39 +Allwinner SoCs High Speed Timer Controller
  40 +
  41 +Required properties:
  42 +
  43 +- compatible : should be "allwinner,sun5i-a13-hstimer" or
  44 +               "allwinner,sun7i-a20-hstimer"
  45 +- reg : Specifies base physical address and size of the registers.
  46 +- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
  47 +               one)
  48 +- clocks: phandle to the source clock (usually the AHB clock)
  49 +
  50 +Example:
  51 +
  52 +timer@01c60000 {
  53 +       compatible = "allwinner,sun7i-a20-hstimer";
  54 +       reg = <0x01c60000 0x1000>;
  55 +       interrupts = <0 51 1>,
  56 +                    <0 52 1>,
  57 +                    <0 53 1>,
  58 +                    <0 54 1>;
  59 +       clocks = <&ahb1_gates 19>;
  60 +};
  61 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
  62 index e3457b9..547004c 100644
  63 --- a/arch/arm/mach-sunxi/Kconfig
  64 +++ b/arch/arm/mach-sunxi/Kconfig
  65 @@ -13,3 +13,4 @@ config ARCH_SUNXI
  66         select PINCTRL_SUNXI
  67         select SPARSE_IRQ
  68         select SUN4I_TIMER
  69 +       select SUN5I_HSTIMER
  70 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
  71 index 634c4d6..cd6950f 100644
  72 --- a/drivers/clocksource/Kconfig
  73 +++ b/drivers/clocksource/Kconfig
  74 @@ -37,6 +37,10 @@ config SUN4I_TIMER
  75         select CLKSRC_MMIO
  76         bool
  77
  78 +config SUN5I_HSTIMER
  79 +       select CLKSRC_MMIO
  80 +       bool
  81 +
  82  config VT8500_TIMER
  83         bool
  84
  85 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
  86 index 33621ef..358358d 100644
  87 --- a/drivers/clocksource/Makefile
  88 +++ b/drivers/clocksource/Makefile
  89 @@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_MOXART)     += moxart_timer.o
  90  obj-$(CONFIG_ARCH_MXS)         += mxs_timer.o
  91  obj-$(CONFIG_ARCH_PRIMA2)      += timer-prima2.o
  92  obj-$(CONFIG_SUN4I_TIMER)      += sun4i_timer.o
  93 +obj-$(CONFIG_SUN5I_HSTIMER)    += timer-sun5i.o
  94  obj-$(CONFIG_ARCH_TEGRA)       += tegra20_timer.o
  95  obj-$(CONFIG_VT8500_TIMER)     += vt8500_timer.o
  96  obj-$(CONFIG_ARCH_NSPIRE)      += zevio-timer.o
  97 diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
  98 new file mode 100644
  99 index 0000000..bddc522
 100 --- /dev/null
 101 +++ b/drivers/clocksource/timer-sun5i.c
 102 @@ -0,0 +1,192 @@
 103 +/*
 104 + * Allwinner SoCs hstimer driver.
 105 + *
 106 + * Copyright (C) 2013 Maxime Ripard
 107 + *
 108 + * Maxime Ripard <maxime.ripard@free-electrons.com>
 109 + *
 110 + * This file is licensed under the terms of the GNU General Public
 111 + * License version 2.  This program is licensed "as is" without any
 112 + * warranty of any kind, whether express or implied.
 113 + */
 114 +
 115 +#include <linux/clk.h>
 116 +#include <linux/clockchips.h>
 117 +#include <linux/delay.h>
 118 +#include <linux/interrupt.h>
 119 +#include <linux/irq.h>
 120 +#include <linux/irqreturn.h>
 121 +#include <linux/sched_clock.h>
 122 +#include <linux/of.h>
 123 +#include <linux/of_address.h>
 124 +#include <linux/of_irq.h>
 125 +
 126 +#define TIMER_IRQ_EN_REG               0x00
 127 +#define TIMER_IRQ_EN(val)                      BIT(val)
 128 +#define TIMER_IRQ_ST_REG               0x04
 129 +#define TIMER_CTL_REG(val)             (0x20 * (val) + 0x10)
 130 +#define TIMER_CTL_ENABLE                       BIT(0)
 131 +#define TIMER_CTL_RELOAD                       BIT(1)
 132 +#define TIMER_CTL_CLK_PRES(val)                        (((val) & 0x7) << 4)
 133 +#define TIMER_CTL_ONESHOT                      BIT(7)
 134 +#define TIMER_INTVAL_LO_REG(val)       (0x20 * (val) + 0x14)
 135 +#define TIMER_INTVAL_HI_REG(val)       (0x20 * (val) + 0x18)
 136 +#define TIMER_CNTVAL_LO_REG(val)       (0x20 * (val) + 0x1c)
 137 +#define TIMER_CNTVAL_HI_REG(val)       (0x20 * (val) + 0x20)
 138 +
 139 +#define TIMER_SYNC_TICKS       3
 140 +
 141 +static void __iomem *timer_base;
 142 +static u32 ticks_per_jiffy;
 143 +
 144 +/*
 145 + * When we disable a timer, we need to wait at least for 2 cycles of
 146 + * the timer source clock. We will use for that the clocksource timer
 147 + * that is already setup and runs at the same frequency than the other
 148 + * timers, and we never will be disabled.
 149 + */
 150 +static void sun5i_clkevt_sync(void)
 151 +{
 152 +       u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
 153 +
 154 +       while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
 155 +               cpu_relax();
 156 +}
 157 +
 158 +static void sun5i_clkevt_time_stop(u8 timer)
 159 +{
 160 +       u32 val = readl(timer_base + TIMER_CTL_REG(timer));
 161 +       writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
 162 +
 163 +       sun5i_clkevt_sync();
 164 +}
 165 +
 166 +static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
 167 +{
 168 +       writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
 169 +}
 170 +
 171 +static void sun5i_clkevt_time_start(u8 timer, bool periodic)
 172 +{
 173 +       u32 val = readl(timer_base + TIMER_CTL_REG(timer));
 174 +
 175 +       if (periodic)
 176 +               val &= ~TIMER_CTL_ONESHOT;
 177 +       else
 178 +               val |= TIMER_CTL_ONESHOT;
 179 +
 180 +       writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
 181 +              timer_base + TIMER_CTL_REG(timer));
 182 +}
 183 +
 184 +static void sun5i_clkevt_mode(enum clock_event_mode mode,
 185 +                             struct clock_event_device *clk)
 186 +{
 187 +       switch (mode) {
 188 +       case CLOCK_EVT_MODE_PERIODIC:
 189 +               sun5i_clkevt_time_stop(0);
 190 +               sun5i_clkevt_time_setup(0, ticks_per_jiffy);
 191 +               sun5i_clkevt_time_start(0, true);
 192 +               break;
 193 +       case CLOCK_EVT_MODE_ONESHOT:
 194 +               sun5i_clkevt_time_stop(0);
 195 +               sun5i_clkevt_time_start(0, false);
 196 +               break;
 197 +       case CLOCK_EVT_MODE_UNUSED:
 198 +       case CLOCK_EVT_MODE_SHUTDOWN:
 199 +       default:
 200 +               sun5i_clkevt_time_stop(0);
 201 +               break;
 202 +       }
 203 +}
 204 +
 205 +static int sun5i_clkevt_next_event(unsigned long evt,
 206 +                                  struct clock_event_device *unused)
 207 +{
 208 +       sun5i_clkevt_time_stop(0);
 209 +       sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
 210 +       sun5i_clkevt_time_start(0, false);
 211 +
 212 +       return 0;
 213 +}
 214 +
 215 +static struct clock_event_device sun5i_clockevent = {
 216 +       .name = "sun5i_tick",
 217 +       .rating = 340,
 218 +       .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 219 +       .set_mode = sun5i_clkevt_mode,
 220 +       .set_next_event = sun5i_clkevt_next_event,
 221 +};
 222 +
 223 +
 224 +static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
 225 +{
 226 +       struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 227 +
 228 +       writel(0x1, timer_base + TIMER_IRQ_ST_REG);
 229 +       evt->event_handler(evt);
 230 +
 231 +       return IRQ_HANDLED;
 232 +}
 233 +
 234 +static struct irqaction sun5i_timer_irq = {
 235 +       .name = "sun5i_timer0",
 236 +       .flags = IRQF_TIMER | IRQF_IRQPOLL,
 237 +       .handler = sun5i_timer_interrupt,
 238 +       .dev_id = &sun5i_clockevent,
 239 +};
 240 +
 241 +static u32 sun5i_timer_sched_read(void)
 242 +{
 243 +       return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1));
 244 +}
 245 +
 246 +static void __init sun5i_timer_init(struct device_node *node)
 247 +{
 248 +       unsigned long rate;
 249 +       struct clk *clk;
 250 +       int ret, irq;
 251 +       u32 val;
 252 +
 253 +       timer_base = of_iomap(node, 0);
 254 +       if (!timer_base)
 255 +               panic("Can't map registers");
 256 +
 257 +       irq = irq_of_parse_and_map(node, 0);
 258 +       if (irq <= 0)
 259 +               panic("Can't parse IRQ");
 260 +
 261 +       clk = of_clk_get(node, 0);
 262 +       if (IS_ERR(clk))
 263 +               panic("Can't get timer clock");
 264 +       clk_prepare_enable(clk);
 265 +       rate = clk_get_rate(clk);
 266 +
 267 +       writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
 268 +       writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
 269 +              timer_base + TIMER_CTL_REG(1));
 270 +
 271 +       setup_sched_clock(sun5i_timer_sched_read, 32, rate);
 272 +       clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
 273 +                             rate, 340, 32, clocksource_mmio_readl_down);
 274 +
 275 +       ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
 276 +
 277 +       ret = setup_irq(irq, &sun5i_timer_irq);
 278 +       if (ret)
 279 +               pr_warn("failed to setup irq %d\n", irq);
 280 +
 281 +       /* Enable timer0 interrupt */
 282 +       val = readl(timer_base + TIMER_IRQ_EN_REG);
 283 +       writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 284 +
 285 +       sun5i_clockevent.cpumask = cpu_possible_mask;
 286 +       sun5i_clockevent.irq = irq;
 287 +
 288 +       clockevents_config_and_register(&sun5i_clockevent, rate,
 289 +                                       TIMER_SYNC_TICKS, 0xffffffff);
 290 +}
 291 +CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
 292 +                      sun5i_timer_init);
 293 +CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
 294 +                      sun5i_timer_init);
 295 --
 296 1.8.5.1
 297