target/linux/sunxi/patches-3.13/261-dt-sun6i-add-pll6-and-spi.patch

   1 From b0a09c756bf6e0b89d6b88a7620ba4cd86b1895b Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Wed, 5 Feb 2014 14:05:04 +0100
   4 Subject: [PATCH] ARM: sun6i: dt: Add PLL6 and SPI module clocks
   5
   6 The module clocks in the A31 are still compatible with the A10 one. Add the SPI
   7 module clocks and the PLL6 in the device tree to allow their use by the SPI
   8 controllers.
   9
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  arch/arm/boot/dts/sun6i-a31.dtsi | 46 ++++++++++++++++++++++++++++++++--------
  13  1 file changed, 37 insertions(+), 9 deletions(-)
  14
  15 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
  16 index 092bf97..93d7bb6 100644
  17 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
  18 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
  19 @@ -83,16 +83,12 @@
  20                         clocks = <&osc24M>;
  21                 };
  22
  23 -               /*
  24 -                * This is a dummy clock, to be used as placeholder on
  25 -                * other mux clocks when a specific parent clock is not
  26 -                * yet implemented. It should be dropped when the driver
  27 -                * is complete.
  28 -                */
  29 -               pll6: pll6 {
  30 +               pll6: clk@01c20028 {
  31                         #clock-cells = <0>;
  32 -                       compatible = "fixed-clock";
  33 -                       clock-frequency = <0>;
  34 +                       compatible = "allwinner,sun6i-a31-pll6-clk";
  35 +                       reg = <0x01c20028 0x4>;
  36 +                       clocks = <&osc24M>;
  37 +                       clock-output-names = "pll6";
  38                 };
  39
  40                 cpu: cpu@01c20050 {
  41 @@ -192,6 +188,38 @@
  42                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
  43                                         "apb2_uart4", "apb2_uart5";
  44                 };
  45 +
  46 +               spi0_clk: clk@01c200a0 {
  47 +                       #clock-cells = <0>;
  48 +                       compatible = "allwinner,sun4i-mod0-clk";
  49 +                       reg = <0x01c200a0 0x4>;
  50 +                       clocks = <&osc24M>, <&pll6>;
  51 +                       clock-output-names = "spi0";
  52 +               };
  53 +
  54 +               spi1_clk: clk@01c200a4 {
  55 +                       #clock-cells = <0>;
  56 +                       compatible = "allwinner,sun4i-mod0-clk";
  57 +                       reg = <0x01c200a4 0x4>;
  58 +                       clocks = <&osc24M>, <&pll6>;
  59 +                       clock-output-names = "spi1";
  60 +               };
  61 +
  62 +               spi2_clk: clk@01c200a8 {
  63 +                       #clock-cells = <0>;
  64 +                       compatible = "allwinner,sun4i-mod0-clk";
  65 +                       reg = <0x01c200a8 0x4>;
  66 +                       clocks = <&osc24M>, <&pll6>;
  67 +                       clock-output-names = "spi2";
  68 +               };
  69 +
  70 +               spi3_clk: clk@01c200ac {
  71 +                       #clock-cells = <0>;
  72 +                       compatible = "allwinner,sun4i-mod0-clk";
  73 +                       reg = <0x01c200ac 0x4>;
  74 +                       clocks = <&osc24M>, <&pll6>;
  75 +                       clock-output-names = "spi3";
  76 +               };
  77         };
  78
  79         soc@01c00000 {
  80 --
  81 1.8.5.5
  82