target/linux/sunxi/patches-3.14/176-clk-sun5i-add-support-for-reset-ctrler.patch

   1 From 3ec31fa2ce161d35f787354037f94d9d22d825d1 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Fri, 20 Dec 2013 22:41:08 +0100
   4 Subject: [PATCH] clocksource: sun5i: Add support for reset controller
   5
   6 The Allwinner A31 that uses this timer has the timer IP asserted in reset.
   7 Add an optional reset property to the DT, and deassert the timer from reset if
   8 it's there.
   9
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt       | 4 ++++
  13  drivers/clocksource/timer-sun5i.c                                   | 6 ++++++
  14  2 files changed, 10 insertions(+)
  15
  16 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  17 +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  18 @@ -9,6 +9,9 @@ Required properties:
  19                 one)
  20  - clocks: phandle to the source clock (usually the AHB clock)
  21
  22 +Optionnal properties:
  23 +- resets: phandle to a reset controller asserting the timer
  24 +
  25  Example:
  26
  27  timer@01c60000 {
  28 @@ -19,4 +22,5 @@ timer@01c60000 {
  29                      <0 53 1>,
  30                      <0 54 1>;
  31         clocks = <&ahb1_gates 19>;
  32 +       resets = <&ahb1rst 19>;
  33  };
  34 --- a/drivers/clocksource/timer-sun5i.c
  35 +++ b/drivers/clocksource/timer-sun5i.c
  36 @@ -16,6 +16,7 @@
  37  #include <linux/interrupt.h>
  38  #include <linux/irq.h>
  39  #include <linux/irqreturn.h>
  40 +#include <linux/reset.h>
  41  #include <linux/sched_clock.h>
  42  #include <linux/of.h>
  43  #include <linux/of_address.h>
  44 @@ -143,6 +144,7 @@ static u64 sun5i_timer_sched_read(void)
  45
  46  static void __init sun5i_timer_init(struct device_node *node)
  47  {
  48 +       struct reset_control *rstc;
  49         unsigned long rate;
  50         struct clk *clk;
  51         int ret, irq;
  52 @@ -162,6 +164,10 @@ static void __init sun5i_timer_init(stru
  53         clk_prepare_enable(clk);
  54         rate = clk_get_rate(clk);
  55
  56 +       rstc = of_reset_control_get(node, NULL);
  57 +       if (!IS_ERR(rstc))
  58 +               reset_control_deassert(rstc);
  59 +
  60         writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
  61         writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
  62                timer_base + TIMER_CTL_REG(1));