target/linux/sunxi/patches-3.14/196-usb-add-sunxi-phy-driver.patch

   1 From 56feaa546c5ce4152fe14f725e9fc6b85f8a565b Mon Sep 17 00:00:00 2001
   2 From: Hans de Goede <hdegoede@redhat.com>
   3 Date: Sat, 4 Jan 2014 23:56:17 +0100
   4 Subject: [PATCH] PHY: sunxi: Add driver for sunxi usb phy
   5
   6 The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
   7 through a single set of registers. Besides this there are also some other
   8 phy related bits which need poking, which are per phy, but shared between the
   9 ohci and ehci controllers, so these are also controlled from this new phy
  10 driver.
  11
  12 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  14 ---
  15  .../devicetree/bindings/phy/sun4i-usb-phy.txt      |  26 ++
  16  drivers/phy/Kconfig                                |  11 +
  17  drivers/phy/Makefile                               |   1 +
  18  drivers/phy/phy-sun4i-usb.c                        | 331 +++++++++++++++++++++
  19  4 files changed, 369 insertions(+)
  20  create mode 100644 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
  21  create mode 100644 drivers/phy/phy-sun4i-usb.c
  22
  23 --- /dev/null
  24 +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
  25 @@ -0,0 +1,26 @@
  26 +Allwinner sun4i USB PHY
  27 +-----------------------
  28 +
  29 +Required properties:
  30 +- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
  31 +  "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
  32 +- reg : a list of offset + length pairs
  33 +- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
  34 +- #phy-cells : from the generic phy bindings, must be 1
  35 +- clocks : phandle + clock specifier for the phy clock
  36 +- clock-names : "usb_phy"
  37 +- resets : a list of phandle + reset specifier pairs
  38 +- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"
  39 +
  40 +Example:
  41 +       usbphy: phy@0x01c13400 {
  42 +               #phy-cells = <1>;
  43 +               compatible = "allwinner,sun4i-a10-usb-phy";
  44 +               /* phy base regs, phy1 pmu reg, phy2 pmu reg */
  45 +               reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
  46 +               reg-names = "phy_ctrl", "pmu1", "pmu2";
  47 +               clocks = <&usb_clk 8>;
  48 +               clock-names = "usb_phy";
  49 +               resets = <&usb_clk 1>, <&usb_clk 2>;
  50 +               reset-names = "usb1_reset", "usb2_reset";
  51 +       };
  52 --- a/drivers/phy/Kconfig
  53 +++ b/drivers/phy/Kconfig
  54 @@ -65,4 +65,15 @@ config BCM_KONA_USB2_PHY
  55         help
  56           Enable this to support the Broadcom Kona USB 2.0 PHY.
  57
  58 +config PHY_SUN4I_USB
  59 +       tristate "Allwinner sunxi SoC USB PHY driver"
  60 +       depends on ARCH_SUNXI && HAS_IOMEM && OF
  61 +       select GENERIC_PHY
  62 +       help
  63 +         Enable this to support the transceiver that is part of Allwinner
  64 +         sunxi SoCs.
  65 +
  66 +         This driver controls the entire USB PHY block, both the USB OTG
  67 +         parts, as well as the 2 regular USB 2 host PHYs.
  68 +
  69  endmenu
  70 --- a/drivers/phy/Makefile
  71 +++ b/drivers/phy/Makefile
  72 @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)     += p
  73  obj-$(CONFIG_PHY_MVEBU_SATA)           += phy-mvebu-sata.o
  74  obj-$(CONFIG_OMAP_USB2)                        += phy-omap-usb2.o
  75  obj-$(CONFIG_TWL4030_USB)              += phy-twl4030-usb.o
  76 +obj-$(CONFIG_PHY_SUN4I_USB)            += phy-sun4i-usb.o
  77 --- /dev/null
  78 +++ b/drivers/phy/phy-sun4i-usb.c
  79 @@ -0,0 +1,331 @@
  80 +/*
  81 + * Allwinner sun4i USB phy driver
  82 + *
  83 + * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
  84 + *
  85 + * Based on code from
  86 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  87 + *
  88 + * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
  89 + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  90 + * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  91 + *
  92 + * This program is free software; you can redistribute it and/or modify
  93 + * it under the terms of the GNU General Public License as published by
  94 + * the Free Software Foundation; either version 2 of the License, or
  95 + * (at your option) any later version.
  96 + *
  97 + * This program is distributed in the hope that it will be useful,
  98 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  99 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 100 + * GNU General Public License for more details.
 101 + */
 102 +
 103 +#include <linux/clk.h>
 104 +#include <linux/io.h>
 105 +#include <linux/kernel.h>
 106 +#include <linux/module.h>
 107 +#include <linux/mutex.h>
 108 +#include <linux/of.h>
 109 +#include <linux/of_address.h>
 110 +#include <linux/phy/phy.h>
 111 +#include <linux/platform_device.h>
 112 +#include <linux/regulator/consumer.h>
 113 +#include <linux/reset.h>
 114 +
 115 +#define REG_ISCR                       0x00
 116 +#define REG_PHYCTL                     0x04
 117 +#define REG_PHYBIST                    0x08
 118 +#define REG_PHYTUNE                    0x0c
 119 +
 120 +#define PHYCTL_DATA                    BIT(7)
 121 +
 122 +#define SUNXI_AHB_ICHR8_EN             BIT(10)
 123 +#define SUNXI_AHB_INCR4_BURST_EN       BIT(9)
 124 +#define SUNXI_AHB_INCRX_ALIGN_EN       BIT(8)
 125 +#define SUNXI_ULPI_BYPASS_EN           BIT(0)
 126 +
 127 +/* Common Control Bits for Both PHYs */
 128 +#define PHY_PLL_BW                     0x03
 129 +#define PHY_RES45_CAL_EN               0x0c
 130 +
 131 +/* Private Control Bits for Each PHY */
 132 +#define PHY_TX_AMPLITUDE_TUNE          0x20
 133 +#define PHY_TX_SLEWRATE_TUNE           0x22
 134 +#define PHY_VBUSVALID_TH_SEL           0x25
 135 +#define PHY_PULLUP_RES_SEL             0x27
 136 +#define PHY_OTG_FUNC_EN                        0x28
 137 +#define PHY_VBUS_DET_EN                        0x29
 138 +#define PHY_DISCON_TH_SEL              0x2a
 139 +
 140 +#define MAX_PHYS                       3
 141 +
 142 +struct sun4i_usb_phy_data {
 143 +       struct clk *clk;
 144 +       void __iomem *base;
 145 +       struct mutex mutex;
 146 +       int num_phys;
 147 +       u32 disc_thresh;
 148 +       struct sun4i_usb_phy {
 149 +               struct phy *phy;
 150 +               void __iomem *pmu;
 151 +               struct regulator *vbus;
 152 +               struct reset_control *reset;
 153 +               int index;
 154 +       } phys[MAX_PHYS];
 155 +};
 156 +
 157 +#define to_sun4i_usb_phy_data(phy) \
 158 +       container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
 159 +
 160 +static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
 161 +                               int len)
 162 +{
 163 +       struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
 164 +       u32 temp, usbc_bit = BIT(phy->index * 2);
 165 +       int i;
 166 +
 167 +       mutex_lock(&phy_data->mutex);
 168 +
 169 +       for (i = 0; i < len; i++) {
 170 +               temp = readl(phy_data->base + REG_PHYCTL);
 171 +
 172 +               /* clear the address portion */
 173 +               temp &= ~(0xff << 8);
 174 +
 175 +               /* set the address */
 176 +               temp |= ((addr + i) << 8);
 177 +               writel(temp, phy_data->base + REG_PHYCTL);
 178 +
 179 +               /* set the data bit and clear usbc bit*/
 180 +               temp = readb(phy_data->base + REG_PHYCTL);
 181 +               if (data & 0x1)
 182 +                       temp |= PHYCTL_DATA;
 183 +               else
 184 +                       temp &= ~PHYCTL_DATA;
 185 +               temp &= ~usbc_bit;
 186 +               writeb(temp, phy_data->base + REG_PHYCTL);
 187 +
 188 +               /* pulse usbc_bit */
 189 +               temp = readb(phy_data->base + REG_PHYCTL);
 190 +               temp |= usbc_bit;
 191 +               writeb(temp, phy_data->base + REG_PHYCTL);
 192 +
 193 +               temp = readb(phy_data->base + REG_PHYCTL);
 194 +               temp &= ~usbc_bit;
 195 +               writeb(temp, phy_data->base + REG_PHYCTL);
 196 +
 197 +               data >>= 1;
 198 +       }
 199 +       mutex_unlock(&phy_data->mutex);
 200 +}
 201 +
 202 +static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
 203 +{
 204 +       u32 bits, reg_value;
 205 +
 206 +       if (!phy->pmu)
 207 +               return;
 208 +
 209 +       bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 210 +               SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 211 +
 212 +       reg_value = readl(phy->pmu);
 213 +
 214 +       if (enable)
 215 +               reg_value |= bits;
 216 +       else
 217 +               reg_value &= ~bits;
 218 +
 219 +       writel(reg_value, phy->pmu);
 220 +}
 221 +
 222 +static int sun4i_usb_phy_init(struct phy *_phy)
 223 +{
 224 +       struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 225 +       struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 226 +       int ret;
 227 +
 228 +       ret = clk_prepare_enable(data->clk);
 229 +       if (ret)
 230 +               return ret;
 231 +
 232 +       ret = reset_control_deassert(phy->reset);
 233 +       if (ret) {
 234 +               clk_disable_unprepare(data->clk);
 235 +               return ret;
 236 +       }
 237 +
 238 +       /* Adjust PHY's magnitude and rate */
 239 +       sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
 240 +
 241 +       /* Disconnect threshold adjustment */
 242 +       sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
 243 +
 244 +       sun4i_usb_phy_passby(phy, 1);
 245 +
 246 +       return 0;
 247 +}
 248 +
 249 +static int sun4i_usb_phy_exit(struct phy *_phy)
 250 +{
 251 +       struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 252 +       struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 253 +
 254 +       sun4i_usb_phy_passby(phy, 0);
 255 +       reset_control_assert(phy->reset);
 256 +       clk_disable_unprepare(data->clk);
 257 +
 258 +       return 0;
 259 +}
 260 +
 261 +static int sun4i_usb_phy_power_on(struct phy *_phy)
 262 +{
 263 +       struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 264 +       int ret = 0;
 265 +
 266 +       if (phy->vbus)
 267 +               ret = regulator_enable(phy->vbus);
 268 +
 269 +       return ret;
 270 +}
 271 +
 272 +static int sun4i_usb_phy_power_off(struct phy *_phy)
 273 +{
 274 +       struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
 275 +
 276 +       if (phy->vbus)
 277 +               regulator_disable(phy->vbus);
 278 +
 279 +       return 0;
 280 +}
 281 +
 282 +static struct phy_ops sun4i_usb_phy_ops = {
 283 +       .init           = sun4i_usb_phy_init,
 284 +       .exit           = sun4i_usb_phy_exit,
 285 +       .power_on       = sun4i_usb_phy_power_on,
 286 +       .power_off      = sun4i_usb_phy_power_off,
 287 +       .owner          = THIS_MODULE,
 288 +};
 289 +
 290 +static struct phy *sun4i_usb_phy_xlate(struct device *dev,
 291 +                                       struct of_phandle_args *args)
 292 +{
 293 +       struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
 294 +
 295 +       if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys))
 296 +               return ERR_PTR(-ENODEV);
 297 +
 298 +       return data->phys[args->args[0]].phy;
 299 +}
 300 +
 301 +static int sun4i_usb_phy_probe(struct platform_device *pdev)
 302 +{
 303 +       struct sun4i_usb_phy_data *data;
 304 +       struct device *dev = &pdev->dev;
 305 +       struct device_node *np = dev->of_node;
 306 +       void __iomem *pmu = NULL;
 307 +       struct phy_provider *phy_provider;
 308 +       struct reset_control *reset;
 309 +       struct regulator *vbus;
 310 +       struct resource *res;
 311 +       struct phy *phy;
 312 +       char name[16];
 313 +       int i;
 314 +
 315 +       data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 316 +       if (!data)
 317 +               return -ENOMEM;
 318 +
 319 +       mutex_init(&data->mutex);
 320 +
 321 +       if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy"))
 322 +               data->num_phys = 2;
 323 +       else
 324 +               data->num_phys = 3;
 325 +
 326 +       if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy"))
 327 +               data->disc_thresh = 3;
 328 +       else
 329 +               data->disc_thresh = 2;
 330 +
 331 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
 332 +       data->base = devm_ioremap_resource(dev, res);
 333 +       if (IS_ERR(data->base))
 334 +               return PTR_ERR(data->base);
 335 +
 336 +       data->clk = devm_clk_get(dev, "usb_phy");
 337 +       if (IS_ERR(data->clk)) {
 338 +               dev_err(dev, "could not get usb_phy clock\n");
 339 +               return PTR_ERR(data->clk);
 340 +       }
 341 +
 342 +       /* Skip 0, 0 is the phy for otg which is not yet supported. */
 343 +       for (i = 1; i < data->num_phys; i++) {
 344 +               snprintf(name, sizeof(name), "usb%d_vbus", i);
 345 +               vbus = devm_regulator_get_optional(dev, name);
 346 +               if (IS_ERR(vbus)) {
 347 +                       if (PTR_ERR(vbus) == -EPROBE_DEFER)
 348 +                               return -EPROBE_DEFER;
 349 +                       vbus = NULL;
 350 +               }
 351 +
 352 +               snprintf(name, sizeof(name), "usb%d_reset", i);
 353 +               reset = devm_reset_control_get(dev, name);
 354 +               if (IS_ERR(reset)) {
 355 +                       dev_err(dev, "failed to get reset %s\n", name);
 356 +                       return PTR_ERR(reset);
 357 +               }
 358 +
 359 +               if (i) { /* No pmu for usbc0 */
 360 +                       snprintf(name, sizeof(name), "pmu%d", i);
 361 +                       res = platform_get_resource_byname(pdev,
 362 +                                                       IORESOURCE_MEM, name);
 363 +                       pmu = devm_ioremap_resource(dev, res);
 364 +                       if (IS_ERR(pmu))
 365 +                               return PTR_ERR(pmu);
 366 +               }
 367 +
 368 +               phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
 369 +               if (IS_ERR(phy)) {
 370 +                       dev_err(dev, "failed to create PHY %d\n", i);
 371 +                       return PTR_ERR(phy);
 372 +               }
 373 +
 374 +               data->phys[i].phy = phy;
 375 +               data->phys[i].pmu = pmu;
 376 +               data->phys[i].vbus = vbus;
 377 +               data->phys[i].reset = reset;
 378 +               data->phys[i].index = i;
 379 +               phy_set_drvdata(phy, &data->phys[i]);
 380 +       }
 381 +
 382 +       dev_set_drvdata(dev, data);
 383 +       phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
 384 +       if (IS_ERR(phy_provider))
 385 +               return PTR_ERR(phy_provider);
 386 +
 387 +       return 0;
 388 +}
 389 +
 390 +static const struct of_device_id sun4i_usb_phy_of_match[] = {
 391 +       { .compatible = "allwinner,sun4i-a10-usb-phy" },
 392 +       { .compatible = "allwinner,sun5i-a13-usb-phy" },
 393 +       { .compatible = "allwinner,sun7i-a20-usb-phy" },
 394 +       { },
 395 +};
 396 +MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
 397 +
 398 +static struct platform_driver sun4i_usb_phy_driver = {
 399 +       .probe  = sun4i_usb_phy_probe,
 400 +       .driver = {
 401 +               .of_match_table = sun4i_usb_phy_of_match,
 402 +               .name  = "sun4i-usb-phy",
 403 +               .owner = THIS_MODULE,
 404 +       }
 405 +};
 406 +module_platform_driver(sun4i_usb_phy_driver);
 407 +
 408 +MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
 409 +MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
 410 +MODULE_LICENSE("GPL v2");