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oxnas: delete linux 4.1 support
[openwrt/openwrt.git] / target / linux / sunxi / patches-3.18 / 271-crypto-add-ss.patch
1 --- a/drivers/crypto/Kconfig
2 +++ b/drivers/crypto/Kconfig
3 @@ -437,4 +437,21 @@ config CRYPTO_DEV_QCE
4 hardware. To compile this driver as a module, choose M here. The
5 module will be called qcrypto.
6
7 +config CRYPTO_DEV_SUNXI_SS
8 + tristate "Support for Allwinner Security System cryptographic accelerator"
9 + depends on ARCH_SUNXI
10 + select CRYPTO_MD5
11 + select CRYPTO_SHA1
12 + select CRYPTO_AES
13 + select CRYPTO_DES
14 + select CRYPTO_BLKCIPHER
15 + help
16 + Some Allwinner SoC have a crypto accelerator named
17 + Security System. Select this if you want to use it.
18 + The Security System handle AES/DES/3DES ciphers in CBC mode
19 + and SHA1 and MD5 hash algorithms.
20 +
21 + To compile this driver as a module, choose M here: the module
22 + will be called sunxi-ss.
23 +
24 endif # CRYPTO_HW
25 --- a/drivers/crypto/Makefile
26 +++ b/drivers/crypto/Makefile
27 @@ -25,3 +25,4 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) += tali
28 obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
29 obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
30 obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
31 +obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss/
32 --- /dev/null
33 +++ b/drivers/crypto/sunxi-ss/Makefile
34 @@ -0,0 +1,2 @@
35 +obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss.o
36 +sunxi-ss-y += sunxi-ss-core.o sunxi-ss-hash.o sunxi-ss-cipher.o
37 --- /dev/null
38 +++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c
39 @@ -0,0 +1,489 @@
40 +/*
41 + * sunxi-ss-cipher.c - hardware cryptographic accelerator for Allwinner A20 SoC
42 + *
43 + * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
44 + *
45 + * This file add support for AES cipher with 128,192,256 bits
46 + * keysize in CBC mode.
47 + * Add support also for DES and 3DES in CBC mode.
48 + *
49 + * You could find the datasheet in Documentation/arm/sunxi/README
50 + *
51 + * This program is free software; you can redistribute it and/or modify
52 + * it under the terms of the GNU General Public License as published by
53 + * the Free Software Foundation; either version 2 of the License, or
54 + * (at your option) any later version.
55 + */
56 +#include "sunxi-ss.h"
57 +
58 +extern struct sunxi_ss_ctx *ss;
59 +
60 +static int sunxi_ss_cipher(struct ablkcipher_request *areq, u32 mode)
61 +{
62 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
63 + struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
64 + const char *cipher_type;
65 +
66 + if (areq->nbytes == 0)
67 + return 0;
68 +
69 + if (areq->info == NULL) {
70 + dev_err(ss->dev, "ERROR: Empty IV\n");
71 + return -EINVAL;
72 + }
73 +
74 + if (areq->src == NULL || areq->dst == NULL) {
75 + dev_err(ss->dev, "ERROR: Some SGs are NULL\n");
76 + return -EINVAL;
77 + }
78 +
79 + cipher_type = crypto_tfm_alg_name(crypto_ablkcipher_tfm(tfm));
80 +
81 + if (strcmp("cbc(aes)", cipher_type) == 0) {
82 + mode |= SS_OP_AES | SS_CBC | SS_ENABLED | op->keymode;
83 + return sunxi_ss_aes_poll(areq, mode);
84 + }
85 +
86 + if (strcmp("cbc(des)", cipher_type) == 0) {
87 + mode |= SS_OP_DES | SS_CBC | SS_ENABLED | op->keymode;
88 + return sunxi_ss_des_poll(areq, mode);
89 + }
90 +
91 + if (strcmp("cbc(des3_ede)", cipher_type) == 0) {
92 + mode |= SS_OP_3DES | SS_CBC | SS_ENABLED | op->keymode;
93 + return sunxi_ss_des_poll(areq, mode);
94 + }
95 +
96 + dev_err(ss->dev, "ERROR: Cipher %s not handled\n", cipher_type);
97 + return -EINVAL;
98 +}
99 +
100 +int sunxi_ss_cipher_encrypt(struct ablkcipher_request *areq)
101 +{
102 + return sunxi_ss_cipher(areq, SS_ENCRYPTION);
103 +}
104 +
105 +int sunxi_ss_cipher_decrypt(struct ablkcipher_request *areq)
106 +{
107 + return sunxi_ss_cipher(areq, SS_DECRYPTION);
108 +}
109 +
110 +int sunxi_ss_cipher_init(struct crypto_tfm *tfm)
111 +{
112 + struct sunxi_tfm_ctx *op = crypto_tfm_ctx(tfm);
113 +
114 + memset(op, 0, sizeof(struct sunxi_tfm_ctx));
115 + return 0;
116 +}
117 +
118 +/*
119 + * Optimized function for the case where we have only one SG,
120 + * so we can use kmap_atomic
121 + */
122 +static int sunxi_ss_aes_poll_atomic(struct ablkcipher_request *areq)
123 +{
124 + u32 spaces;
125 + struct scatterlist *in_sg = areq->src;
126 + struct scatterlist *out_sg = areq->dst;
127 + void *src_addr;
128 + void *dst_addr;
129 + unsigned int ileft = areq->nbytes;
130 + unsigned int oleft = areq->nbytes;
131 + unsigned int todo;
132 + u32 *src32;
133 + u32 *dst32;
134 + u32 rx_cnt = 32;
135 + u32 tx_cnt = 0;
136 + int i;
137 +
138 + src_addr = kmap_atomic(sg_page(in_sg)) + in_sg->offset;
139 + if (src_addr == NULL) {
140 + dev_err(ss->dev, "kmap_atomic error for src SG\n");
141 + writel(0, ss->base + SS_CTL);
142 + mutex_unlock(&ss->lock);
143 + return -EINVAL;
144 + }
145 +
146 + dst_addr = kmap_atomic(sg_page(out_sg)) + out_sg->offset;
147 + if (dst_addr == NULL) {
148 + dev_err(ss->dev, "kmap_atomic error for dst SG\n");
149 + writel(0, ss->base + SS_CTL);
150 + kunmap_atomic(src_addr);
151 + mutex_unlock(&ss->lock);
152 + return -EINVAL;
153 + }
154 +
155 + src32 = (u32 *)src_addr;
156 + dst32 = (u32 *)dst_addr;
157 + ileft = areq->nbytes / 4;
158 + oleft = areq->nbytes / 4;
159 + i = 0;
160 + do {
161 + if (ileft > 0 && rx_cnt > 0) {
162 + todo = min(rx_cnt, ileft);
163 + ileft -= todo;
164 + do {
165 + writel_relaxed(*src32++,
166 + ss->base +
167 + SS_RXFIFO);
168 + todo--;
169 + } while (todo > 0);
170 + }
171 + if (tx_cnt > 0) {
172 + todo = min(tx_cnt, oleft);
173 + oleft -= todo;
174 + do {
175 + *dst32++ = readl_relaxed(ss->base +
176 + SS_TXFIFO);
177 + todo--;
178 + } while (todo > 0);
179 + }
180 + spaces = readl_relaxed(ss->base + SS_FCSR);
181 + rx_cnt = SS_RXFIFO_SPACES(spaces);
182 + tx_cnt = SS_TXFIFO_SPACES(spaces);
183 + } while (oleft > 0);
184 + writel(0, ss->base + SS_CTL);
185 + kunmap_atomic(src_addr);
186 + kunmap_atomic(dst_addr);
187 + mutex_unlock(&ss->lock);
188 + return 0;
189 +}
190 +
191 +int sunxi_ss_aes_poll(struct ablkcipher_request *areq, u32 mode)
192 +{
193 + u32 spaces;
194 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
195 + struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
196 + unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
197 + /* when activating SS, the default FIFO space is 32 */
198 + u32 rx_cnt = 32;
199 + u32 tx_cnt = 0;
200 + u32 v;
201 + int i;
202 + struct scatterlist *in_sg = areq->src;
203 + struct scatterlist *out_sg = areq->dst;
204 + void *src_addr;
205 + void *dst_addr;
206 + unsigned int ileft = areq->nbytes;
207 + unsigned int oleft = areq->nbytes;
208 + unsigned int sgileft = areq->src->length;
209 + unsigned int sgoleft = areq->dst->length;
210 + unsigned int todo;
211 + u32 *src32;
212 + u32 *dst32;
213 +
214 + mutex_lock(&ss->lock);
215 +
216 + for (i = 0; i < op->keylen; i += 4)
217 + writel(*(op->key + i/4), ss->base + SS_KEY0 + i);
218 +
219 + if (areq->info != NULL) {
220 + for (i = 0; i < 4 && i < ivsize / 4; i++) {
221 + v = *(u32 *)(areq->info + i * 4);
222 + writel(v, ss->base + SS_IV0 + i * 4);
223 + }
224 + }
225 + writel(mode, ss->base + SS_CTL);
226 +
227 + /* If we have only one SG, we can use kmap_atomic */
228 + if (sg_next(in_sg) == NULL && sg_next(out_sg) == NULL)
229 + return sunxi_ss_aes_poll_atomic(areq);
230 +
231 + /*
232 + * If we have more than one SG, we cannot use kmap_atomic since
233 + * we hold the mapping too long
234 + */
235 + src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
236 + if (src_addr == NULL) {
237 + dev_err(ss->dev, "KMAP error for src SG\n");
238 + mutex_unlock(&ss->lock);
239 + return -EINVAL;
240 + }
241 + dst_addr = kmap(sg_page(out_sg)) + out_sg->offset;
242 + if (dst_addr == NULL) {
243 + kunmap(sg_page(in_sg));
244 + dev_err(ss->dev, "KMAP error for dst SG\n");
245 + mutex_unlock(&ss->lock);
246 + return -EINVAL;
247 + }
248 + src32 = (u32 *)src_addr;
249 + dst32 = (u32 *)dst_addr;
250 + ileft = areq->nbytes / 4;
251 + oleft = areq->nbytes / 4;
252 + sgileft = in_sg->length / 4;
253 + sgoleft = out_sg->length / 4;
254 + do {
255 + spaces = readl_relaxed(ss->base + SS_FCSR);
256 + rx_cnt = SS_RXFIFO_SPACES(spaces);
257 + tx_cnt = SS_TXFIFO_SPACES(spaces);
258 + todo = min3(rx_cnt, ileft, sgileft);
259 + if (todo > 0) {
260 + ileft -= todo;
261 + sgileft -= todo;
262 + }
263 + while (todo > 0) {
264 + writel_relaxed(*src32++, ss->base + SS_RXFIFO);
265 + todo--;
266 + }
267 + if (in_sg != NULL && sgileft == 0 && ileft > 0) {
268 + kunmap(sg_page(in_sg));
269 + in_sg = sg_next(in_sg);
270 + while (in_sg != NULL && in_sg->length == 0)
271 + in_sg = sg_next(in_sg);
272 + if (in_sg != NULL && ileft > 0) {
273 + src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
274 + if (src_addr == NULL) {
275 + dev_err(ss->dev, "ERROR: KMAP for src SG\n");
276 + mutex_unlock(&ss->lock);
277 + return -EINVAL;
278 + }
279 + src32 = src_addr;
280 + sgileft = in_sg->length / 4;
281 + }
282 + }
283 + /* do not test oleft since when oleft == 0 we have finished */
284 + todo = min3(tx_cnt, oleft, sgoleft);
285 + if (todo > 0) {
286 + oleft -= todo;
287 + sgoleft -= todo;
288 + }
289 + while (todo > 0) {
290 + *dst32++ = readl_relaxed(ss->base + SS_TXFIFO);
291 + todo--;
292 + }
293 + if (out_sg != NULL && sgoleft == 0 && oleft >= 0) {
294 + kunmap(sg_page(out_sg));
295 + out_sg = sg_next(out_sg);
296 + while (out_sg != NULL && out_sg->length == 0)
297 + out_sg = sg_next(out_sg);
298 + if (out_sg != NULL && oleft > 0) {
299 + dst_addr = kmap(sg_page(out_sg)) +
300 + out_sg->offset;
301 + if (dst_addr == NULL) {
302 + dev_err(ss->dev, "KMAP error\n");
303 + mutex_unlock(&ss->lock);
304 + return -EINVAL;
305 + }
306 + dst32 = dst_addr;
307 + sgoleft = out_sg->length / 4;
308 + }
309 + }
310 + } while (oleft > 0);
311 +
312 + writel_relaxed(0, ss->base + SS_CTL);
313 + mutex_unlock(&ss->lock);
314 + return 0;
315 +}
316 +
317 +/*
318 + * Pure CPU way of doing DES/3DES with SS
319 + * Since DES and 3DES SGs could be smaller than 4 bytes, I use sg_copy_to_buffer
320 + * for "linearize" them.
321 + * The problem with that is that I alloc (2 x areq->nbytes) for buf_in/buf_out
322 + * TODO: change this system, I need to support other mode than CBC where len
323 + * is not a multiple of 4 and the hack of linearize use too much memory
324 + * SGsrc -> buf_in -> SS -> buf_out -> SGdst
325 + */
326 +int sunxi_ss_des_poll(struct ablkcipher_request *areq, u32 mode)
327 +{
328 + u32 value, spaces;
329 + size_t nb_in_sg_tx, nb_in_sg_rx;
330 + size_t ir, it;
331 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
332 + struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
333 + unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
334 + u32 tx_cnt = 0;
335 + u32 rx_cnt = 0;
336 + u32 v;
337 + int i;
338 + int no_chunk = 1;
339 + struct scatterlist *in_sg = areq->src;
340 + struct scatterlist *out_sg = areq->dst;
341 +
342 + /*
343 + * if we have only SGs with size multiple of 4,
344 + * we can use the SS AES function
345 + */
346 + while (in_sg != NULL && no_chunk == 1) {
347 + if ((in_sg->length % 4) != 0)
348 + no_chunk = 0;
349 + in_sg = sg_next(in_sg);
350 + }
351 + while (out_sg != NULL && no_chunk == 1) {
352 + if ((out_sg->length % 4) != 0)
353 + no_chunk = 0;
354 + out_sg = sg_next(out_sg);
355 + }
356 +
357 + if (no_chunk == 1)
358 + return sunxi_ss_aes_poll(areq, mode);
359 +
360 + in_sg = areq->src;
361 + out_sg = areq->dst;
362 +
363 + nb_in_sg_rx = sg_nents(in_sg);
364 + nb_in_sg_tx = sg_nents(out_sg);
365 +
366 + /*
367 + * buf_in and buf_out are allocated only one time
368 + * then we keep the buffer until driver end
369 + * the allocation can only grow more
370 + * we do not reduce it for simplification
371 + */
372 + mutex_lock(&ss->bufin_lock);
373 + if (ss->buf_in == NULL) {
374 + ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL);
375 + ss->buf_in_size = areq->nbytes;
376 + } else {
377 + if (areq->nbytes > ss->buf_in_size) {
378 + kfree(ss->buf_in);
379 + ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL);
380 + ss->buf_in_size = areq->nbytes;
381 + }
382 + }
383 + if (ss->buf_in == NULL) {
384 + ss->buf_in_size = 0;
385 + mutex_unlock(&ss->bufin_lock);
386 + dev_err(ss->dev, "Unable to allocate pages.\n");
387 + return -ENOMEM;
388 + }
389 + mutex_lock(&ss->bufout_lock);
390 + if (ss->buf_out == NULL) {
391 + ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL);
392 + if (ss->buf_out == NULL) {
393 + ss->buf_out_size = 0;
394 + mutex_unlock(&ss->bufin_lock);
395 + mutex_unlock(&ss->bufout_lock);
396 + dev_err(ss->dev, "Unable to allocate pages.\n");
397 + return -ENOMEM;
398 + }
399 + ss->buf_out_size = areq->nbytes;
400 + } else {
401 + if (areq->nbytes > ss->buf_out_size) {
402 + kfree(ss->buf_out);
403 + ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL);
404 + if (ss->buf_out == NULL) {
405 + ss->buf_out_size = 0;
406 + mutex_unlock(&ss->bufin_lock);
407 + mutex_unlock(&ss->bufout_lock);
408 + dev_err(ss->dev, "Unable to allocate pages.\n");
409 + return -ENOMEM;
410 + }
411 + ss->buf_out_size = areq->nbytes;
412 + }
413 + }
414 +
415 + sg_copy_to_buffer(areq->src, nb_in_sg_rx, ss->buf_in, areq->nbytes);
416 +
417 + ir = 0;
418 + it = 0;
419 + mutex_lock(&ss->lock);
420 +
421 + for (i = 0; i < op->keylen; i += 4)
422 + writel(*(op->key + i/4), ss->base + SS_KEY0 + i);
423 + if (areq->info != NULL) {
424 + for (i = 0; i < 4 && i < ivsize / 4; i++) {
425 + v = *(u32 *)(areq->info + i * 4);
426 + writel(v, ss->base + SS_IV0 + i * 4);
427 + }
428 + }
429 + writel(mode, ss->base + SS_CTL);
430 +
431 + do {
432 + if (rx_cnt == 0 || tx_cnt == 0) {
433 + spaces = readl(ss->base + SS_FCSR);
434 + rx_cnt = SS_RXFIFO_SPACES(spaces);
435 + tx_cnt = SS_TXFIFO_SPACES(spaces);
436 + }
437 + if (rx_cnt > 0 && ir < areq->nbytes) {
438 + do {
439 + value = *(u32 *)(ss->buf_in + ir);
440 + writel(value, ss->base + SS_RXFIFO);
441 + ir += 4;
442 + rx_cnt--;
443 + } while (rx_cnt > 0 && ir < areq->nbytes);
444 + }
445 + if (tx_cnt > 0 && it < areq->nbytes) {
446 + do {
447 + value = readl(ss->base + SS_TXFIFO);
448 + *(u32 *)(ss->buf_out + it) = value;
449 + it += 4;
450 + tx_cnt--;
451 + } while (tx_cnt > 0 && it < areq->nbytes);
452 + }
453 + if (ir == areq->nbytes) {
454 + mutex_unlock(&ss->bufin_lock);
455 + ir++;
456 + }
457 + } while (it < areq->nbytes);
458 +
459 + writel(0, ss->base + SS_CTL);
460 + mutex_unlock(&ss->lock);
461 +
462 + /*
463 + * a simple optimization, since we dont need the hardware for this copy
464 + * we release the lock and do the copy. With that we gain 5/10% perf
465 + */
466 + sg_copy_from_buffer(areq->dst, nb_in_sg_tx, ss->buf_out, areq->nbytes);
467 +
468 + mutex_unlock(&ss->bufout_lock);
469 + return 0;
470 +}
471 +
472 +/* check and set the AES key, prepare the mode to be used */
473 +int sunxi_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
474 + unsigned int keylen)
475 +{
476 + struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
477 +
478 + switch (keylen) {
479 + case 128 / 8:
480 + op->keymode = SS_AES_128BITS;
481 + break;
482 + case 192 / 8:
483 + op->keymode = SS_AES_192BITS;
484 + break;
485 + case 256 / 8:
486 + op->keymode = SS_AES_256BITS;
487 + break;
488 + default:
489 + dev_err(ss->dev, "ERROR: Invalid keylen %u\n", keylen);
490 + crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
491 + return -EINVAL;
492 + }
493 + op->keylen = keylen;
494 + memcpy(op->key, key, keylen);
495 + return 0;
496 +}
497 +
498 +/* check and set the DES key, prepare the mode to be used */
499 +int sunxi_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
500 + unsigned int keylen)
501 +{
502 + struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
503 +
504 + if (keylen != DES_KEY_SIZE) {
505 + dev_err(ss->dev, "Invalid keylen %u\n", keylen);
506 + crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
507 + return -EINVAL;
508 + }
509 + op->keylen = keylen;
510 + memcpy(op->key, key, keylen);
511 + return 0;
512 +}
513 +
514 +/* check and set the 3DES key, prepare the mode to be used */
515 +int sunxi_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
516 + unsigned int keylen)
517 +{
518 + struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
519 +
520 + if (keylen != 3 * DES_KEY_SIZE) {
521 + dev_err(ss->dev, "Invalid keylen %u\n", keylen);
522 + crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
523 + return -EINVAL;
524 + }
525 + op->keylen = keylen;
526 + memcpy(op->key, key, keylen);
527 + return 0;
528 +}
529 --- /dev/null
530 +++ b/drivers/crypto/sunxi-ss/sunxi-ss-core.c
531 @@ -0,0 +1,318 @@
532 +/*
533 + * sunxi-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
534 + *
535 + * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
536 + *
537 + * Core file which registers crypto algorithms supported by the SS.
538 + *
539 + * You could find a link for the datasheet in Documentation/arm/sunxi/README
540 + *
541 + * This program is free software; you can redistribute it and/or modify
542 + * it under the terms of the GNU General Public License as published by
543 + * the Free Software Foundation; either version 2 of the License, or
544 + * (at your option) any later version.
545 + */
546 +#include <linux/clk.h>
547 +#include <linux/crypto.h>
548 +#include <linux/io.h>
549 +#include <linux/module.h>
550 +#include <linux/of.h>
551 +#include <linux/platform_device.h>
552 +#include <crypto/scatterwalk.h>
553 +#include <linux/scatterlist.h>
554 +#include <linux/interrupt.h>
555 +#include <linux/delay.h>
556 +
557 +#include "sunxi-ss.h"
558 +
559 +struct sunxi_ss_ctx *ss;
560 +
561 +/*
562 + * General notes for whole driver:
563 + *
564 + * After each request the device must be disabled with a write of 0 in SS_CTL
565 + *
566 + * For performance reason, we use writel_relaxed/read_relaxed for all
567 + * operations on RX and TX FIFO and also SS_FCSR.
568 + * Excepts for the last write on TX FIFO.
569 + * For all other registers, we use writel/readl.
570 + * See http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117644
571 + * and http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117640
572 + */
573 +
574 +static struct ahash_alg sunxi_md5_alg = {
575 + .init = sunxi_hash_init,
576 + .update = sunxi_hash_update,
577 + .final = sunxi_hash_final,
578 + .finup = sunxi_hash_finup,
579 + .digest = sunxi_hash_digest,
580 + .halg = {
581 + .digestsize = MD5_DIGEST_SIZE,
582 + .base = {
583 + .cra_name = "md5",
584 + .cra_driver_name = "md5-sunxi-ss",
585 + .cra_priority = 300,
586 + .cra_alignmask = 3,
587 + .cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
588 + .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
589 + .cra_ctxsize = sizeof(struct sunxi_req_ctx),
590 + .cra_module = THIS_MODULE,
591 + .cra_type = &crypto_ahash_type,
592 + .cra_init = sunxi_hash_crainit
593 + }
594 + }
595 +};
596 +
597 +static struct ahash_alg sunxi_sha1_alg = {
598 + .init = sunxi_hash_init,
599 + .update = sunxi_hash_update,
600 + .final = sunxi_hash_final,
601 + .finup = sunxi_hash_finup,
602 + .digest = sunxi_hash_digest,
603 + .halg = {
604 + .digestsize = SHA1_DIGEST_SIZE,
605 + .base = {
606 + .cra_name = "sha1",
607 + .cra_driver_name = "sha1-sunxi-ss",
608 + .cra_priority = 300,
609 + .cra_alignmask = 3,
610 + .cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
611 + .cra_blocksize = SHA1_BLOCK_SIZE,
612 + .cra_ctxsize = sizeof(struct sunxi_req_ctx),
613 + .cra_module = THIS_MODULE,
614 + .cra_type = &crypto_ahash_type,
615 + .cra_init = sunxi_hash_crainit
616 + }
617 + }
618 +};
619 +
620 +static struct crypto_alg sunxi_cipher_algs[] = {
621 +{
622 + .cra_name = "cbc(aes)",
623 + .cra_driver_name = "cbc-aes-sunxi-ss",
624 + .cra_priority = 300,
625 + .cra_blocksize = AES_BLOCK_SIZE,
626 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
627 + .cra_ctxsize = sizeof(struct sunxi_tfm_ctx),
628 + .cra_module = THIS_MODULE,
629 + .cra_alignmask = 3,
630 + .cra_type = &crypto_ablkcipher_type,
631 + .cra_init = sunxi_ss_cipher_init,
632 + .cra_u = {
633 + .ablkcipher = {
634 + .min_keysize = AES_MIN_KEY_SIZE,
635 + .max_keysize = AES_MAX_KEY_SIZE,
636 + .ivsize = AES_BLOCK_SIZE,
637 + .setkey = sunxi_ss_aes_setkey,
638 + .encrypt = sunxi_ss_cipher_encrypt,
639 + .decrypt = sunxi_ss_cipher_decrypt,
640 + }
641 + }
642 +}, {
643 + .cra_name = "cbc(des)",
644 + .cra_driver_name = "cbc-des-sunxi-ss",
645 + .cra_priority = 300,
646 + .cra_blocksize = DES_BLOCK_SIZE,
647 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
648 + .cra_ctxsize = sizeof(struct sunxi_req_ctx),
649 + .cra_module = THIS_MODULE,
650 + .cra_alignmask = 3,
651 + .cra_type = &crypto_ablkcipher_type,
652 + .cra_init = sunxi_ss_cipher_init,
653 + .cra_u.ablkcipher = {
654 + .min_keysize = DES_KEY_SIZE,
655 + .max_keysize = DES_KEY_SIZE,
656 + .ivsize = DES_BLOCK_SIZE,
657 + .setkey = sunxi_ss_des_setkey,
658 + .encrypt = sunxi_ss_cipher_encrypt,
659 + .decrypt = sunxi_ss_cipher_decrypt,
660 + }
661 +}, {
662 + .cra_name = "cbc(des3_ede)",
663 + .cra_driver_name = "cbc-des3-sunxi-ss",
664 + .cra_priority = 300,
665 + .cra_blocksize = DES3_EDE_BLOCK_SIZE,
666 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
667 + .cra_ctxsize = sizeof(struct sunxi_req_ctx),
668 + .cra_module = THIS_MODULE,
669 + .cra_alignmask = 3,
670 + .cra_type = &crypto_ablkcipher_type,
671 + .cra_init = sunxi_ss_cipher_init,
672 + .cra_u.ablkcipher = {
673 + .min_keysize = DES3_EDE_KEY_SIZE,
674 + .max_keysize = DES3_EDE_KEY_SIZE,
675 + .ivsize = DES3_EDE_BLOCK_SIZE,
676 + .setkey = sunxi_ss_des3_setkey,
677 + .encrypt = sunxi_ss_cipher_encrypt,
678 + .decrypt = sunxi_ss_cipher_decrypt,
679 + }
680 +}
681 +};
682 +
683 +static int sunxi_ss_probe(struct platform_device *pdev)
684 +{
685 + struct resource *res;
686 + u32 v;
687 + int err;
688 + unsigned long cr;
689 + const unsigned long cr_ahb = 24 * 1000 * 1000;
690 + const unsigned long cr_mod = 150 * 1000 * 1000;
691 +
692 + if (!pdev->dev.of_node)
693 + return -ENODEV;
694 +
695 + ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
696 + if (ss == NULL)
697 + return -ENOMEM;
698 +
699 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
700 + ss->base = devm_ioremap_resource(&pdev->dev, res);
701 + if (IS_ERR(ss->base)) {
702 + dev_err(&pdev->dev, "Cannot request MMIO\n");
703 + return PTR_ERR(ss->base);
704 + }
705 +
706 + ss->ssclk = devm_clk_get(&pdev->dev, "mod");
707 + if (IS_ERR(ss->ssclk)) {
708 + err = PTR_ERR(ss->ssclk);
709 + dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
710 + return err;
711 + }
712 + dev_dbg(&pdev->dev, "clock ss acquired\n");
713 +
714 + ss->busclk = devm_clk_get(&pdev->dev, "ahb");
715 + if (IS_ERR(ss->busclk)) {
716 + err = PTR_ERR(ss->busclk);
717 + dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
718 + return err;
719 + }
720 + dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
721 +
722 + /* Enable both clocks */
723 + err = clk_prepare_enable(ss->busclk);
724 + if (err != 0) {
725 + dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
726 + return err;
727 + }
728 + err = clk_prepare_enable(ss->ssclk);
729 + if (err != 0) {
730 + dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
731 + clk_disable_unprepare(ss->busclk);
732 + return err;
733 + }
734 +
735 + /*
736 + * Check that clock have the correct rates gived in the datasheet
737 + * Try to set the clock to the maximum allowed
738 + */
739 + err = clk_set_rate(ss->ssclk, cr_mod);
740 + if (err != 0) {
741 + dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
742 + clk_disable_unprepare(ss->ssclk);
743 + clk_disable_unprepare(ss->busclk);
744 + return err;
745 + }
746 +
747 + cr = clk_get_rate(ss->busclk);
748 + if (cr >= cr_ahb)
749 + dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
750 + cr, cr / 1000000, cr_ahb);
751 + else
752 + dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
753 + cr, cr / 1000000, cr_ahb);
754 +
755 + cr = clk_get_rate(ss->ssclk);
756 + if (cr <= cr_mod)
757 + if (cr < cr_mod)
758 + dev_info(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
759 + cr, cr / 1000000, cr_mod);
760 + else
761 + dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
762 + cr, cr / 1000000, cr_mod);
763 + else
764 + dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
765 + cr, cr / 1000000, cr_mod);
766 +
767 + /*
768 + * Datasheet named it "Die Bonding ID"
769 + * I expect to be a sort of Security System Revision number.
770 + * Since the A80 seems to have an other version of SS
771 + * this info could be useful
772 + */
773 + writel(SS_ENABLED, ss->base + SS_CTL);
774 + v = readl(ss->base + SS_CTL);
775 + v >>= 16;
776 + v &= 0x07;
777 + dev_info(&pdev->dev, "Die ID %d\n", v);
778 + writel(0, ss->base + SS_CTL);
779 +
780 + ss->dev = &pdev->dev;
781 +
782 + mutex_init(&ss->lock);
783 + mutex_init(&ss->bufin_lock);
784 + mutex_init(&ss->bufout_lock);
785 +
786 + err = crypto_register_ahash(&sunxi_md5_alg);
787 + if (err)
788 + goto error_md5;
789 + err = crypto_register_ahash(&sunxi_sha1_alg);
790 + if (err)
791 + goto error_sha1;
792 + err = crypto_register_algs(sunxi_cipher_algs,
793 + ARRAY_SIZE(sunxi_cipher_algs));
794 + if (err)
795 + goto error_ciphers;
796 +
797 + return 0;
798 +error_ciphers:
799 + crypto_unregister_ahash(&sunxi_sha1_alg);
800 +error_sha1:
801 + crypto_unregister_ahash(&sunxi_md5_alg);
802 +error_md5:
803 + clk_disable_unprepare(ss->ssclk);
804 + clk_disable_unprepare(ss->busclk);
805 + return err;
806 +}
807 +
808 +static int __exit sunxi_ss_remove(struct platform_device *pdev)
809 +{
810 + if (!pdev->dev.of_node)
811 + return 0;
812 +
813 + crypto_unregister_ahash(&sunxi_md5_alg);
814 + crypto_unregister_ahash(&sunxi_sha1_alg);
815 + crypto_unregister_algs(sunxi_cipher_algs,
816 + ARRAY_SIZE(sunxi_cipher_algs));
817 +
818 + if (ss->buf_in != NULL)
819 + kfree(ss->buf_in);
820 + if (ss->buf_out != NULL)
821 + kfree(ss->buf_out);
822 +
823 + writel(0, ss->base + SS_CTL);
824 + clk_disable_unprepare(ss->busclk);
825 + clk_disable_unprepare(ss->ssclk);
826 + return 0;
827 +}
828 +
829 +static const struct of_device_id a20ss_crypto_of_match_table[] = {
830 + { .compatible = "allwinner,sun7i-a20-crypto" },
831 + {}
832 +};
833 +MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
834 +
835 +static struct platform_driver sunxi_ss_driver = {
836 + .probe = sunxi_ss_probe,
837 + .remove = __exit_p(sunxi_ss_remove),
838 + .driver = {
839 + .owner = THIS_MODULE,
840 + .name = "sunxi-ss",
841 + .of_match_table = a20ss_crypto_of_match_table,
842 + },
843 +};
844 +
845 +module_platform_driver(sunxi_ss_driver);
846 +
847 +MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
848 +MODULE_LICENSE("GPL");
849 +MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");
850 --- /dev/null
851 +++ b/drivers/crypto/sunxi-ss/sunxi-ss-hash.c
852 @@ -0,0 +1,445 @@
853 +/*
854 + * sunxi-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
855 + *
856 + * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
857 + *
858 + * This file add support for MD5 and SHA1.
859 + *
860 + * You could find the datasheet in Documentation/arm/sunxi/README
861 + *
862 + * This program is free software; you can redistribute it and/or modify
863 + * it under the terms of the GNU General Public License as published by
864 + * the Free Software Foundation; either version 2 of the License, or
865 + * (at your option) any later version.
866 + */
867 +#include "sunxi-ss.h"
868 +
869 +/* This is a totaly arbitrary value */
870 +#define SS_TIMEOUT 100
871 +
872 +extern struct sunxi_ss_ctx *ss;
873 +
874 +int sunxi_hash_crainit(struct crypto_tfm *tfm)
875 +{
876 + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
877 + sizeof(struct sunxi_req_ctx));
878 + return 0;
879 +}
880 +
881 +/* sunxi_hash_init: initialize request context */
882 +int sunxi_hash_init(struct ahash_request *areq)
883 +{
884 + const char *hash_type;
885 + struct sunxi_req_ctx *op = ahash_request_ctx(areq);
886 +
887 + memset(op, 0, sizeof(struct sunxi_req_ctx));
888 +
889 + hash_type = crypto_tfm_alg_name(areq->base.tfm);
890 +
891 + if (strcmp(hash_type, "sha1") == 0)
892 + op->mode = SS_OP_SHA1;
893 + if (strcmp(hash_type, "md5") == 0)
894 + op->mode = SS_OP_MD5;
895 + if (op->mode == 0)
896 + return -EINVAL;
897 +
898 + return 0;
899 +}
900 +
901 +static u32 rx_cnt;
902 +
903 +inline void ss_writer(const u32 v)
904 +{
905 + u32 spaces;
906 +
907 + writel(v, ss->base + SS_RXFIFO);
908 + rx_cnt--;
909 + while (rx_cnt == 0) {
910 + spaces = readl_relaxed(ss->base + SS_FCSR);
911 + rx_cnt = SS_RXFIFO_SPACES(spaces);
912 + }
913 +}
914 +
915 +inline void ss_writer_relaxed(const u32 v)
916 +{
917 + u32 spaces;
918 +
919 + writel_relaxed(v, ss->base + SS_RXFIFO);
920 + rx_cnt--;
921 + while (rx_cnt == 0) {
922 + spaces = readl_relaxed(ss->base + SS_FCSR);
923 + rx_cnt = SS_RXFIFO_SPACES(spaces);
924 + }
925 +}
926 +
927 +/*
928 + * sunxi_hash_update: update hash engine
929 + *
930 + * Could be used for both SHA1 and MD5
931 + * Write data by step of 32bits and put then in the SS.
932 + *
933 + * Since we cannot leave partial data and hash state in the engine,
934 + * we need to get the hash state at the end of this function.
935 + * After some work, I have found that we can get the hash state every 64o
936 + *
937 + * So the first work is to get the number of bytes to write to SS modulo 64
938 + * The extra bytes will go to two different destination:
939 + * op->wait for full 32bits word
940 + * op->wb (waiting bytes) for partial 32 bits word
941 + * So we can have up to (64/4)-1 op->wait words and 0/1/2/3 bytes in wb
942 + *
943 + * So at the begin of update()
944 + * if op->nwait * 4 + areq->nbytes < 64
945 + * => all data writed to wait buffers and end=0
946 + * if not write all nwait to the device and position end to complete to 64o
947 + *
948 + * example 1:
949 + * update1 60o => nwait=15
950 + * update2 60o => need one more word to have 64o
951 + * end=4
952 + * so write all data in op->wait and one word of SGs
953 + * write remaining data in op->wait
954 + * final state op->nwait=14
955 + */
956 +int sunxi_hash_update(struct ahash_request *areq)
957 +{
958 + u32 v, ivmode = 0;
959 + unsigned int i = 0;
960 + /*
961 + * i is the total bytes read from SGs, to be compared to areq->nbytes
962 + * i is important because we cannot rely on SG length since the sum of
963 + * SG->length could be greater than areq->nbytes
964 + */
965 +
966 + struct sunxi_req_ctx *op = ahash_request_ctx(areq);
967 + struct scatterlist *in_sg;
968 + unsigned int in_i = 0; /* advancement in the current SG */
969 + u64 end;
970 + /*
971 + * end is the position when we need to stop writing to the device,
972 + * to be compared to i
973 + */
974 + int in_r;
975 + void *src_addr;
976 +
977 + dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x bw=%u ww=%u",
978 + __func__, crypto_tfm_alg_name(areq->base.tfm),
979 + op->byte_count, areq->nbytes, op->mode,
980 + op->nbw, op->nwait);
981 +
982 + if (areq->nbytes == 0)
983 + return 0;
984 +
985 + end = ((areq->nbytes + op->nwait * 4 + op->nbw) / 64) * 64
986 + - op->nbw - op->nwait * 4;
987 +
988 + if (end > areq->nbytes || areq->nbytes - end > 63) {
989 + dev_err(ss->dev, "ERROR: Bound error %llu %u\n",
990 + end, areq->nbytes);
991 + return -EINVAL;
992 + }
993 +
994 + if (op->nwait > 0 && end > 0) {
995 + /* a precedent update was done */
996 + for (i = 0; i < op->nwait; i++) {
997 + ss_writer(op->wait[i]);
998 + op->byte_count += 4;
999 + }
1000 + op->nwait = 0;
1001 + }
1002 +
1003 + mutex_lock(&ss->lock);
1004 + /*
1005 + * if some data have been processed before,
1006 + * we need to restore the partial hash state
1007 + */
1008 + if (op->byte_count > 0) {
1009 + ivmode = SS_IV_ARBITRARY;
1010 + for (i = 0; i < 5; i++)
1011 + writel(op->hash[i], ss->base + SS_IV0 + i * 4);
1012 + }
1013 + /* Enable the device */
1014 + writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
1015 +
1016 + rx_cnt = 0;
1017 + i = 0;
1018 +
1019 + in_sg = areq->src;
1020 + src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
1021 + if (src_addr == NULL) {
1022 + mutex_unlock(&ss->lock);
1023 + dev_err(ss->dev, "ERROR: Cannot kmap source buffer\n");
1024 + return -EFAULT;
1025 + }
1026 + do {
1027 + /*
1028 + * step 1, if some bytes remains from last SG,
1029 + * try to complete them to 4 and send that word
1030 + */
1031 + if (op->nbw > 0) {
1032 + while (op->nbw < 4 && i < areq->nbytes &&
1033 + in_i < in_sg->length) {
1034 + op->wb |= (*(u8 *)(src_addr + in_i))
1035 + << (8 * op->nbw);
1036 + dev_dbg(ss->dev, "%s Complete w=%d wb=%x\n",
1037 + __func__, op->nbw, op->wb);
1038 + i++;
1039 + in_i++;
1040 + op->nbw++;
1041 + }
1042 + if (op->nbw == 4) {
1043 + if (i <= end) {
1044 + ss_writer(op->wb);
1045 + op->byte_count += 4;
1046 + } else {
1047 + op->wait[op->nwait] = op->wb;
1048 + op->nwait++;
1049 + dev_dbg(ss->dev, "%s Keep %u bytes after %llu\n",
1050 + __func__, op->nwait, end);
1051 + }
1052 + op->nbw = 0;
1053 + op->wb = 0;
1054 + }
1055 + }
1056 + /* step 2, main loop, read data 4bytes at a time */
1057 + while (i < areq->nbytes && in_i < in_sg->length) {
1058 + /* how many bytes we can read, (we need 4) */
1059 + in_r = min(in_sg->length - in_i, areq->nbytes - i);
1060 + if (in_r < 4) {
1061 + /* Not enough data to write to the device */
1062 + op->wb = 0;
1063 + while (in_r > 0) {
1064 + op->wb |= (*(u8 *)(src_addr + in_i))
1065 + << (8 * op->nbw);
1066 + dev_dbg(ss->dev, "%s ending bw=%d wb=%x\n",
1067 + __func__, op->nbw, op->wb);
1068 + in_r--;
1069 + i++;
1070 + in_i++;
1071 + op->nbw++;
1072 + }
1073 + goto nextsg;
1074 + }
1075 + v = *(u32 *)(src_addr + in_i);
1076 + if (i < end) {
1077 + /* last write must be done without relaxed */
1078 + if (i + 4 >= end)
1079 + ss_writer(v);
1080 + else
1081 + ss_writer_relaxed(v);
1082 + i += 4;
1083 + op->byte_count += 4;
1084 + in_i += 4;
1085 + } else {
1086 + op->wait[op->nwait] = v;
1087 + i += 4;
1088 + in_i += 4;
1089 + op->nwait++;
1090 + dev_dbg(ss->dev, "%s Keep word ww=%u after %llu\n",
1091 + __func__, op->nwait, end);
1092 + if (op->nwait > 15) {
1093 + dev_err(ss->dev, "FATAL: Cannot enqueue more, bug?\n");
1094 + writel(0, ss->base + SS_CTL);
1095 + mutex_unlock(&ss->lock);
1096 + return -EIO;
1097 + }
1098 + }
1099 + }
1100 +nextsg:
1101 + /* Nothing more to read in this SG */
1102 + if (in_i == in_sg->length) {
1103 + kunmap(sg_page(in_sg));
1104 + do {
1105 + in_sg = sg_next(in_sg);
1106 + } while (in_sg != NULL && in_sg->length == 0);
1107 + in_i = 0;
1108 + if (in_sg != NULL) {
1109 + src_addr = kmap(sg_page(in_sg)) + in_sg->offset;
1110 + if (src_addr == NULL) {
1111 + mutex_unlock(&ss->lock);
1112 + dev_err(ss->dev, "ERROR: Cannot kmap source buffer\n");
1113 + return -EFAULT;
1114 + }
1115 + }
1116 + }
1117 + } while (in_sg != NULL && i < areq->nbytes);
1118 +
1119 + /* ask the device to finish the hashing */
1120 + writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
1121 + i = 0;
1122 + do {
1123 + v = readl(ss->base + SS_CTL);
1124 + i++;
1125 + } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
1126 + if (i >= SS_TIMEOUT) {
1127 + dev_err(ss->dev, "ERROR: %s hash end timeout after %d loop, CTL=%x\n",
1128 + __func__, i, v);
1129 + writel(0, ss->base + SS_CTL);
1130 + mutex_unlock(&ss->lock);
1131 + return -EIO;
1132 + }
1133 +
1134 + /* get the partial hash */
1135 + if (op->mode == SS_OP_SHA1) {
1136 + for (i = 0; i < 5; i++)
1137 + op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
1138 + } else {
1139 + for (i = 0; i < 4; i++)
1140 + op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
1141 + }
1142 +
1143 + writel(0, ss->base + SS_CTL);
1144 + mutex_unlock(&ss->lock);
1145 + return 0;
1146 +}
1147 +
1148 +/*
1149 + * sunxi_hash_final: finalize hashing operation
1150 + *
1151 + * If we have some remaining bytes, we write them.
1152 + * Then ask the SS for finalizing the hashing operation
1153 + */
1154 +int sunxi_hash_final(struct ahash_request *areq)
1155 +{
1156 + u32 v, ivmode = 0;
1157 + unsigned int i;
1158 + int zeros;
1159 + unsigned int index, padlen;
1160 + __be64 bits;
1161 + struct sunxi_req_ctx *op = ahash_request_ctx(areq);
1162 +
1163 + dev_dbg(ss->dev, "%s byte=%llu len=%u mode=%x bw=%u %x h=%x ww=%u",
1164 + __func__, op->byte_count, areq->nbytes, op->mode,
1165 + op->nbw, op->wb, op->hash[0], op->nwait);
1166 +
1167 + mutex_lock(&ss->lock);
1168 + rx_cnt = 0;
1169 +
1170 + /*
1171 + * if we have already writed something,
1172 + * restore the partial hash state
1173 + */
1174 + if (op->byte_count > 0) {
1175 + ivmode = SS_IV_ARBITRARY;
1176 + for (i = 0; i < 5; i++)
1177 + writel(op->hash[i], ss->base + SS_IV0 + i * 4);
1178 + }
1179 + writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
1180 +
1181 + /* write the remaining words of the wait buffer */
1182 + if (op->nwait > 0) {
1183 + for (i = 0; i < op->nwait; i++) {
1184 + v = op->wait[i];
1185 + ss_writer(v);
1186 + op->byte_count += 4;
1187 + dev_dbg(ss->dev, "%s write %llu i=%u %x\n",
1188 + __func__, op->byte_count, i, v);
1189 + }
1190 + op->nwait = 0;
1191 + }
1192 +
1193 + /* write the remaining bytes of the nbw buffer */
1194 + if (op->nbw > 0) {
1195 + op->wb |= ((1 << 7) << (op->nbw * 8));
1196 + ss_writer(op->wb);
1197 + } else {
1198 + ss_writer((1 << 7));
1199 + }
1200 +
1201 + /*
1202 + * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
1203 + * I take the operations from other md5/sha1 implementations
1204 + */
1205 +
1206 + /* we have already send 4 more byte of which nbw data */
1207 + if (op->mode == SS_OP_MD5) {
1208 + index = (op->byte_count + 4) & 0x3f;
1209 + op->byte_count += op->nbw;
1210 + if (index > 56)
1211 + zeros = (120 - index) / 4;
1212 + else
1213 + zeros = (56 - index) / 4;
1214 + } else {
1215 + op->byte_count += op->nbw;
1216 + index = op->byte_count & 0x3f;
1217 + padlen = (index < 56) ? (56 - index) : ((64+56) - index);
1218 + zeros = (padlen - 1) / 4;
1219 + }
1220 + for (i = 0; i < zeros; i++)
1221 + ss_writer(0);
1222 +
1223 + /* write the length of data */
1224 + if (op->mode == SS_OP_SHA1) {
1225 + bits = cpu_to_be64(op->byte_count << 3);
1226 + ss_writer(bits & 0xffffffff);
1227 + ss_writer((bits >> 32) & 0xffffffff);
1228 + } else {
1229 + ss_writer((op->byte_count << 3) & 0xffffffff);
1230 + ss_writer((op->byte_count >> 29) & 0xffffffff);
1231 + }
1232 +
1233 + /* Tell the SS to stop the hashing */
1234 + writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
1235 +
1236 + /*
1237 + * Wait for SS to finish the hash.
1238 + * The timeout could happend only in case of bad overcloking
1239 + * or driver bug.
1240 + */
1241 + i = 0;
1242 + do {
1243 + v = readl(ss->base + SS_CTL);
1244 + i++;
1245 + } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
1246 + if (i >= SS_TIMEOUT) {
1247 + dev_err(ss->dev, "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
1248 + i, SS_TIMEOUT, v, areq->nbytes);
1249 + writel(0, ss->base + SS_CTL);
1250 + mutex_unlock(&ss->lock);
1251 + return -EIO;
1252 + }
1253 +
1254 + /* Get the hash from the device */
1255 + if (op->mode == SS_OP_SHA1) {
1256 + for (i = 0; i < 5; i++) {
1257 + v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
1258 + memcpy(areq->result + i * 4, &v, 4);
1259 + }
1260 + } else {
1261 + for (i = 0; i < 4; i++) {
1262 + v = readl(ss->base + SS_MD0 + i * 4);
1263 + memcpy(areq->result + i * 4, &v, 4);
1264 + }
1265 + }
1266 + writel(0, ss->base + SS_CTL);
1267 + mutex_unlock(&ss->lock);
1268 + return 0;
1269 +}
1270 +
1271 +/* sunxi_hash_finup: finalize hashing operation after an update */
1272 +int sunxi_hash_finup(struct ahash_request *areq)
1273 +{
1274 + int err;
1275 +
1276 + err = sunxi_hash_update(areq);
1277 + if (err != 0)
1278 + return err;
1279 +
1280 + return sunxi_hash_final(areq);
1281 +}
1282 +
1283 +/* combo of init/update/final functions */
1284 +int sunxi_hash_digest(struct ahash_request *areq)
1285 +{
1286 + int err;
1287 +
1288 + err = sunxi_hash_init(areq);
1289 + if (err != 0)
1290 + return err;
1291 +
1292 + err = sunxi_hash_update(areq);
1293 + if (err != 0)
1294 + return err;
1295 +
1296 + return sunxi_hash_final(areq);
1297 +}
1298 --- /dev/null
1299 +++ b/drivers/crypto/sunxi-ss/sunxi-ss.h
1300 @@ -0,0 +1,193 @@
1301 +/*
1302 + * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC
1303 + *
1304 + * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com>
1305 + *
1306 + * Support AES cipher with 128,192,256 bits keysize.
1307 + * Support MD5 and SHA1 hash algorithms.
1308 + * Support DES and 3DES
1309 + *
1310 + * You could find the datasheet in Documentation/arm/sunxi/README
1311 + *
1312 + * Licensed under the GPL-2.
1313 + */
1314 +
1315 +#include <linux/clk.h>
1316 +#include <linux/crypto.h>
1317 +#include <linux/io.h>
1318 +#include <linux/module.h>
1319 +#include <linux/of.h>
1320 +#include <linux/platform_device.h>
1321 +#include <crypto/scatterwalk.h>
1322 +#include <linux/scatterlist.h>
1323 +#include <linux/interrupt.h>
1324 +#include <linux/delay.h>
1325 +#include <crypto/md5.h>
1326 +#include <crypto/sha.h>
1327 +#include <crypto/hash.h>
1328 +#include <crypto/internal/hash.h>
1329 +#include <crypto/aes.h>
1330 +#include <crypto/des.h>
1331 +#include <crypto/internal/rng.h>
1332 +
1333 +#define SS_CTL 0x00
1334 +#define SS_KEY0 0x04
1335 +#define SS_KEY1 0x08
1336 +#define SS_KEY2 0x0C
1337 +#define SS_KEY3 0x10
1338 +#define SS_KEY4 0x14
1339 +#define SS_KEY5 0x18
1340 +#define SS_KEY6 0x1C
1341 +#define SS_KEY7 0x20
1342 +
1343 +#define SS_IV0 0x24
1344 +#define SS_IV1 0x28
1345 +#define SS_IV2 0x2C
1346 +#define SS_IV3 0x30
1347 +
1348 +#define SS_CNT0 0x34
1349 +#define SS_CNT1 0x38
1350 +#define SS_CNT2 0x3C
1351 +#define SS_CNT3 0x40
1352 +
1353 +#define SS_FCSR 0x44
1354 +#define SS_ICSR 0x48
1355 +
1356 +#define SS_MD0 0x4C
1357 +#define SS_MD1 0x50
1358 +#define SS_MD2 0x54
1359 +#define SS_MD3 0x58
1360 +#define SS_MD4 0x5C
1361 +
1362 +#define SS_RXFIFO 0x200
1363 +#define SS_TXFIFO 0x204
1364 +
1365 +/* SS_CTL configuration values */
1366 +
1367 +/* PRNG generator mode - bit 15 */
1368 +#define SS_PRNG_ONESHOT (0 << 15)
1369 +#define SS_PRNG_CONTINUE (1 << 15)
1370 +
1371 +/* IV mode for hash */
1372 +#define SS_IV_ARBITRARY (1 << 14)
1373 +
1374 +/* SS operation mode - bits 12-13 */
1375 +#define SS_ECB (0 << 12)
1376 +#define SS_CBC (1 << 12)
1377 +#define SS_CNT (2 << 12)
1378 +
1379 +/* Counter width for CNT mode - bits 10-11 */
1380 +#define SS_CNT_16BITS (0 << 10)
1381 +#define SS_CNT_32BITS (1 << 10)
1382 +#define SS_CNT_64BITS (2 << 10)
1383 +
1384 +/* Key size for AES - bits 8-9 */
1385 +#define SS_AES_128BITS (0 << 8)
1386 +#define SS_AES_192BITS (1 << 8)
1387 +#define SS_AES_256BITS (2 << 8)
1388 +
1389 +/* Operation direction - bit 7 */
1390 +#define SS_ENCRYPTION (0 << 7)
1391 +#define SS_DECRYPTION (1 << 7)
1392 +
1393 +/* SS Method - bits 4-6 */
1394 +#define SS_OP_AES (0 << 4)
1395 +#define SS_OP_DES (1 << 4)
1396 +#define SS_OP_3DES (2 << 4)
1397 +#define SS_OP_SHA1 (3 << 4)
1398 +#define SS_OP_MD5 (4 << 4)
1399 +#define SS_OP_PRNG (5 << 4)
1400 +
1401 +/* Data end bit - bit 2 */
1402 +#define SS_DATA_END (1 << 2)
1403 +
1404 +/* PRNG start bit - bit 1 */
1405 +#define SS_PRNG_START (1 << 1)
1406 +
1407 +/* SS Enable bit - bit 0 */
1408 +#define SS_DISABLED (0 << 0)
1409 +#define SS_ENABLED (1 << 0)
1410 +
1411 +/* SS_FCSR configuration values */
1412 +/* RX FIFO status - bit 30 */
1413 +#define SS_RXFIFO_FREE (1 << 30)
1414 +
1415 +/* RX FIFO empty spaces - bits 24-29 */
1416 +#define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f)
1417 +
1418 +/* TX FIFO status - bit 22 */
1419 +#define SS_TXFIFO_AVAILABLE (1 << 22)
1420 +
1421 +/* TX FIFO available spaces - bits 16-21 */
1422 +#define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f)
1423 +
1424 +#define SS_RXFIFO_EMP_INT_PENDING (1 << 10)
1425 +#define SS_TXFIFO_AVA_INT_PENDING (1 << 8)
1426 +#define SS_RXFIFO_EMP_INT_ENABLE (1 << 2)
1427 +#define SS_TXFIFO_AVA_INT_ENABLE (1 << 0)
1428 +
1429 +/* SS_ICSR configuration values */
1430 +#define SS_ICS_DRQ_ENABLE (1 << 4)
1431 +
1432 +struct sunxi_ss_ctx {
1433 + void __iomem *base;
1434 + int irq;
1435 + struct clk *busclk;
1436 + struct clk *ssclk;
1437 + struct device *dev;
1438 + struct resource *res;
1439 + void *buf_in; /* pointer to data to be uploaded to the device */
1440 + size_t buf_in_size; /* size of buf_in */
1441 + void *buf_out;
1442 + size_t buf_out_size;
1443 + struct mutex lock; /* control the use of the device */
1444 + struct mutex bufout_lock; /* control the use of buf_out*/
1445 + struct mutex bufin_lock; /* control the sue of buf_in*/
1446 +};
1447 +
1448 +struct sunxi_tfm_ctx {
1449 + u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */
1450 + u32 keylen;
1451 + u32 keymode;
1452 +};
1453 +
1454 +struct sunxi_req_ctx {
1455 + u32 mode;
1456 + u64 byte_count; /* number of bytes "uploaded" to the device */
1457 + u32 wb; /* a partial word waiting to be completed and
1458 + uploaded to the device */
1459 + /* number of bytes to be uploaded in the wb word */
1460 + unsigned int nbw;
1461 + u32 hash[5];
1462 + u32 wait[64];
1463 + unsigned int nwait;
1464 +};
1465 +
1466 +#define SS_SEED_LEN (192/8)
1467 +#define SS_DATA_LEN (160/8)
1468 +
1469 +struct prng_context {
1470 + u32 seed[SS_SEED_LEN/4];
1471 + unsigned int slen;
1472 +};
1473 +
1474 +int sunxi_hash_crainit(struct crypto_tfm *tfm);
1475 +int sunxi_hash_init(struct ahash_request *areq);
1476 +int sunxi_hash_update(struct ahash_request *areq);
1477 +int sunxi_hash_final(struct ahash_request *areq);
1478 +int sunxi_hash_finup(struct ahash_request *areq);
1479 +int sunxi_hash_digest(struct ahash_request *areq);
1480 +int sunxi_hash_export(struct ahash_request *areq, void *out);
1481 +int sunxi_hash_import(struct ahash_request *areq, const void *in);
1482 +
1483 +int sunxi_ss_aes_poll(struct ablkcipher_request *areq, u32 mode);
1484 +int sunxi_ss_des_poll(struct ablkcipher_request *areq, u32 mode);
1485 +int sunxi_ss_cipher_init(struct crypto_tfm *tfm);
1486 +int sunxi_ss_cipher_encrypt(struct ablkcipher_request *areq);
1487 +int sunxi_ss_cipher_decrypt(struct ablkcipher_request *areq);
1488 +int sunxi_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1489 + unsigned int keylen);
1490 +int sunxi_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1491 + unsigned int keylen);
1492 +int sunxi_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1493 + unsigned int keylen);
OpenWrt Source Repository