target/linux/sunxi/patches-4.1/119-mtd-nand-ecc-for-samsung.patch

   1 From 3fecbdac2fe503fb6896ec08dd2474958d198d62 Mon Sep 17 00:00:00 2001
   2 From: Hans de Goede <hdegoede@redhat.com>
   3 Date: Sun, 24 May 2015 12:01:16 +0200
   4 Subject: [PATCH] mtd: nand: nand_decode_ext_id(): Fill in ecc strength and
   5  size for Samsung
   6
   7 On some nand controllers with hw-ecc the controller code wants to know the
   8 ecc strength and size and having these as 0, 0 is not accepted.
   9
  10 Specifying these in devicetree is possible but undesirable as the nand
  11 may be different in different production runs of the same board, so it
  12 is better to get this info from the nand id where possible.
  13
  14 This commit adds code to read the ecc strength and size from the nand for
  15 Samsung extended-id nands. This code is based on the info for the 5th
  16 id byte in the datasheets for the following Samsung nands: K9GAG08U0E,
  17 K9GAG08U0F, K9GAG08X0D, K9GBG08U0A, K9GBG08U0B. These all use these bits
  18 in the exact same way.
  19
  20 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  21 ---
  22  drivers/mtd/nand/nand_base.c | 35 +++++++++++++++++++++++++++++++++++
  23  1 file changed, 35 insertions(+)
  24
  25 diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
  26 index 51642c6..e3d4d8e 100644
  27 --- a/drivers/mtd/nand/nand_base.c
  28 +++ b/drivers/mtd/nand/nand_base.c
  29 @@ -4063,6 +4063,41 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
  30                 mtd->erasesize = (128 * 1024) <<
  31                         (((extid >> 1) & 0x04) | (extid & 0x03));
  32                 *busw = 0;
  33 +               /* Calc ecc strength and size from 5th id byte*/
  34 +               switch ((id_data[4] >> 4) & 0x07) {
  35 +               case 0:
  36 +                       chip->ecc_strength_ds = 1;
  37 +                       chip->ecc_step_ds = 512;
  38 +                       break;
  39 +               case 1:
  40 +                       chip->ecc_strength_ds = 2;
  41 +                       chip->ecc_step_ds = 512;
  42 +                       break;
  43 +               case 2:
  44 +                       chip->ecc_strength_ds = 4;
  45 +                       chip->ecc_step_ds = 512;
  46 +                       break;
  47 +               case 3:
  48 +                       chip->ecc_strength_ds = 8;
  49 +                       chip->ecc_step_ds = 512;
  50 +                       break;
  51 +               case 4:
  52 +                       chip->ecc_strength_ds = 16;
  53 +                       chip->ecc_step_ds = 512;
  54 +                       break;
  55 +               case 5:
  56 +                       chip->ecc_strength_ds = 24;
  57 +                       chip->ecc_step_ds = 1024;
  58 +                       break;
  59 +               case 6:
  60 +                       chip->ecc_strength_ds = 40;
  61 +                       chip->ecc_step_ds = 1024;
  62 +                       break;
  63 +               case 7:
  64 +                       chip->ecc_strength_ds = 60;
  65 +                       chip->ecc_step_ds = 1024;
  66 +                       break;
  67 +               }
  68         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
  69                         !nand_is_slc(chip)) {
  70                 unsigned int tmp;