sunxi: add support for 4.1
[openwrt/openwrt.git] / target / linux / sunxi / patches-4.1 / 126-2-dt-sun5i-add-nand-ctrlpin-defs.patch
1 From a8ad7637cec0c2c2b1322d78b142beea4621dd23 Mon Sep 17 00:00:00 2001
2 From: Hans de Goede <hdegoede@redhat.com>
3 Date: Tue, 26 May 2015 17:18:26 +0200
4 Subject: [PATCH] ARM: dts: sun5i: Add NAND controller pin definitions
5
6 Define the NAND controller pin configs.
7
8 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
9 ---
10 arch/arm/boot/dts/sun5i-a10s.dtsi | 14 ++++++++++++++
11 arch/arm/boot/dts/sun5i.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
12 2 files changed, 52 insertions(+)
13
14 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
15 index f11efb7..1962ec9 100644
16 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
17 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
18 @@ -201,6 +201,20 @@
19 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
20 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
21 };
22 +
23 + nand_cs2_pins_a: nand_cs@2 {
24 + allwinner,pins = "PC17";
25 + allwinner,function = "nand0";
26 + allwinner,drive = <0>;
27 + allwinner,pull = <0>;
28 + };
29 +
30 + nand_cs3_pins_a: nand_cs@3 {
31 + allwinner,pins = "PC18";
32 + allwinner,function = "nand0";
33 + allwinner,drive = <0>;
34 + allwinner,pull = <0>;
35 + };
36 };
37
38 &sram_a {
39 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
40 index 772f8d8..0dc7c96 100644
41 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
42 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
43 @@ -544,6 +544,44 @@
44 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
45 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
46 };
47 +
48 + nand_pins_a: nand_base0@0 {
49 + allwinner,pins = "PC0", "PC1", "PC2",
50 + "PC5", "PC8", "PC9", "PC10",
51 + "PC11", "PC12", "PC13", "PC14",
52 + "PC15";
53 + allwinner,function = "nand0";
54 + allwinner,drive = <0>;
55 + allwinner,pull = <0>;
56 + };
57 +
58 + nand_cs0_pins_a: nand_cs@0 {
59 + allwinner,pins = "PC4";
60 + allwinner,function = "nand0";
61 + allwinner,drive = <0>;
62 + allwinner,pull = <0>;
63 + };
64 +
65 + nand_cs1_pins_a: nand_cs@1 {
66 + allwinner,pins = "PC3";
67 + allwinner,function = "nand0";
68 + allwinner,drive = <0>;
69 + allwinner,pull = <0>;
70 + };
71 +
72 + nand_rb0_pins_a: nand_rb@0 {
73 + allwinner,pins = "PC6";
74 + allwinner,function = "nand0";
75 + allwinner,drive = <0>;
76 + allwinner,pull = <0>;
77 + };
78 +
79 + nand_rb1_pins_a: nand_rb@1 {
80 + allwinner,pins = "PC7";
81 + allwinner,function = "nand0";
82 + allwinner,drive = <0>;
83 + allwinner,pull = <0>;
84 + };
85 };
86
87 timer@01c20c00 {