sunxi: add support for 4.1
[openwrt/openwrt.git] / target / linux / sunxi / patches-4.1 / 163-clk-sunxi-mod1-clock.patch
1 From 7fbbca069587b7f467e76f583ad640977de1a4ff Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Fri, 18 Jul 2014 15:28:02 -0300
4 Subject: [PATCH] clk: sunxi: mod1 clock support
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 The module 1 type of clocks consist of a gate and a mux and are used on
10 the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
11 SPDIF. This commit adds support for them on the sunxi clock driver.
12
13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
14 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
15 ---
16 drivers/clk/sunxi/Makefile | 1 +
17 drivers/clk/sunxi/clk-a10-mod1.c | 69 ++++++++++++++++++++++++++++++++++++++++
18 2 files changed, 70 insertions(+)
19 create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c
20
21 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
22 index 6fa845e..960eeab 100644
23 --- a/drivers/clk/sunxi/Makefile
24 +++ b/drivers/clk/sunxi/Makefile
25 @@ -5,6 +5,7 @@
26 obj-y += clk-sunxi.o clk-factors.o
27 obj-y += clk-a10-codec.o
28 obj-y += clk-a10-hosc.o
29 +obj-y += clk-a10-mod1.o
30 obj-y += clk-a10-pll2.o
31 obj-y += clk-a20-gmac.o
32 obj-y += clk-mod0.o
33 diff --git a/drivers/clk/sunxi/clk-a10-mod1.c b/drivers/clk/sunxi/clk-a10-mod1.c
34 new file mode 100644
35 index 0000000..1357641
36 --- /dev/null
37 +++ b/drivers/clk/sunxi/clk-a10-mod1.c
38 @@ -0,0 +1,69 @@
39 +/*
40 + * Copyright 2013 Emilio López
41 + *
42 + * Emilio López <emilio@elopez.com.ar>
43 + *
44 + * This program is free software; you can redistribute it and/or modify
45 + * it under the terms of the GNU General Public License as published by
46 + * the Free Software Foundation; either version 2 of the License, or
47 + * (at your option) any later version.
48 + *
49 + * This program is distributed in the hope that it will be useful,
50 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
51 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
52 + * GNU General Public License for more details.
53 + */
54 +
55 +#include <linux/clk-provider.h>
56 +#include <linux/clkdev.h>
57 +#include <linux/of.h>
58 +#include <linux/of_address.h>
59 +
60 +static DEFINE_SPINLOCK(mod1_lock);
61 +
62 +#define SUN4I_MOD1_ENABLE 31
63 +#define SUN4I_MOD1_MUX 16
64 +#define SUN4I_MOD1_MUX_WIDTH 2
65 +#define SUN4I_MOD1_MAX_PARENTS 4
66 +
67 +static void __init sun4i_mod1_clk_setup(struct device_node *node)
68 +{
69 + struct clk *clk;
70 + struct clk_mux *mux;
71 + struct clk_gate *gate;
72 + const char *parents[4];
73 + const char *clk_name = node->name;
74 + void __iomem *reg;
75 + int i = 0;
76 +
77 + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
78 + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
79 + if (!mux || !gate) {
80 + kfree(mux);
81 + kfree(gate);
82 + return;
83 + }
84 +
85 + of_property_read_string(node, "clock-output-names", &clk_name);
86 + reg = of_iomap(node, 0);
87 +
88 + while (i < SUN4I_MOD1_MAX_PARENTS &&
89 + (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
90 + i++;
91 +
92 + gate->reg = reg;
93 + gate->bit_idx = SUN4I_MOD1_ENABLE;
94 + gate->lock = &mod1_lock;
95 + mux->reg = reg;
96 + mux->shift = SUN4I_MOD1_MUX;
97 + mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
98 + mux->lock = &mod1_lock;
99 +
100 + clk = clk_register_composite(NULL, clk_name, parents, i,
101 + &mux->hw, &clk_mux_ops,
102 + NULL, NULL,
103 + &gate->hw, &clk_gate_ops, 0);
104 + if (!IS_ERR(clk))
105 + of_clk_add_provider(node, of_clk_src_simple_get, clk);
106 +}
107 +CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk", sun4i_mod1_clk_setup);