target/linux/sunxi/patches-4.1/163-clk-sunxi-mod1-clock.patch

   1 From 7fbbca069587b7f467e76f583ad640977de1a4ff Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Fri, 18 Jul 2014 15:28:02 -0300
   4 Subject: [PATCH] clk: sunxi: mod1 clock support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The module 1 type of clocks consist of a gate and a mux and are used on
  10 the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
  11 SPDIF. This commit adds support for them on the sunxi clock driver.
  12
  13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  14 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  15 ---
  16  drivers/clk/sunxi/Makefile       |  1 +
  17  drivers/clk/sunxi/clk-a10-mod1.c | 69 ++++++++++++++++++++++++++++++++++++++++
  18  2 files changed, 70 insertions(+)
  19  create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c
  20
  21 --- a/drivers/clk/sunxi/Makefile
  22 +++ b/drivers/clk/sunxi/Makefile
  23 @@ -5,6 +5,7 @@
  24  obj-y += clk-sunxi.o clk-factors.o
  25  obj-y += clk-a10-codec.o
  26  obj-y += clk-a10-hosc.o
  27 +obj-y += clk-a10-mod1.o
  28  obj-y += clk-a10-pll2.o
  29  obj-y += clk-a20-gmac.o
  30  obj-y += clk-mod0.o
  31 --- /dev/null
  32 +++ b/drivers/clk/sunxi/clk-a10-mod1.c
  33 @@ -0,0 +1,69 @@
  34 +/*
  35 + * Copyright 2013 Emilio López
  36 + *
  37 + * Emilio López <emilio@elopez.com.ar>
  38 + *
  39 + * This program is free software; you can redistribute it and/or modify
  40 + * it under the terms of the GNU General Public License as published by
  41 + * the Free Software Foundation; either version 2 of the License, or
  42 + * (at your option) any later version.
  43 + *
  44 + * This program is distributed in the hope that it will be useful,
  45 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  46 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  47 + * GNU General Public License for more details.
  48 + */
  49 +
  50 +#include <linux/clk-provider.h>
  51 +#include <linux/clkdev.h>
  52 +#include <linux/of.h>
  53 +#include <linux/of_address.h>
  54 +
  55 +static DEFINE_SPINLOCK(mod1_lock);
  56 +
  57 +#define SUN4I_MOD1_ENABLE      31
  58 +#define SUN4I_MOD1_MUX         16
  59 +#define SUN4I_MOD1_MUX_WIDTH   2
  60 +#define SUN4I_MOD1_MAX_PARENTS 4
  61 +
  62 +static void __init sun4i_mod1_clk_setup(struct device_node *node)
  63 +{
  64 +       struct clk *clk;
  65 +       struct clk_mux *mux;
  66 +       struct clk_gate *gate;
  67 +       const char *parents[4];
  68 +       const char *clk_name = node->name;
  69 +       void __iomem *reg;
  70 +       int i = 0;
  71 +
  72 +       mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  73 +       gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  74 +       if (!mux || !gate) {
  75 +               kfree(mux);
  76 +               kfree(gate);
  77 +               return;
  78 +       }
  79 +
  80 +       of_property_read_string(node, "clock-output-names", &clk_name);
  81 +       reg = of_iomap(node, 0);
  82 +
  83 +       while (i < SUN4I_MOD1_MAX_PARENTS &&
  84 +              (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
  85 +               i++;
  86 +
  87 +       gate->reg = reg;
  88 +       gate->bit_idx = SUN4I_MOD1_ENABLE;
  89 +       gate->lock = &mod1_lock;
  90 +       mux->reg = reg;
  91 +       mux->shift = SUN4I_MOD1_MUX;
  92 +       mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
  93 +       mux->lock = &mod1_lock;
  94 +
  95 +       clk = clk_register_composite(NULL, clk_name, parents, i,
  96 +                                    &mux->hw, &clk_mux_ops,
  97 +                                    NULL, NULL,
  98 +                                    &gate->hw, &clk_gate_ops, 0);
  99 +       if (!IS_ERR(clk))
 100 +               of_clk_add_provider(node, of_clk_src_simple_get, clk);
 101 +}
 102 +CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk", sun4i_mod1_clk_setup);