target/linux/sunxi/patches-4.1/164-1-dt-add-pll2-into-dtsi.patch

   1 From 32bb743195e1e48c48fc5cefd7c6ecdce56046a3 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Fri, 18 Jul 2014 15:58:44 -0300
   4 Subject: [PATCH] ARM: sunxi: Add PLL2 support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds the PLL2 definition to the sun4i, sun5i and sun7i
  10 device trees. PLL2 is used to clock audio devices.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  14 ---
  15  arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
  16  arch/arm/boot/dts/sun5i.dtsi     | 8 ++++++++
  17  arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
  18  3 files changed, 24 insertions(+)
  19
  20 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
  21 index 30f663a..fab13af 100644
  22 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  23 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  24 @@ -195,6 +195,14 @@
  25                         clock-output-names = "pll1";
  26                 };
  27
  28 +               pll2: clk@01c20008 {
  29 +                       #clock-cells = <1>;
  30 +                       compatible = "allwinner,sun4i-a10-b-pll2-clk";
  31 +                       reg = <0x01c20008 0x4>;
  32 +                       clocks = <&osc24M>;
  33 +                       clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
  34 +               };
  35 +
  36                 pll4: clk@01c20018 {
  37                         #clock-cells = <0>;
  38                         compatible = "allwinner,sun4i-a10-pll1-clk";
  39 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
  40 index 53d3ead..a4b6a66 100644
  41 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
  42 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
  43 @@ -102,6 +102,14 @@
  44                         clock-output-names = "pll1";
  45                 };
  46
  47 +               pll2: clk@01c20008 {
  48 +                       #clock-cells = <1>;
  49 +                       compatible = "allwinner,sun4i-a10-b-pll2-clk";
  50 +                       reg = <0x01c20008 0x4>;
  51 +                       clocks = <&osc24M>;
  52 +                       clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
  53 +               };
  54 +
  55                 pll4: clk@01c20018 {
  56                         #clock-cells = <0>;
  57                         compatible = "allwinner,sun4i-a10-pll1-clk";
  58 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
  59 index 7549f1b..12d9ffd 100644
  60 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  61 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  62 @@ -199,6 +199,14 @@
  63                         clock-output-names = "pll1";
  64                 };
  65
  66 +               pll2: clk@01c20008 {
  67 +                       #clock-cells = <1>;
  68 +                       compatible = "allwinner,sun4i-a10-b-pll2-clk";
  69 +                       reg = <0x01c20008 0x4>;
  70 +                       clocks = <&osc24M>;
  71 +                       clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
  72 +               };
  73 +
  74                 pll4: clk@01c20018 {
  75                         #clock-cells = <0>;
  76                         compatible = "allwinner,sun7i-a20-pll4-clk";