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kernel: update 4.1 to 4.1.5
[openwrt/openwrt.git] / target / linux / sunxi / patches-4.1 / 170-musb-add-driver.patch
1 From 744543c599c420bcddca08cd2e2713b82a008328 Mon Sep 17 00:00:00 2001
2 From: Hans de Goede <hdegoede@redhat.com>
3 Date: Wed, 8 Jul 2015 16:41:38 +0200
4 Subject: [PATCH] usb: musb: sunxi: Add support for the Allwinner sunxi musb
5 controller
6
7 This is based on initial code to get the Allwinner sunxi musb controller
8 supported by Chen-Yu Tsai and Roman Byshko.
9
10 This adds support for the Allwinner sunxi musb controller in both host only
11 and otg mode. Peripheral only mode is not supported, as no boards use that.
12
13 This has been tested on a cubietruck (A20 SoC) and an UTOO P66 tablet
14 (A13 SoC) with a variety of devices in host mode and with the g_serial gadget
15 driver in peripheral mode, plugging otg / host cables in/out a lot of times
16 in all possible imaginable plug orders.
17
18 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
19 Signed-off-by: Felipe Balbi <balbi@ti.com>
20 ---
21 .../bindings/usb/allwinner,sun4i-a10-musb.txt | 27 +
22 drivers/usb/musb/Kconfig | 13 +-
23 drivers/usb/musb/Makefile | 1 +
24 drivers/usb/musb/sunxi.c | 703 +++++++++++++++++++++
25 4 files changed, 743 insertions(+), 1 deletion(-)
26 create mode 100644 Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
27 create mode 100644 drivers/usb/musb/sunxi.c
28
29 --- /dev/null
30 +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
31 @@ -0,0 +1,27 @@
32 +Allwinner sun4i A10 musb DRC/OTG controller
33 +-------------------------------------------
34 +
35 +Required properties:
36 + - compatible : "allwinner,sun4i-a10-musb"
37 + - reg : mmio address range of the musb controller
38 + - clocks : clock specifier for the musb controller ahb gate clock
39 + - interrupts : interrupt to which the musb controller is connected
40 + - interrupt-names : must be "mc"
41 + - phys : phy specifier for the otg phy
42 + - phy-names : must be "usb"
43 + - dr_mode : Dual-Role mode must be "host" or "otg"
44 + - extcon : extcon specifier for the otg phy
45 +
46 +Example:
47 +
48 + usb_otg: usb@01c13000 {
49 + compatible = "allwinner,sun4i-a10-musb";
50 + reg = <0x01c13000 0x0400>;
51 + clocks = <&ahb_gates 0>;
52 + interrupts = <38>;
53 + interrupt-names = "mc";
54 + phys = <&usbphy 0>;
55 + phy-names = "usb";
56 + extcon = <&usbphy 0>;
57 + status = "disabled";
58 + };
59 --- a/drivers/usb/musb/Kconfig
60 +++ b/drivers/usb/musb/Kconfig
61 @@ -5,7 +5,7 @@
62
63 # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
64 config USB_MUSB_HDRC
65 - tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
66 + tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, AW, ...)'
67 depends on (USB || USB_GADGET)
68 help
69 Say Y here if your system has a dual role high speed USB
70 @@ -20,6 +20,8 @@ config USB_MUSB_HDRC
71 Analog Devices parts using this IP include Blackfin BF54x,
72 BF525 and BF527.
73
74 + Allwinner SoCs using this IP include A10, A13, A20, ...
75 +
76 If you do not know what this is, please say N.
77
78 To compile this driver as a module, choose M here; the
79 @@ -60,6 +62,15 @@ endchoice
80
81 comment "Platform Glue Layer"
82
83 +config USB_MUSB_SUNXI
84 + tristate "Allwinner (sunxi)"
85 + depends on ARCH_SUNXI
86 + depends on NOP_USB_XCEIV
87 + depends on PHY_SUN4I_USB
88 + depends on EXTCON
89 + depends on GENERIC_PHY
90 + select SUNXI_SRAM
91 +
92 config USB_MUSB_DAVINCI
93 tristate "DaVinci"
94 depends on ARCH_DAVINCI_DMx
95 --- a/drivers/usb/musb/Makefile
96 +++ b/drivers/usb/musb/Makefile
97 @@ -20,6 +20,7 @@ obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.
98 obj-$(CONFIG_USB_MUSB_BLACKFIN) += blackfin.o
99 obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
100 obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o
101 +obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
102
103
104 obj-$(CONFIG_USB_MUSB_AM335X_CHILD) += musb_am335x.o
105 --- /dev/null
106 +++ b/drivers/usb/musb/sunxi.c
107 @@ -0,0 +1,703 @@
108 +/*
109 + * Allwinner sun4i MUSB Glue Layer
110 + *
111 + * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
112 + *
113 + * Based on code from
114 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
115 + *
116 + * This program is free software; you can redistribute it and/or modify
117 + * it under the terms of the GNU General Public License as published by
118 + * the Free Software Foundation; either version 2 of the License, or
119 + * (at your option) any later version.
120 + *
121 + * This program is distributed in the hope that it will be useful,
122 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
123 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
124 + * GNU General Public License for more details.
125 + */
126 +
127 +#include <linux/clk.h>
128 +#include <linux/err.h>
129 +#include <linux/extcon.h>
130 +#include <linux/io.h>
131 +#include <linux/kernel.h>
132 +#include <linux/module.h>
133 +#include <linux/of.h>
134 +#include <linux/phy/phy-sun4i-usb.h>
135 +#include <linux/platform_device.h>
136 +#include <linux/soc/sunxi/sunxi_sram.h>
137 +#include <linux/usb/musb.h>
138 +#include <linux/usb/of.h>
139 +#include <linux/usb/usb_phy_generic.h>
140 +#include <linux/workqueue.h>
141 +#include "musb_core.h"
142 +
143 +/*
144 + * Register offsets, note sunxi musb has a different layout then most
145 + * musb implementations, we translate the layout in musb_readb & friends.
146 + */
147 +#define SUNXI_MUSB_POWER 0x0040
148 +#define SUNXI_MUSB_DEVCTL 0x0041
149 +#define SUNXI_MUSB_INDEX 0x0042
150 +#define SUNXI_MUSB_VEND0 0x0043
151 +#define SUNXI_MUSB_INTRTX 0x0044
152 +#define SUNXI_MUSB_INTRRX 0x0046
153 +#define SUNXI_MUSB_INTRTXE 0x0048
154 +#define SUNXI_MUSB_INTRRXE 0x004a
155 +#define SUNXI_MUSB_INTRUSB 0x004c
156 +#define SUNXI_MUSB_INTRUSBE 0x0050
157 +#define SUNXI_MUSB_FRAME 0x0054
158 +#define SUNXI_MUSB_TXFIFOSZ 0x0090
159 +#define SUNXI_MUSB_TXFIFOADD 0x0092
160 +#define SUNXI_MUSB_RXFIFOSZ 0x0094
161 +#define SUNXI_MUSB_RXFIFOADD 0x0096
162 +#define SUNXI_MUSB_FADDR 0x0098
163 +#define SUNXI_MUSB_TXFUNCADDR 0x0098
164 +#define SUNXI_MUSB_TXHUBADDR 0x009a
165 +#define SUNXI_MUSB_TXHUBPORT 0x009b
166 +#define SUNXI_MUSB_RXFUNCADDR 0x009c
167 +#define SUNXI_MUSB_RXHUBADDR 0x009e
168 +#define SUNXI_MUSB_RXHUBPORT 0x009f
169 +#define SUNXI_MUSB_CONFIGDATA 0x00c0
170 +
171 +/* VEND0 bits */
172 +#define SUNXI_MUSB_VEND0_PIO_MODE 0
173 +
174 +/* flags */
175 +#define SUNXI_MUSB_FL_ENABLED 0
176 +#define SUNXI_MUSB_FL_HOSTMODE 1
177 +#define SUNXI_MUSB_FL_HOSTMODE_PEND 2
178 +#define SUNXI_MUSB_FL_VBUS_ON 3
179 +#define SUNXI_MUSB_FL_PHY_ON 4
180 +
181 +/* Our read/write methods need access and do not get passed in a musb ref :| */
182 +static struct musb *sunxi_musb;
183 +
184 +struct sunxi_glue {
185 + struct device *dev;
186 + struct platform_device *musb;
187 + struct clk *clk;
188 + struct phy *phy;
189 + struct platform_device *usb_phy;
190 + struct usb_phy *xceiv;
191 + unsigned long flags;
192 + struct work_struct work;
193 + struct extcon_dev *extcon;
194 + struct notifier_block host_nb;
195 +};
196 +
197 +/* phy_power_on / off may sleep, so we use a workqueue */
198 +static void sunxi_musb_work(struct work_struct *work)
199 +{
200 + struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
201 + bool vbus_on, phy_on;
202 +
203 + if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
204 + return;
205 +
206 + if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
207 + struct musb *musb = platform_get_drvdata(glue->musb);
208 + unsigned long flags;
209 + u8 devctl;
210 +
211 + spin_lock_irqsave(&musb->lock, flags);
212 +
213 + devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
214 + if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
215 + set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
216 + musb->xceiv->otg->default_a = 1;
217 + musb->xceiv->otg->state = OTG_STATE_A_IDLE;
218 + MUSB_HST_MODE(musb);
219 + devctl |= MUSB_DEVCTL_SESSION;
220 + } else {
221 + clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
222 + musb->xceiv->otg->default_a = 0;
223 + musb->xceiv->otg->state = OTG_STATE_B_IDLE;
224 + MUSB_DEV_MODE(musb);
225 + devctl &= ~MUSB_DEVCTL_SESSION;
226 + }
227 + writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
228 +
229 + spin_unlock_irqrestore(&musb->lock, flags);
230 + }
231 +
232 + vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
233 + phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
234 +
235 + if (phy_on != vbus_on) {
236 + if (vbus_on) {
237 + phy_power_on(glue->phy);
238 + set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
239 + } else {
240 + phy_power_off(glue->phy);
241 + clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
242 + }
243 + }
244 +}
245 +
246 +static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
247 +{
248 + struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
249 +
250 + if (is_on)
251 + set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
252 + else
253 + clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
254 +
255 + schedule_work(&glue->work);
256 +}
257 +
258 +static void sunxi_musb_pre_root_reset_end(struct musb *musb)
259 +{
260 + struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
261 +
262 + sun4i_usb_phy_set_squelch_detect(glue->phy, false);
263 +}
264 +
265 +static void sunxi_musb_post_root_reset_end(struct musb *musb)
266 +{
267 + struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
268 +
269 + sun4i_usb_phy_set_squelch_detect(glue->phy, true);
270 +}
271 +
272 +static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
273 +{
274 + struct musb *musb = __hci;
275 + unsigned long flags;
276 +
277 + spin_lock_irqsave(&musb->lock, flags);
278 +
279 + musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
280 + if (musb->int_usb)
281 + writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
282 +
283 + /*
284 + * sunxi musb often signals babble on low / full speed device
285 + * disconnect, without ever raising MUSB_INTR_DISCONNECT, since
286 + * normally babble never happens treat it as disconnect.
287 + */
288 + if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
289 + musb->int_usb &= ~MUSB_INTR_BABBLE;
290 + musb->int_usb |= MUSB_INTR_DISCONNECT;
291 + }
292 +
293 + if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
294 + /* ep0 FADDR must be 0 when (re)entering peripheral mode */
295 + musb_ep_select(musb->mregs, 0);
296 + musb_writeb(musb->mregs, MUSB_FADDR, 0);
297 + }
298 +
299 + musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
300 + if (musb->int_tx)
301 + writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
302 +
303 + musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
304 + if (musb->int_rx)
305 + writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
306 +
307 + musb_interrupt(musb);
308 +
309 + spin_unlock_irqrestore(&musb->lock, flags);
310 +
311 + return IRQ_HANDLED;
312 +}
313 +
314 +static int sunxi_musb_host_notifier(struct notifier_block *nb,
315 + unsigned long event, void *ptr)
316 +{
317 + struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
318 +
319 + if (event)
320 + set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
321 + else
322 + clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
323 +
324 + set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
325 + schedule_work(&glue->work);
326 +
327 + return NOTIFY_DONE;
328 +}
329 +
330 +static int sunxi_musb_init(struct musb *musb)
331 +{
332 + struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
333 + int ret;
334 +
335 + sunxi_musb = musb;
336 + musb->phy = glue->phy;
337 + musb->xceiv = glue->xceiv;
338 +
339 + ret = sunxi_sram_claim(musb->controller->parent);
340 + if (ret)
341 + return ret;
342 +
343 + ret = clk_prepare_enable(glue->clk);
344 + if (ret)
345 + goto error_sram_release;
346 +
347 + writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
348 +
349 + /* Register notifier before calling phy_init() */
350 + if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) {
351 + ret = extcon_register_notifier(glue->extcon, EXTCON_USB_HOST,
352 + &glue->host_nb);
353 + if (ret)
354 + goto error_clk_disable;
355 + }
356 +
357 + ret = phy_init(glue->phy);
358 + if (ret)
359 + goto error_unregister_notifier;
360 +
361 + if (musb->port_mode == MUSB_PORT_MODE_HOST) {
362 + ret = phy_power_on(glue->phy);
363 + if (ret)
364 + goto error_phy_exit;
365 + set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
366 + /* Stop musb work from turning vbus off again */
367 + set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
368 + }
369 +
370 + musb->isr = sunxi_musb_interrupt;
371 +
372 + /* Stop the musb-core from doing runtime pm (not supported on sunxi) */
373 + pm_runtime_get(musb->controller);
374 +
375 + return 0;
376 +
377 +error_phy_exit:
378 + phy_exit(glue->phy);
379 +error_unregister_notifier:
380 + if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
381 + extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
382 + &glue->host_nb);
383 +error_clk_disable:
384 + clk_disable_unprepare(glue->clk);
385 +error_sram_release:
386 + sunxi_sram_release(musb->controller->parent);
387 + return ret;
388 +}
389 +
390 +static int sunxi_musb_exit(struct musb *musb)
391 +{
392 + struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
393 +
394 + pm_runtime_put(musb->controller);
395 +
396 + cancel_work_sync(&glue->work);
397 + if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
398 + phy_power_off(glue->phy);
399 +
400 + phy_exit(glue->phy);
401 +
402 + if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
403 + extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
404 + &glue->host_nb);
405 +
406 + clk_disable_unprepare(glue->clk);
407 + sunxi_sram_release(musb->controller->parent);
408 +
409 + return 0;
410 +}
411 +
412 +static void sunxi_musb_enable(struct musb *musb)
413 +{
414 + struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
415 +
416 + /* musb_core does not call us in a balanced manner */
417 + if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
418 + return;
419 +
420 + schedule_work(&glue->work);
421 +}
422 +
423 +static void sunxi_musb_disable(struct musb *musb)
424 +{
425 + struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
426 +
427 + clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
428 +}
429 +
430 +/*
431 + * sunxi musb register layout
432 + * 0x00 - 0x17 fifo regs, 1 long per fifo
433 + * 0x40 - 0x57 generic control regs (power - frame)
434 + * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
435 + * 0x90 - 0x97 fifo control regs (indexed)
436 + * 0x98 - 0x9f multipoint / busctl regs (indexed)
437 + * 0xc0 configdata reg
438 + */
439 +
440 +static u32 sunxi_musb_fifo_offset(u8 epnum)
441 +{
442 + return (epnum * 4);
443 +}
444 +
445 +static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
446 +{
447 + WARN_ONCE(offset != 0,
448 + "sunxi_musb_ep_offset called with non 0 offset\n");
449 +
450 + return 0x80; /* indexed, so ignore epnum */
451 +}
452 +
453 +static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
454 +{
455 + return SUNXI_MUSB_TXFUNCADDR + offset;
456 +}
457 +
458 +static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset)
459 +{
460 + if (addr == sunxi_musb->mregs) {
461 + /* generic control or fifo control reg access */
462 + switch (offset) {
463 + case MUSB_FADDR:
464 + return readb(addr + SUNXI_MUSB_FADDR);
465 + case MUSB_POWER:
466 + return readb(addr + SUNXI_MUSB_POWER);
467 + case MUSB_INTRUSB:
468 + return readb(addr + SUNXI_MUSB_INTRUSB);
469 + case MUSB_INTRUSBE:
470 + return readb(addr + SUNXI_MUSB_INTRUSBE);
471 + case MUSB_INDEX:
472 + return readb(addr + SUNXI_MUSB_INDEX);
473 + case MUSB_TESTMODE:
474 + return 0; /* No testmode on sunxi */
475 + case MUSB_DEVCTL:
476 + return readb(addr + SUNXI_MUSB_DEVCTL);
477 + case MUSB_TXFIFOSZ:
478 + return readb(addr + SUNXI_MUSB_TXFIFOSZ);
479 + case MUSB_RXFIFOSZ:
480 + return readb(addr + SUNXI_MUSB_RXFIFOSZ);
481 + case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
482 + return readb(addr + SUNXI_MUSB_CONFIGDATA);
483 + /* Offset for these is fixed by sunxi_musb_busctl_offset() */
484 + case SUNXI_MUSB_TXFUNCADDR:
485 + case SUNXI_MUSB_TXHUBADDR:
486 + case SUNXI_MUSB_TXHUBPORT:
487 + case SUNXI_MUSB_RXFUNCADDR:
488 + case SUNXI_MUSB_RXHUBADDR:
489 + case SUNXI_MUSB_RXHUBPORT:
490 + /* multipoint / busctl reg access */
491 + return readb(addr + offset);
492 + default:
493 + dev_err(sunxi_musb->controller->parent,
494 + "Error unknown readb offset %u\n", offset);
495 + return 0;
496 + }
497 + } else if (addr == (sunxi_musb->mregs + 0x80)) {
498 + /* ep control reg access */
499 + /* sunxi has a 2 byte hole before the txtype register */
500 + if (offset >= MUSB_TXTYPE)
501 + offset += 2;
502 + return readb(addr + offset);
503 + }
504 +
505 + dev_err(sunxi_musb->controller->parent,
506 + "Error unknown readb at 0x%x bytes offset\n",
507 + (int)(addr - sunxi_musb->mregs));
508 + return 0;
509 +}
510 +
511 +static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
512 +{
513 + if (addr == sunxi_musb->mregs) {
514 + /* generic control or fifo control reg access */
515 + switch (offset) {
516 + case MUSB_FADDR:
517 + return writeb(data, addr + SUNXI_MUSB_FADDR);
518 + case MUSB_POWER:
519 + return writeb(data, addr + SUNXI_MUSB_POWER);
520 + case MUSB_INTRUSB:
521 + return writeb(data, addr + SUNXI_MUSB_INTRUSB);
522 + case MUSB_INTRUSBE:
523 + return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
524 + case MUSB_INDEX:
525 + return writeb(data, addr + SUNXI_MUSB_INDEX);
526 + case MUSB_TESTMODE:
527 + if (data)
528 + dev_warn(sunxi_musb->controller->parent,
529 + "sunxi-musb does not have testmode\n");
530 + return;
531 + case MUSB_DEVCTL:
532 + return writeb(data, addr + SUNXI_MUSB_DEVCTL);
533 + case MUSB_TXFIFOSZ:
534 + return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
535 + case MUSB_RXFIFOSZ:
536 + return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
537 + /* Offset for these is fixed by sunxi_musb_busctl_offset() */
538 + case SUNXI_MUSB_TXFUNCADDR:
539 + case SUNXI_MUSB_TXHUBADDR:
540 + case SUNXI_MUSB_TXHUBPORT:
541 + case SUNXI_MUSB_RXFUNCADDR:
542 + case SUNXI_MUSB_RXHUBADDR:
543 + case SUNXI_MUSB_RXHUBPORT:
544 + /* multipoint / busctl reg access */
545 + return writeb(data, addr + offset);
546 + default:
547 + dev_err(sunxi_musb->controller->parent,
548 + "Error unknown writeb offset %u\n", offset);
549 + return;
550 + }
551 + } else if (addr == (sunxi_musb->mregs + 0x80)) {
552 + /* ep control reg access */
553 + if (offset >= MUSB_TXTYPE)
554 + offset += 2;
555 + return writeb(data, addr + offset);
556 + }
557 +
558 + dev_err(sunxi_musb->controller->parent,
559 + "Error unknown writeb at 0x%x bytes offset\n",
560 + (int)(addr - sunxi_musb->mregs));
561 +}
562 +
563 +static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset)
564 +{
565 + if (addr == sunxi_musb->mregs) {
566 + /* generic control or fifo control reg access */
567 + switch (offset) {
568 + case MUSB_INTRTX:
569 + return readw(addr + SUNXI_MUSB_INTRTX);
570 + case MUSB_INTRRX:
571 + return readw(addr + SUNXI_MUSB_INTRRX);
572 + case MUSB_INTRTXE:
573 + return readw(addr + SUNXI_MUSB_INTRTXE);
574 + case MUSB_INTRRXE:
575 + return readw(addr + SUNXI_MUSB_INTRRXE);
576 + case MUSB_FRAME:
577 + return readw(addr + SUNXI_MUSB_FRAME);
578 + case MUSB_TXFIFOADD:
579 + return readw(addr + SUNXI_MUSB_TXFIFOADD);
580 + case MUSB_RXFIFOADD:
581 + return readw(addr + SUNXI_MUSB_RXFIFOADD);
582 + case MUSB_HWVERS:
583 + return 0; /* sunxi musb version is not known */
584 + default:
585 + dev_err(sunxi_musb->controller->parent,
586 + "Error unknown readw offset %u\n", offset);
587 + return 0;
588 + }
589 + } else if (addr == (sunxi_musb->mregs + 0x80)) {
590 + /* ep control reg access */
591 + return readw(addr + offset);
592 + }
593 +
594 + dev_err(sunxi_musb->controller->parent,
595 + "Error unknown readw at 0x%x bytes offset\n",
596 + (int)(addr - sunxi_musb->mregs));
597 + return 0;
598 +}
599 +
600 +static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
601 +{
602 + if (addr == sunxi_musb->mregs) {
603 + /* generic control or fifo control reg access */
604 + switch (offset) {
605 + case MUSB_INTRTX:
606 + return writew(data, addr + SUNXI_MUSB_INTRTX);
607 + case MUSB_INTRRX:
608 + return writew(data, addr + SUNXI_MUSB_INTRRX);
609 + case MUSB_INTRTXE:
610 + return writew(data, addr + SUNXI_MUSB_INTRTXE);
611 + case MUSB_INTRRXE:
612 + return writew(data, addr + SUNXI_MUSB_INTRRXE);
613 + case MUSB_FRAME:
614 + return writew(data, addr + SUNXI_MUSB_FRAME);
615 + case MUSB_TXFIFOADD:
616 + return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
617 + case MUSB_RXFIFOADD:
618 + return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
619 + default:
620 + dev_err(sunxi_musb->controller->parent,
621 + "Error unknown writew offset %u\n", offset);
622 + return;
623 + }
624 + } else if (addr == (sunxi_musb->mregs + 0x80)) {
625 + /* ep control reg access */
626 + return writew(data, addr + offset);
627 + }
628 +
629 + dev_err(sunxi_musb->controller->parent,
630 + "Error unknown writew at 0x%x bytes offset\n",
631 + (int)(addr - sunxi_musb->mregs));
632 +}
633 +
634 +static const struct musb_platform_ops sunxi_musb_ops = {
635 + .quirks = MUSB_INDEXED_EP,
636 + .init = sunxi_musb_init,
637 + .exit = sunxi_musb_exit,
638 + .enable = sunxi_musb_enable,
639 + .disable = sunxi_musb_disable,
640 + .fifo_offset = sunxi_musb_fifo_offset,
641 + .ep_offset = sunxi_musb_ep_offset,
642 + .busctl_offset = sunxi_musb_busctl_offset,
643 + .readb = sunxi_musb_readb,
644 + .writeb = sunxi_musb_writeb,
645 + .readw = sunxi_musb_readw,
646 + .writew = sunxi_musb_writew,
647 + .set_vbus = sunxi_musb_set_vbus,
648 + .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
649 + .post_root_reset_end = sunxi_musb_post_root_reset_end,
650 +};
651 +
652 +/* Allwinner OTG supports up to 5 endpoints */
653 +#define SUNXI_MUSB_MAX_EP_NUM 6
654 +#define SUNXI_MUSB_RAM_BITS 11
655 +
656 +static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
657 + MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
658 + MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
659 + MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
660 + MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
661 + MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
662 + MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
663 + MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
664 + MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
665 + MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
666 + MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
667 +};
668 +
669 +static struct musb_hdrc_config sunxi_musb_hdrc_config = {
670 + .fifo_cfg = sunxi_musb_mode_cfg,
671 + .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
672 + .multipoint = true,
673 + .dyn_fifo = true,
674 + .soft_con = true,
675 + .num_eps = SUNXI_MUSB_MAX_EP_NUM,
676 + .ram_bits = SUNXI_MUSB_RAM_BITS,
677 + .dma = 0,
678 +};
679 +
680 +static int sunxi_musb_probe(struct platform_device *pdev)
681 +{
682 + struct musb_hdrc_platform_data pdata;
683 + struct platform_device_info pinfo;
684 + struct sunxi_glue *glue;
685 + struct device_node *np = pdev->dev.of_node;
686 + int ret;
687 +
688 + if (!np) {
689 + dev_err(&pdev->dev, "Error no device tree node found\n");
690 + return -EINVAL;
691 + }
692 +
693 + glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
694 + if (!glue)
695 + return -ENOMEM;
696 +
697 + memset(&pdata, 0, sizeof(pdata));
698 + switch (of_usb_get_dr_mode(np)) {
699 +#if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
700 + case USB_DR_MODE_HOST:
701 + pdata.mode = MUSB_PORT_MODE_HOST;
702 + break;
703 +#endif
704 +#ifdef CONFIG_USB_MUSB_DUAL_ROLE
705 + case USB_DR_MODE_OTG:
706 + glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
707 + if (IS_ERR(glue->extcon)) {
708 + if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
709 + return -EPROBE_DEFER;
710 + dev_err(&pdev->dev, "Invalid or missing extcon\n");
711 + return PTR_ERR(glue->extcon);
712 + }
713 + pdata.mode = MUSB_PORT_MODE_DUAL_ROLE;
714 + break;
715 +#endif
716 + default:
717 + dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
718 + return -EINVAL;
719 + }
720 + pdata.platform_ops = &sunxi_musb_ops;
721 + pdata.config = &sunxi_musb_hdrc_config;
722 +
723 + glue->dev = &pdev->dev;
724 + INIT_WORK(&glue->work, sunxi_musb_work);
725 + glue->host_nb.notifier_call = sunxi_musb_host_notifier;
726 +
727 + glue->clk = devm_clk_get(&pdev->dev, NULL);
728 + if (IS_ERR(glue->clk)) {
729 + dev_err(&pdev->dev, "Error getting clock: %ld\n",
730 + PTR_ERR(glue->clk));
731 + return PTR_ERR(glue->clk);
732 + }
733 +
734 + glue->phy = devm_phy_get(&pdev->dev, "usb");
735 + if (IS_ERR(glue->phy)) {
736 + if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
737 + return -EPROBE_DEFER;
738 + dev_err(&pdev->dev, "Error getting phy %ld\n",
739 + PTR_ERR(glue->phy));
740 + return PTR_ERR(glue->phy);
741 + }
742 +
743 + glue->usb_phy = usb_phy_generic_register();
744 + if (IS_ERR(glue->usb_phy)) {
745 + dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
746 + PTR_ERR(glue->usb_phy));
747 + return PTR_ERR(glue->usb_phy);
748 + }
749 +
750 + glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
751 + if (IS_ERR(glue->xceiv)) {
752 + ret = PTR_ERR(glue->xceiv);
753 + dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
754 + goto err_unregister_usb_phy;
755 + }
756 +
757 + platform_set_drvdata(pdev, glue);
758 +
759 + memset(&pinfo, 0, sizeof(pinfo));
760 + pinfo.name = "musb-hdrc";
761 + pinfo.id = PLATFORM_DEVID_AUTO;
762 + pinfo.parent = &pdev->dev;
763 + pinfo.res = pdev->resource;
764 + pinfo.num_res = pdev->num_resources;
765 + pinfo.data = &pdata;
766 + pinfo.size_data = sizeof(pdata);
767 +
768 + glue->musb = platform_device_register_full(&pinfo);
769 + if (IS_ERR(glue->musb)) {
770 + ret = PTR_ERR(glue->musb);
771 + dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
772 + goto err_unregister_usb_phy;
773 + }
774 +
775 + return 0;
776 +
777 +err_unregister_usb_phy:
778 + usb_phy_generic_unregister(glue->usb_phy);
779 + return ret;
780 +}
781 +
782 +static int sunxi_musb_remove(struct platform_device *pdev)
783 +{
784 + struct sunxi_glue *glue = platform_get_drvdata(pdev);
785 + struct platform_device *usb_phy = glue->usb_phy;
786 +
787 + platform_device_unregister(glue->musb); /* Frees glue ! */
788 + usb_phy_generic_unregister(usb_phy);
789 +
790 + return 0;
791 +}
792 +
793 +static const struct of_device_id sunxi_musb_match[] = {
794 + { .compatible = "allwinner,sun4i-a10-musb", },
795 + {}
796 +};
797 +
798 +static struct platform_driver sunxi_musb_driver = {
799 + .probe = sunxi_musb_probe,
800 + .remove = sunxi_musb_remove,
801 + .driver = {
802 + .name = "musb-sunxi",
803 + .of_match_table = sunxi_musb_match,
804 + },
805 +};
806 +module_platform_driver(sunxi_musb_driver);
807 +
808 +MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
809 +MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
810 +MODULE_LICENSE("GPL v2");
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