target/linux/sunxi/patches-4.4/106-phy-add-h3-usbphys.patch

   1 From 317c5224795b41a08ba8c08573d74ba95096faa5 Mon Sep 17 00:00:00 2001
   2 From: Reinder de Haan <patchesrdh@mveas.com>
   3 Date: Fri, 11 Dec 2015 16:32:18 +0100
   4 Subject: [PATCH] phy-sun4i-usb: Add support for the host usb-phys found on the
   5  H3 SoC
   6
   7 Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
   8 not yet (fully) supported after this commit.
   9
  10 Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
  11 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  12 Acked-by: Rob Herring <robh@kernel.org>
  13 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  14 ---
  15  .../devicetree/bindings/phy/sun4i-usb-phy.txt      |  1 +
  16  drivers/phy/phy-sun4i-usb.c                        | 41 +++++++++++++++++-----
  17  2 files changed, 33 insertions(+), 9 deletions(-)
  18
  19 diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
  20 index 0cebf74..95736d7 100644
  21 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
  22 +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
  23 @@ -9,6 +9,7 @@ Required properties:
  24    * allwinner,sun7i-a20-usb-phy
  25    * allwinner,sun8i-a23-usb-phy
  26    * allwinner,sun8i-a33-usb-phy
  27 +  * allwinner,sun8i-h3-usb-phy
  28  - reg : a list of offset + length pairs
  29  - reg-names :
  30    * "phy_ctrl"
  31 diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
  32 index 35b1fa3..bae54f7 100644
  33 --- a/drivers/phy/phy-sun4i-usb.c
  34 +++ b/drivers/phy/phy-sun4i-usb.c
  35 @@ -47,6 +47,9 @@
  36  #define REG_PHYBIST                    0x08
  37  #define REG_PHYTUNE                    0x0c
  38  #define REG_PHYCTL_A33                 0x10
  39 +#define REG_PHY_UNK_H3                 0x20
  40 +
  41 +#define REG_PMU_UNK_H3                 0x10
  42
  43  #define PHYCTL_DATA                    BIT(7)
  44
  45 @@ -80,7 +83,7 @@
  46  #define PHY_DISCON_TH_SEL              0x2a
  47  #define PHY_SQUELCH_DETECT             0x3c
  48
  49 -#define MAX_PHYS                       3
  50 +#define MAX_PHYS                       4
  51
  52  /*
  53   * Note do not raise the debounce time, we must report Vusb high within 100ms
  54 @@ -92,6 +95,7 @@
  55  enum sun4i_usb_phy_type {
  56         sun4i_a10_phy,
  57         sun8i_a33_phy,
  58 +       sun8i_h3_phy,
  59  };
  60
  61  struct sun4i_usb_phy_cfg {
  62 @@ -239,6 +243,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
  63         struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
  64         struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
  65         int ret;
  66 +       u32 val;
  67
  68         ret = clk_prepare_enable(phy->clk);
  69         if (ret)
  70 @@ -250,16 +255,26 @@ static int sun4i_usb_phy_init(struct phy *_phy)
  71                 return ret;
  72         }
  73
  74 -       /* Enable USB 45 Ohm resistor calibration */
  75 -       if (phy->index == 0)
  76 -               sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
  77 +       if (data->cfg->type == sun8i_h3_phy) {
  78 +               if (phy->index == 0) {
  79 +                       val = readl(data->base + REG_PHY_UNK_H3);
  80 +                       writel(val & ~1, data->base + REG_PHY_UNK_H3);
  81 +               }
  82 +
  83 +               val = readl(phy->pmu + REG_PMU_UNK_H3);
  84 +               writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
  85 +       } else {
  86 +               /* Enable USB 45 Ohm resistor calibration */
  87 +               if (phy->index == 0)
  88 +                       sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
  89
  90 -       /* Adjust PHY's magnitude and rate */
  91 -       sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
  92 +               /* Adjust PHY's magnitude and rate */
  93 +               sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
  94
  95 -       /* Disconnect threshold adjustment */
  96 -       sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
  97 -                           data->cfg->disc_thresh, 2);
  98 +               /* Disconnect threshold adjustment */
  99 +               sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
 100 +                                   data->cfg->disc_thresh, 2);
 101 +       }
 102
 103         sun4i_usb_phy_passby(phy, 1);
 104
 105 @@ -726,6 +741,13 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 106         .dedicated_clocks = true,
 107  };
 108
 109 +static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 110 +       .num_phys = 4,
 111 +       .type = sun8i_h3_phy,
 112 +       .disc_thresh = 3,
 113 +       .dedicated_clocks = true,
 114 +};
 115 +
 116  static const struct of_device_id sun4i_usb_phy_of_match[] = {
 117         { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
 118         { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
 119 @@ -733,6 +755,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 120         { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
 121         { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
 122         { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
 123 +       { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
 124         { },
 125  };
 126  MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);