6910834297fc17ad74e84eae93476415859b02f1
[openwrt/openwrt.git] / target / linux / sunxi / patches-4.4 / 133-dt-sun8i-add-usbphy-usbhost-ctrl-nodes.patch
1 From 5971a2f283d21eab36d7de24d35301f081f83418 Mon Sep 17 00:00:00 2001
2 From: Reinder de Haan <patchesrdh@mveas.com>
3 Date: Tue, 3 Nov 2015 15:14:20 +0100
4 Subject: [PATCH] ARM: dts: sun8i: Add usbphy and usb host controller nodes
5
6 Add nodes describing the H3's usbphy and usb host controller nodes.
7
8 Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
9 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
10 ---
11 arch/arm/boot/dts/sun8i-h3.dtsi | 101 ++++++++++++++++++++++++++++++++++++++++
12 1 file changed, 101 insertions(+)
13
14 diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
15 index cbab947..1169f515 100644
16 --- a/arch/arm/boot/dts/sun8i-h3.dtsi
17 +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
18 @@ -362,6 +362,107 @@
19 #size-cells = <0>;
20 };
21
22 + usbphy: phy@01c19400 {
23 + compatible = "allwinner,sun8i-h3-usb-phy";
24 + reg = <0x01c19400 0x2c>,
25 + <0x01c1a800 0x4>,
26 + <0x01c1b800 0x4>,
27 + <0x01c1c800 0x4>,
28 + <0x01c1d800 0x4>;
29 + reg-names = "phy_ctrl",
30 + "pmu0",
31 + "pmu1",
32 + "pmu2",
33 + "pmu3";
34 + clocks = <&usb_clk 8>,
35 + <&usb_clk 9>,
36 + <&usb_clk 10>,
37 + <&usb_clk 11>;
38 + clock-names = "usb0_phy",
39 + "usb1_phy",
40 + "usb2_phy",
41 + "usb3_phy";
42 + resets = <&usb_clk 0>,
43 + <&usb_clk 1>,
44 + <&usb_clk 2>,
45 + <&usb_clk 3>;
46 + reset-names = "usb0_reset",
47 + "usb1_reset",
48 + "usb2_reset",
49 + "usb3_reset";
50 + status = "disabled";
51 + #phy-cells = <1>;
52 + };
53 +
54 + ehci1: usb@01c1b000 {
55 + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
56 + reg = <0x01c1b000 0x100>;
57 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
58 + clocks = <&bus_gates 25>, <&bus_gates 29>;
59 + resets = <&ahb_rst 25>, <&ahb_rst 29>;
60 + phys = <&usbphy 1>;
61 + phy-names = "usb";
62 + status = "disabled";
63 + };
64 +
65 + ohci1: usb@01c1b400 {
66 + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
67 + reg = <0x01c1b400 0x100>;
68 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
69 + clocks = <&bus_gates 29>, <&bus_gates 25>,
70 + <&usb_clk 17>;
71 + resets = <&ahb_rst 29>, <&ahb_rst 25>;
72 + phys = <&usbphy 1>;
73 + phy-names = "usb";
74 + status = "disabled";
75 + };
76 +
77 + ehci2: usb@01c1c000 {
78 + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
79 + reg = <0x01c1c000 0x100>;
80 + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
81 + clocks = <&bus_gates 26>, <&bus_gates 30>;
82 + resets = <&ahb_rst 26>, <&ahb_rst 30>;
83 + phys = <&usbphy 2>;
84 + phy-names = "usb";
85 + status = "disabled";
86 + };
87 +
88 + ohci2: usb@01c1c400 {
89 + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
90 + reg = <0x01c1c400 0x100>;
91 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
92 + clocks = <&bus_gates 30>, <&bus_gates 26>,
93 + <&usb_clk 18>;
94 + resets = <&ahb_rst 30>, <&ahb_rst 26>;
95 + phys = <&usbphy 2>;
96 + phy-names = "usb";
97 + status = "disabled";
98 + };
99 +
100 + ehci3: usb@01c1d000 {
101 + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
102 + reg = <0x01c1d000 0x100>;
103 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
104 + clocks = <&bus_gates 27>, <&bus_gates 31>;
105 + resets = <&ahb_rst 27>, <&ahb_rst 31>;
106 + phys = <&usbphy 3>;
107 + phy-names = "usb";
108 + status = "disabled";
109 + };
110 +
111 + ohci3: usb@01c1d400 {
112 + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
113 + reg = <0x01c1d400 0x100>;
114 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
115 + clocks = <&bus_gates 31>, <&bus_gates 27>,
116 + <&usb_clk 19>;
117 + resets = <&ahb_rst 31>, <&ahb_rst 27>;
118 + phys = <&usbphy 3>;
119 + phy-names = "usb";
120 + status = "disabled";
121 + };
122 +
123 pio: pinctrl@01c20800 {
124 compatible = "allwinner,sun8i-h3-pinctrl";
125 reg = <0x01c20800 0x400>;