target/linux/sunxi/patches-4.9/0019-arm64-allwinner-a64-Add-MMC-nodes.patch

   1 From f3dff3478a8a7b09f9a92023955a151584658893 Mon Sep 17 00:00:00 2001
   2 From: Andre Przywara <andre.przywara@arm.com>
   3 Date: Thu, 6 Oct 2016 02:25:22 +0100
   4 Subject: arm64: allwinner: a64: Add MMC nodes
   5
   6 The A64 has 3 MMC controllers, one of them being especially targeted to
   7 eMMC. Among other things, it has a data strobe signal and a 8 bits data
   8 width.
   9
  10 The two other are more usual controllers that will have a 4 bits width at
  11 most and no data strobe signal, which limits it to more usual SD or MMC
  12 peripherals.
  13
  14 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  15 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  16 Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
  17 Acked-by: Chen-Yu Tsai <wens@csie.org>
  18 ---
  19  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 39 +++++++++++++++++++++++++++
  20  1 file changed, 39 insertions(+)
  21
  22 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  23 +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  24 @@ -121,6 +121,45 @@
  25                 #size-cells = <1>;
  26                 ranges;
  27
  28 +               mmc0: mmc@1c0f000 {
  29 +                       compatible = "allwinner,sun50i-a64-mmc";
  30 +                       reg = <0x01c0f000 0x1000>;
  31 +                       clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
  32 +                       clock-names = "ahb", "mmc";
  33 +                       resets = <&ccu RST_BUS_MMC0>;
  34 +                       reset-names = "ahb";
  35 +                       interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  36 +                       status = "disabled";
  37 +                       #address-cells = <1>;
  38 +                       #size-cells = <0>;
  39 +               };
  40 +
  41 +               mmc1: mmc@1c10000 {
  42 +                       compatible = "allwinner,sun50i-a64-mmc";
  43 +                       reg = <0x01c10000 0x1000>;
  44 +                       clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
  45 +                       clock-names = "ahb", "mmc";
  46 +                       resets = <&ccu RST_BUS_MMC1>;
  47 +                       reset-names = "ahb";
  48 +                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  49 +                       status = "disabled";
  50 +                       #address-cells = <1>;
  51 +                       #size-cells = <0>;
  52 +               };
  53 +
  54 +               mmc2: mmc@1c11000 {
  55 +                       compatible = "allwinner,sun50i-a64-emmc";
  56 +                       reg = <0x01c11000 0x1000>;
  57 +                       clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
  58 +                       clock-names = "ahb", "mmc";
  59 +                       resets = <&ccu RST_BUS_MMC2>;
  60 +                       reset-names = "ahb";
  61 +                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  62 +                       status = "disabled";
  63 +                       #address-cells = <1>;
  64 +                       #size-cells = <0>;
  65 +               };
  66 +
  67                 usb_otg: usb@01c19000 {
  68                         compatible = "allwinner,sun8i-a33-musb";
  69                         reg = <0x01c19000 0x0400>;