0d7803775e4a323f4164374e8cf6ede9a89c2e96
[openwrt/openwrt.git] / target / linux / sunxi / patches-4.9 / 0026-arm64-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch
1 From 0d98479738b950e30bb4f782d60099d44076ad67 Mon Sep 17 00:00:00 2001
2 From: Icenowy Zheng <icenowy@aosc.io>
3 Date: Wed, 5 Apr 2017 22:30:34 +0800
4 Subject: arm64: allwinner: a64: add pmu0 regs for USB PHY
5
6 The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
7 controller pair that can be connected to the PHY0.
8
9 Add the MMIO region for PHY node.
10
11 Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
12 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
13 ---
14 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
15 1 file changed, 2 insertions(+)
16
17 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
18 +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
19 @@ -184,8 +184,10 @@
20 usbphy: phy@01c19400 {
21 compatible = "allwinner,sun50i-a64-usb-phy";
22 reg = <0x01c19400 0x14>,
23 + <0x01c1a800 0x4>,
24 <0x01c1b800 0x4>;
25 reg-names = "phy_ctrl",
26 + "pmu0",
27 "pmu1";
28 clocks = <&ccu CLK_USB_PHY0>,
29 <&ccu CLK_USB_PHY1>;