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Add 2.6.34 patches
[openwrt/openwrt.git] / target / linux / xburst / patches-2.6.34 / 056-udc.patch
1 From 9b62834f0e2aba2111ba22e734982f7c71293355 Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Sat, 24 Apr 2010 12:18:46 +0200
4 Subject: [PATCH] Add jz4740 udc driver
5
6 ---
7 drivers/usb/gadget/Kconfig | 14 +
8 drivers/usb/gadget/Makefile | 1 +
9 drivers/usb/gadget/gadget_chips.h | 9 +
10 drivers/usb/gadget/jz4740_udc.c | 2439 +++++++++++++++++++++++++++++++++++++
11 drivers/usb/gadget/jz4740_udc.h | 99 ++
12 5 files changed, 2562 insertions(+), 0 deletions(-)
13 create mode 100644 drivers/usb/gadget/jz4740_udc.c
14 create mode 100644 drivers/usb/gadget/jz4740_udc.h
15
16 diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
17 index 11a3e0f..a33d0c8 100644
18 --- a/drivers/usb/gadget/Kconfig
19 +++ b/drivers/usb/gadget/Kconfig
20 @@ -121,11 +121,25 @@ choice
21 #
22 # Integrated controllers
23 #
24 +config USB_GADGET_JZ4740
25 + boolean "JZ4740 UDC"
26 + depends on SOC_JZ4740
27 + select USB_GADGET_SELECTED
28 + select USB_GADGET_DUALSPEED
29 + help
30 + Select this to support the Ingenic JZ4740 processor
31 + high speed USB device controller.
32 +
33 +config USB_JZ4740
34 + tristate
35 + depends on USB_GADGET_JZ4740
36 + default USB_GADGET
37
38 config USB_GADGET_AT91
39 boolean "Atmel AT91 USB Device Port"
40 depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9 && !ARCH_AT91SAM9G45
41 select USB_GADGET_SELECTED
42 +
43 help
44 Many Atmel AT91 processors (such as the AT91RM2000) have a
45 full speed USB Device Port with support for five configurable
46 diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
47 index 43b51da..8c6ee6b 100644
48 --- a/drivers/usb/gadget/Makefile
49 +++ b/drivers/usb/gadget/Makefile
50 @@ -28,6 +28,7 @@ obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
51 obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o
52 obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
53 obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
54 +obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
55
56 #
57 # USB gadget drivers
58 diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
59 index e511fec..b2ec5fb 100644
60 --- a/drivers/usb/gadget/gadget_chips.h
61 +++ b/drivers/usb/gadget/gadget_chips.h
62 @@ -15,6 +15,12 @@
63 #ifndef __GADGET_CHIPS_H
64 #define __GADGET_CHIPS_H
65
66 +#ifdef CONFIG_USB_GADGET_JZ4740
67 +#define gadget_is_jz4740(g) !strcmp("ingenic_hsusb", (g)->name)
68 +#else
69 +#define gadget_is_jz4740(g) 0
70 +#endif
71 +
72 #ifdef CONFIG_USB_GADGET_NET2280
73 #define gadget_is_net2280(g) !strcmp("net2280", (g)->name)
74 #else
75 @@ -200,6 +206,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
76 return 0x25;
77 else if (gadget_is_s3c_hsotg(gadget))
78 return 0x26;
79 + else if (gadget_is_jz4740(gadget))
80 + return 0x27;
81 +
82 return -ENOENT;
83 }
84
85 diff --git a/drivers/usb/gadget/jz4740_udc.c b/drivers/usb/gadget/jz4740_udc.c
86 new file mode 100644
87 index 0000000..bea1a37
88 --- /dev/null
89 +++ b/drivers/usb/gadget/jz4740_udc.c
90 @@ -0,0 +1,2439 @@
91 +/*
92 + * linux/drivers/usb/gadget/jz4740_udc.c
93 + *
94 + * Ingenic JZ4740 on-chip high speed USB device controller
95 + *
96 + * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
97 + * Author: <jlwei@ingenic.cn>
98 + *
99 + * This program is free software; you can redistribute it and/or modify
100 + * it under the terms of the GNU General Public License as published by
101 + * the Free Software Foundation; either version 2 of the License, or
102 + * (at your option) any later version.
103 + */
104 +
105 +/*
106 + * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
107 + *
108 + * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
109 + * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
110 + */
111 +
112 +#include <linux/kernel.h>
113 +#include <linux/module.h>
114 +#include <linux/platform_device.h>
115 +#include <linux/delay.h>
116 +#include <linux/ioport.h>
117 +#include <linux/slab.h>
118 +#include <linux/errno.h>
119 +#include <linux/init.h>
120 +#include <linux/list.h>
121 +#include <linux/interrupt.h>
122 +#include <linux/proc_fs.h>
123 +#include <linux/usb.h>
124 +#include <linux/usb/gadget.h>
125 +#include <linux/clk.h>
126 +
127 +#include <asm/byteorder.h>
128 +#include <asm/io.h>
129 +#include <asm/irq.h>
130 +#include <asm/system.h>
131 +#include <asm/mach-jz4740/clock.h>
132 +
133 +#include "jz4740_udc.h"
134 +
135 +#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
136 +#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
137 +#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
138 +#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
139 +#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
140 +#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
141 +#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
142 +#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
143 +#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
144 +#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
145 +#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
146 +
147 +#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
148 +#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
149 +#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
150 +#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
151 +#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
152 +#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
153 +#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
154 +#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
155 +
156 +#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
157 +
158 +#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
159 +#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
160 +
161 +#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
162 +#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
163 +#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
164 +#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
165 +#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
166 +#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
167 +#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
168 +
169 +/* Power register bit masks */
170 +#define USB_POWER_SUSPENDM 0x01
171 +#define USB_POWER_RESUME 0x04
172 +#define USB_POWER_HSMODE 0x10
173 +#define USB_POWER_HSENAB 0x20
174 +#define USB_POWER_SOFTCONN 0x40
175 +
176 +/* Interrupt register bit masks */
177 +#define USB_INTR_SUSPEND 0x01
178 +#define USB_INTR_RESUME 0x02
179 +#define USB_INTR_RESET 0x04
180 +
181 +#define USB_INTR_EP0 0x0001
182 +#define USB_INTR_INEP1 0x0002
183 +#define USB_INTR_INEP2 0x0004
184 +#define USB_INTR_OUTEP1 0x0002
185 +
186 +/* CSR0 bit masks */
187 +#define USB_CSR0_OUTPKTRDY 0x01
188 +#define USB_CSR0_INPKTRDY 0x02
189 +#define USB_CSR0_SENTSTALL 0x04
190 +#define USB_CSR0_DATAEND 0x08
191 +#define USB_CSR0_SETUPEND 0x10
192 +#define USB_CSR0_SENDSTALL 0x20
193 +#define USB_CSR0_SVDOUTPKTRDY 0x40
194 +#define USB_CSR0_SVDSETUPEND 0x80
195 +
196 +/* Endpoint CSR register bits */
197 +#define USB_INCSRH_AUTOSET 0x80
198 +#define USB_INCSRH_ISO 0x40
199 +#define USB_INCSRH_MODE 0x20
200 +#define USB_INCSRH_DMAREQENAB 0x10
201 +#define USB_INCSRH_DMAREQMODE 0x04
202 +#define USB_INCSR_CDT 0x40
203 +#define USB_INCSR_SENTSTALL 0x20
204 +#define USB_INCSR_SENDSTALL 0x10
205 +#define USB_INCSR_FF 0x08
206 +#define USB_INCSR_UNDERRUN 0x04
207 +#define USB_INCSR_FFNOTEMPT 0x02
208 +#define USB_INCSR_INPKTRDY 0x01
209 +#define USB_OUTCSRH_AUTOCLR 0x80
210 +#define USB_OUTCSRH_ISO 0x40
211 +#define USB_OUTCSRH_DMAREQENAB 0x20
212 +#define USB_OUTCSRH_DNYT 0x10
213 +#define USB_OUTCSRH_DMAREQMODE 0x08
214 +#define USB_OUTCSR_CDT 0x80
215 +#define USB_OUTCSR_SENTSTALL 0x40
216 +#define USB_OUTCSR_SENDSTALL 0x20
217 +#define USB_OUTCSR_FF 0x10
218 +#define USB_OUTCSR_DATAERR 0x08
219 +#define USB_OUTCSR_OVERRUN 0x04
220 +#define USB_OUTCSR_FFFULL 0x02
221 +#define USB_OUTCSR_OUTPKTRDY 0x01
222 +
223 +/* Testmode register bits */
224 +#define USB_TEST_SE0NAK 0x01
225 +#define USB_TEST_J 0x02
226 +#define USB_TEST_K 0x04
227 +#define USB_TEST_PACKET 0x08
228 +
229 +/* DMA control bits */
230 +#define USB_CNTL_ENA 0x01
231 +#define USB_CNTL_DIR_IN 0x02
232 +#define USB_CNTL_MODE_1 0x04
233 +#define USB_CNTL_INTR_EN 0x08
234 +#define USB_CNTL_EP(n) ((n) << 4)
235 +#define USB_CNTL_BURST_0 (0 << 9)
236 +#define USB_CNTL_BURST_4 (1 << 9)
237 +#define USB_CNTL_BURST_8 (2 << 9)
238 +#define USB_CNTL_BURST_16 (3 << 9)
239 +
240 +
241 +#ifndef DEBUG
242 +# define DEBUG(fmt,args...) do {} while(0)
243 +#endif
244 +#ifndef DEBUG_EP0
245 +# define NO_STATES
246 +# define DEBUG_EP0(fmt,args...) do {} while(0)
247 +#endif
248 +#ifndef DEBUG_SETUP
249 +# define DEBUG_SETUP(fmt,args...) do {} while(0)
250 +#endif
251 +
252 +static unsigned int use_dma = 0; /* 1: use DMA, 0: use PIO */
253 +
254 +module_param(use_dma, int, 0);
255 +MODULE_PARM_DESC(use_dma, "DMA mode enable flag");
256 +
257 +struct jz4740_udc *the_controller;
258 +
259 +/*
260 + * Local declarations.
261 + */
262 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
263 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
264 +
265 +static void done(struct jz4740_ep *ep, struct jz4740_request *req,
266 + int status);
267 +static void pio_irq_enable(struct jz4740_ep *ep);
268 +static void pio_irq_disable(struct jz4740_ep *ep);
269 +static void stop_activity(struct jz4740_udc *dev,
270 + struct usb_gadget_driver *driver);
271 +static void nuke(struct jz4740_ep *ep, int status);
272 +static void flush(struct jz4740_ep *ep);
273 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
274 +
275 +/*-------------------------------------------------------------------------*/
276 +
277 +/* inline functions of register read/write/set/clear */
278 +
279 +static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
280 +{
281 + return readb(udc->base + reg);
282 +}
283 +
284 +static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
285 +{
286 + return readw(udc->base + reg);
287 +}
288 +
289 +static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
290 +{
291 + return readl(udc->base + reg);
292 +}
293 +
294 +static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
295 +{
296 + writeb(val, udc->base + reg);
297 +}
298 +
299 +static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
300 +{
301 + writew(val, udc->base + reg);
302 +}
303 +
304 +static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
305 +{
306 + writel(val, udc->base + reg);
307 +}
308 +
309 +static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
310 +{
311 + usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
312 +}
313 +
314 +static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask)
315 +{
316 + usb_writew(udc, reg, usb_readw(udc, reg) | mask);
317 +}
318 +
319 +static inline void usb_setl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
320 +{
321 + usb_writel(udc, reg, usb_readl(udc, reg) | mask);
322 +}
323 +
324 +static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
325 +{
326 + usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
327 +}
328 +
329 +static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
330 +{
331 + usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
332 +}
333 +
334 +static inline void usb_clearl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
335 +{
336 + usb_writel(udc, reg, usb_readl(udc, reg) & ~mask);
337 +}
338 +
339 +/*-------------------------------------------------------------------------*/
340 +
341 +static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
342 +{
343 + usb_writeb(udc, JZ_REG_UDC_INDEX, index);
344 +}
345 +
346 +static inline void jz_udc_select_ep(struct jz4740_ep *ep)
347 +{
348 + jz_udc_set_index(ep->dev, ep_index(ep));
349 +}
350 +
351 +static inline int write_packet(struct jz4740_ep *ep,
352 + struct jz4740_request *req, int max)
353 +{
354 + uint8_t *buf;
355 + int length, nlong, nbyte;
356 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
357 +
358 + buf = req->req.buf + req->req.actual;
359 + prefetch(buf);
360 +
361 + length = req->req.length - req->req.actual;
362 + length = min(length, max);
363 + req->req.actual += length;
364 +
365 + DEBUG("Write %d (max %d), fifo %x\n", length, max, ep->fifo);
366 +
367 + nlong = length >> 2;
368 + nbyte = length & 0x3;
369 + while (nlong--) {
370 + usb_writel(ep->dev, ep->fifo, *((uint32_t *)buf));
371 + buf += 4;
372 + }
373 + while (nbyte--) {
374 + usb_writeb(ep->dev, ep->fifo, *buf++);
375 + }
376 +
377 + return length;
378 +}
379 +
380 +static inline int read_packet(struct jz4740_ep *ep,
381 + struct jz4740_request *req, int count)
382 +{
383 + uint8_t *buf;
384 + int length, nlong, nbyte;
385 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
386 +
387 + buf = req->req.buf + req->req.actual;
388 + prefetchw(buf);
389 +
390 + length = req->req.length - req->req.actual;
391 + length = min(length, count);
392 + req->req.actual += length;
393 +
394 + DEBUG("Read %d, fifo %x\n", length, ep->fifo);
395 +
396 + nlong = length >> 2;
397 + nbyte = length & 0x3;
398 + while (nlong--) {
399 + *((uint32_t *)buf) = usb_readl(ep->dev, ep->fifo);
400 + buf += 4;
401 + }
402 + while (nbyte--) {
403 + *buf++ = usb_readb(ep->dev, ep->fifo);
404 + }
405 +
406 + return length;
407 +}
408 +
409 +/*-------------------------------------------------------------------------*/
410 +
411 +/*
412 + * udc_disable - disable USB device controller
413 + */
414 +static void udc_disable(struct jz4740_udc *dev)
415 +{
416 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
417 +
418 + udc_set_address(dev, 0);
419 +
420 + /* Disable interrupts */
421 + usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
422 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
423 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
424 +
425 + /* Disable DMA */
426 + usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
427 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
428 +
429 + /* Disconnect from usb */
430 + usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
431 +
432 + /* Disable the USB PHY */
433 + clk_disable(dev->clk);
434 +
435 + dev->ep0state = WAIT_FOR_SETUP;
436 + dev->gadget.speed = USB_SPEED_UNKNOWN;
437 +
438 + return;
439 +}
440 +
441 +/*
442 + * udc_reinit - initialize software state
443 + */
444 +static void udc_reinit(struct jz4740_udc *dev)
445 +{
446 + int i;
447 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
448 +
449 + /* device/ep0 records init */
450 + INIT_LIST_HEAD(&dev->gadget.ep_list);
451 + INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
452 + dev->ep0state = WAIT_FOR_SETUP;
453 +
454 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
455 + struct jz4740_ep *ep = &dev->ep[i];
456 +
457 + if (i != 0)
458 + list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
459 +
460 + INIT_LIST_HEAD(&ep->queue);
461 + ep->desc = 0;
462 + ep->stopped = 0;
463 + ep->pio_irqs = 0;
464 + }
465 +}
466 +
467 +/* until it's enabled, this UDC should be completely invisible
468 + * to any USB host.
469 + */
470 +static void udc_enable(struct jz4740_udc *dev)
471 +{
472 + int i;
473 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
474 +
475 + /* UDC state is incorrect - Added by River */
476 + if (dev->state != UDC_STATE_ENABLE) {
477 + return;
478 + }
479 +
480 + dev->gadget.speed = USB_SPEED_UNKNOWN;
481 +
482 + /* Flush FIFO for each */
483 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
484 + struct jz4740_ep *ep = &dev->ep[i];
485 +
486 + jz_udc_set_index(dev, ep_index(ep));
487 + flush(ep);
488 + }
489 +
490 + /* Set this bit to allow the UDC entering low-power mode when
491 + * there are no actions on the USB bus.
492 + * UDC still works during this bit was set.
493 + */
494 + jz4740_clock_udc_enable_auto_suspend();
495 +
496 + /* Enable the USB PHY */
497 + clk_enable(dev->clk);
498 +
499 + /* Disable interrupts */
500 +/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
501 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
502 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
503 +
504 + /* Enable interrupts */
505 + usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
506 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
507 + /* Don't enable rest of the interrupts */
508 + /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
509 + usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
510 +
511 + /* Enable SUSPEND */
512 + /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
513 +
514 + /* Enable HS Mode */
515 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
516 +
517 + /* Let host detect UDC:
518 + * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
519 + * transistor on and pull the USBDP pin HIGH.
520 + */
521 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
522 +
523 + return;
524 +}
525 +
526 +/*-------------------------------------------------------------------------*/
527 +
528 +/* keeping it simple:
529 + * - one bus driver, initted first;
530 + * - one function driver, initted second
531 + */
532 +
533 +/*
534 + * Register entry point for the peripheral controller driver.
535 + */
536 +
537 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
538 +{
539 + struct jz4740_udc *dev = the_controller;
540 + int retval;
541 +
542 + if (!driver || !driver->bind) {
543 + return -EINVAL;
544 + }
545 +
546 + if (!dev) {
547 + return -ENODEV;
548 + }
549 +
550 + if (dev->driver) {
551 + return -EBUSY;
552 + }
553 +
554 + /* hook up the driver */
555 + dev->driver = driver;
556 + dev->gadget.dev.driver = &driver->driver;
557 +
558 + retval = driver->bind(&dev->gadget);
559 + if (retval) {
560 + DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
561 + driver->driver.name, retval);
562 + dev->driver = 0;
563 + return retval;
564 + }
565 +
566 + /* then enable host detection and ep0; and we're ready
567 + * for set_configuration as well as eventual disconnect.
568 + */
569 + udc_enable(dev);
570 +
571 + DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
572 + driver->driver.name);
573 +
574 + return 0;
575 +}
576 +
577 +EXPORT_SYMBOL(usb_gadget_register_driver);
578 +
579 +static void stop_activity(struct jz4740_udc *dev,
580 + struct usb_gadget_driver *driver)
581 +{
582 + int i;
583 +
584 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
585 +
586 + /* don't disconnect drivers more than once */
587 + if (dev->gadget.speed == USB_SPEED_UNKNOWN)
588 + driver = 0;
589 + dev->gadget.speed = USB_SPEED_UNKNOWN;
590 +
591 + /* prevent new request submissions, kill any outstanding requests */
592 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
593 + struct jz4740_ep *ep = &dev->ep[i];
594 +
595 + ep->stopped = 1;
596 +
597 + jz_udc_set_index(dev, ep_index(ep));
598 + nuke(ep, -ESHUTDOWN);
599 + }
600 +
601 + /* report disconnect; the driver is already quiesced */
602 + if (driver) {
603 + spin_unlock(&dev->lock);
604 + driver->disconnect(&dev->gadget);
605 + spin_lock(&dev->lock);
606 + }
607 +
608 + /* re-init driver-visible data structures */
609 + udc_reinit(dev);
610 +}
611 +
612 +
613 +/*
614 + * Unregister entry point for the peripheral controller driver.
615 + */
616 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
617 +{
618 + struct jz4740_udc *dev = the_controller;
619 + unsigned long flags;
620 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
621 +
622 + if (!dev)
623 + return -ENODEV;
624 + if (!driver || driver != dev->driver)
625 + return -EINVAL;
626 + if (!driver->unbind)
627 + return -EBUSY;
628 +
629 + spin_lock_irqsave(&dev->lock, flags);
630 + dev->driver = 0;
631 + stop_activity(dev, driver);
632 + spin_unlock_irqrestore(&dev->lock, flags);
633 +
634 + driver->unbind(&dev->gadget);
635 +
636 + udc_disable(dev);
637 +
638 + DEBUG("unregistered driver '%s'\n", driver->driver.name);
639 +
640 + return 0;
641 +}
642 +
643 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
644 +
645 +/*-------------------------------------------------------------------------*/
646 +
647 +/*
648 + * Starting DMA using mode 1
649 + */
650 +static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req)
651 +{
652 + struct jz4740_udc *dev = ep->dev;
653 + uint32_t count = req->req.length;
654 + uint32_t physaddr = virt_to_phys((void *)req->req.buf);
655 +
656 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
657 +
658 + jz_udc_select_ep(ep);
659 +
660 + if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */
661 + ep->reg_addr = JZ_REG_UDC_ADDR1;
662 +
663 + dma_cache_wback_inv((unsigned long)req->req.buf, count);
664 +
665 + pio_irq_enable(ep);
666 +
667 + usb_writeb(dev, JZ_REG_UDC_INCSRH,
668 + USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
669 +
670 + usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr);
671 + usb_writel(dev, JZ_REG_UDC_COUNT1, count);
672 + usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 |
673 + USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
674 + }
675 + else { /* Bulk-OUT transfer using DMA channel 2 */
676 + ep->reg_addr = JZ_REG_UDC_ADDR2;
677 +
678 + dma_cache_wback_inv((unsigned long)req->req.buf, count);
679 +
680 + pio_irq_enable(ep);
681 +
682 + usb_setb(dev, JZ_REG_UDC_OUTCSRH,
683 + USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
684 +
685 + usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr);
686 + usb_writel(dev, JZ_REG_UDC_COUNT2, count);
687 + usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 |
688 + USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
689 + }
690 +}
691 +
692 +/*-------------------------------------------------------------------------*/
693 +
694 +/** Write request to FIFO (max write == maxp size)
695 + * Return: 0 = still running, 1 = completed, negative = errno
696 + * NOTE: INDEX register must be set for EP
697 + */
698 +static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
699 +{
700 + struct jz4740_udc *dev = ep->dev;
701 + uint32_t max, csr;
702 + uint32_t physaddr = virt_to_phys((void *)req->req.buf);
703 +
704 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
705 + max = le16_to_cpu(ep->desc->wMaxPacketSize);
706 +
707 + if (use_dma) {
708 + uint32_t dma_count;
709 +
710 + /* DMA interrupt generated due to the last packet loaded into the FIFO */
711 +
712 + dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
713 + req->req.actual += dma_count;
714 +
715 + if (dma_count % max) {
716 + /* If the last packet is less than MAXP, set INPKTRDY manually */
717 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
718 + }
719 +
720 + done(ep, req, 0);
721 + if (list_empty(&ep->queue)) {
722 + pio_irq_disable(ep);
723 + return 1;
724 + }
725 + else {
726 + /* advance the request queue */
727 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
728 + kick_dma(ep, req);
729 + return 0;
730 + }
731 + }
732 +
733 + /*
734 + * PIO mode handling starts here ...
735 + */
736 +
737 + csr = usb_readb(dev, ep->csr);
738 +
739 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
740 + unsigned count;
741 + int is_last, is_short;
742 +
743 + count = write_packet(ep, req, max);
744 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
745 +
746 + /* last packet is usually short (or a zlp) */
747 + if (unlikely(count != max))
748 + is_last = is_short = 1;
749 + else {
750 + if (likely(req->req.length != req->req.actual)
751 + || req->req.zero)
752 + is_last = 0;
753 + else
754 + is_last = 1;
755 + /* interrupt/iso maxpacket may not fill the fifo */
756 + is_short = unlikely(max < ep_maxpacket(ep));
757 + }
758 +
759 + DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
760 + ep->ep.name, count,
761 + is_last ? "/L" : "", is_short ? "/S" : "",
762 + req->req.length - req->req.actual, req);
763 +
764 + /* requests complete when all IN data is in the FIFO */
765 + if (is_last) {
766 + done(ep, req, 0);
767 + if (list_empty(&ep->queue)) {
768 + pio_irq_disable(ep);
769 + }
770 + return 1;
771 + }
772 + } else {
773 + DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
774 + }
775 +
776 + return 0;
777 +}
778 +
779 +/** Read to request from FIFO (max read == bytes in fifo)
780 + * Return: 0 = still running, 1 = completed, negative = errno
781 + * NOTE: INDEX register must be set for EP
782 + */
783 +static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
784 +{
785 + struct jz4740_udc *dev = ep->dev;
786 + uint32_t csr;
787 + unsigned count, is_short;
788 + uint32_t physaddr = virt_to_phys((void *)req->req.buf);
789 +
790 + if (use_dma) {
791 + uint32_t dma_count;
792 +
793 + /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */
794 +
795 + dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
796 + req->req.actual += dma_count;
797 +
798 + /* Disable interrupt and DMA */
799 + pio_irq_disable(ep);
800 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
801 +
802 + /* Read all bytes from this packet */
803 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
804 + count = read_packet(ep, req, count);
805 +
806 + if (count) {
807 + /* If the last packet is greater than zero, clear OUTPKTRDY manually */
808 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
809 + }
810 + done(ep, req, 0);
811 +
812 + if (!list_empty(&ep->queue)) {
813 + /* advance the request queue */
814 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
815 + kick_dma(ep, req);
816 + }
817 +
818 + return 1;
819 + }
820 +
821 + /*
822 + * PIO mode handling starts here ...
823 + */
824 +
825 + /* make sure there's a packet in the FIFO. */
826 + csr = usb_readb(dev, ep->csr);
827 + if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
828 + DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
829 + return -EINVAL;
830 + }
831 +
832 + /* read all bytes from this packet */
833 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
834 +
835 + is_short = (count < ep->ep.maxpacket);
836 +
837 + count = read_packet(ep, req, count);
838 +
839 + DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
840 + ep->ep.name, csr, count,
841 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
842 +
843 + /* Clear OutPktRdy */
844 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
845 +
846 + /* completion */
847 + if (is_short || req->req.actual == req->req.length) {
848 + done(ep, req, 0);
849 +
850 + if (list_empty(&ep->queue))
851 + pio_irq_disable(ep);
852 + return 1;
853 + }
854 +
855 + /* finished that packet. the next one may be waiting... */
856 + return 0;
857 +}
858 +
859 +/*
860 + * done - retire a request; caller blocked irqs
861 + * INDEX register is preserved to keep same
862 + */
863 +static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
864 +{
865 + unsigned int stopped = ep->stopped;
866 + unsigned long flags;
867 + uint32_t index;
868 +
869 + DEBUG("%s, %p\n", __FUNCTION__, ep);
870 + list_del_init(&req->queue);
871 +
872 + if (likely(req->req.status == -EINPROGRESS))
873 + req->req.status = status;
874 + else
875 + status = req->req.status;
876 +
877 + if (status && status != -ESHUTDOWN)
878 + DEBUG("complete %s req %p stat %d len %u/%u\n",
879 + ep->ep.name, &req->req, status,
880 + req->req.actual, req->req.length);
881 +
882 + /* don't modify queue heads during completion callback */
883 + ep->stopped = 1;
884 + /* Read current index (completion may modify it) */
885 + spin_lock_irqsave(&ep->dev->lock, flags);
886 + index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
887 +
888 + req->req.complete(&ep->ep, &req->req);
889 +
890 + /* Restore index */
891 + jz_udc_set_index(ep->dev, index);
892 + spin_unlock_irqrestore(&ep->dev->lock, flags);
893 + ep->stopped = stopped;
894 +}
895 +
896 +/** Enable EP interrupt */
897 +static void pio_irq_enable(struct jz4740_ep *ep)
898 +{
899 + uint8_t index = ep_index(ep);
900 + struct jz4740_udc *dev = ep->dev;
901 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
902 +
903 + if (ep_is_in(ep)) {
904 + switch (index) {
905 + case 1:
906 + case 2:
907 + usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index));
908 + dev->in_mask |= BIT(index);
909 + break;
910 + default:
911 + DEBUG("Unknown endpoint: %d\n", index);
912 + break;
913 + }
914 + }
915 + else {
916 + switch (index) {
917 + case 1:
918 + usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index));
919 + dev->out_mask |= BIT(index);
920 + break;
921 + default:
922 + DEBUG("Unknown endpoint: %d\n", index);
923 + break;
924 + }
925 + }
926 +}
927 +
928 +/** Disable EP interrupt */
929 +static void pio_irq_disable(struct jz4740_ep *ep)
930 +{
931 + uint8_t index = ep_index(ep);
932 + struct jz4740_udc *dev = ep->dev;
933 +
934 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
935 +
936 + if (ep_is_in(ep)) {
937 + switch (ep_index(ep)) {
938 + case 1:
939 + case 2:
940 + usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index));
941 + dev->in_mask &= ~BIT(index);
942 + break;
943 + default:
944 + DEBUG("Unknown endpoint: %d\n", index);
945 + break;
946 + }
947 + }
948 + else {
949 + switch (ep_index(ep)) {
950 + case 1:
951 + usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index));
952 + dev->out_mask &= ~BIT(index);
953 + break;
954 + default:
955 + DEBUG("Unknown endpoint: %d\n", index);
956 + break;
957 + }
958 + }
959 +}
960 +
961 +/*
962 + * nuke - dequeue ALL requests
963 + */
964 +static void nuke(struct jz4740_ep *ep, int status)
965 +{
966 + struct jz4740_request *req;
967 +
968 + DEBUG("%s, %p\n", __FUNCTION__, ep);
969 +
970 + /* Flush FIFO */
971 + flush(ep);
972 +
973 + /* called with irqs blocked */
974 + while (!list_empty(&ep->queue)) {
975 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
976 + done(ep, req, status);
977 + }
978 +
979 + /* Disable IRQ if EP is enabled (has descriptor) */
980 + if (ep->desc)
981 + pio_irq_disable(ep);
982 +}
983 +
984 +/** Flush EP FIFO
985 + * NOTE: INDEX register must be set before this call
986 + */
987 +static void flush(struct jz4740_ep *ep)
988 +{
989 + DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
990 +
991 + switch (ep->type) {
992 + case ep_bulk_in:
993 + case ep_interrupt:
994 + usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
995 + break;
996 + case ep_bulk_out:
997 + usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
998 + break;
999 + case ep_control:
1000 + break;
1001 + }
1002 +}
1003 +
1004 +/**
1005 + * jz4740_in_epn - handle IN interrupt
1006 + */
1007 +static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
1008 +{
1009 + uint32_t csr;
1010 + struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
1011 + struct jz4740_request *req;
1012 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1013 +
1014 + jz_udc_set_index(dev, ep_index(ep));
1015 +
1016 + csr = usb_readb(dev, ep->csr);
1017 + DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
1018 +
1019 + if (csr & USB_INCSR_SENTSTALL) {
1020 + DEBUG("USB_INCSR_SENTSTALL\n");
1021 + usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
1022 + return;
1023 + }
1024 +
1025 + if (!ep->desc) {
1026 + DEBUG("%s: NO EP DESC\n", __FUNCTION__);
1027 + return;
1028 + }
1029 +
1030 + if (list_empty(&ep->queue))
1031 + req = 0;
1032 + else
1033 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1034 +
1035 + DEBUG("req: %p\n", req);
1036 +
1037 + if (!req)
1038 + return;
1039 +
1040 + write_fifo(ep, req);
1041 +}
1042 +
1043 +/*
1044 + * Bulk OUT (recv)
1045 + */
1046 +static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
1047 +{
1048 + struct jz4740_ep *ep = &dev->ep[ep_idx];
1049 + struct jz4740_request *req;
1050 +
1051 + DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
1052 +
1053 + jz_udc_set_index(dev, ep_index(ep));
1054 + if (ep->desc) {
1055 + uint32_t csr;
1056 +
1057 + if (use_dma) {
1058 + /* DMA starts here ... */
1059 + if (list_empty(&ep->queue))
1060 + req = 0;
1061 + else
1062 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1063 +
1064 + if (req)
1065 + read_fifo(ep, req);
1066 + return;
1067 + }
1068 +
1069 + /*
1070 + * PIO mode starts here ...
1071 + */
1072 +
1073 + while ((csr = usb_readb(dev, ep->csr)) &
1074 + (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
1075 + DEBUG("%s: %x\n", __FUNCTION__, csr);
1076 +
1077 + if (csr & USB_OUTCSR_SENTSTALL) {
1078 + DEBUG("%s: stall sent, flush fifo\n",
1079 + __FUNCTION__);
1080 + /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
1081 + flush(ep);
1082 + } else if (csr & USB_OUTCSR_OUTPKTRDY) {
1083 + if (list_empty(&ep->queue))
1084 + req = 0;
1085 + else
1086 + req =
1087 + list_entry(ep->queue.next,
1088 + struct jz4740_request,
1089 + queue);
1090 +
1091 + if (!req) {
1092 + DEBUG("%s: NULL REQ %d\n",
1093 + __FUNCTION__, ep_idx);
1094 + break;
1095 + } else {
1096 + read_fifo(ep, req);
1097 + }
1098 + }
1099 + }
1100 + } else {
1101 + /* Throw packet away.. */
1102 + DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
1103 + flush(ep);
1104 + }
1105 +}
1106 +
1107 +/** Halt specific EP
1108 + * Return 0 if success
1109 + * NOTE: Sets INDEX register to EP !
1110 + */
1111 +static int jz4740_set_halt(struct usb_ep *_ep, int value)
1112 +{
1113 + struct jz4740_udc *dev;
1114 + struct jz4740_ep *ep;
1115 + unsigned long flags;
1116 +
1117 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1118 +
1119 + ep = container_of(_ep, struct jz4740_ep, ep);
1120 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1121 + DEBUG("%s, bad ep\n", __FUNCTION__);
1122 + return -EINVAL;
1123 + }
1124 +
1125 + dev = ep->dev;
1126 +
1127 + spin_lock_irqsave(&dev->lock, flags);
1128 +
1129 + jz_udc_select_ep(ep);
1130 +
1131 + DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
1132 +
1133 + if (ep_index(ep) == 0) {
1134 + /* EP0 */
1135 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
1136 + } else if (ep_is_in(ep)) {
1137 + uint32_t csr = usb_readb(dev, ep->csr);
1138 + if (value && ((csr & USB_INCSR_FFNOTEMPT)
1139 + || !list_empty(&ep->queue))) {
1140 + /*
1141 + * Attempts to halt IN endpoints will fail (returning -EAGAIN)
1142 + * if any transfer requests are still queued, or if the controller
1143 + * FIFO still holds bytes that the host hasn\92t collected.
1144 + */
1145 + spin_unlock_irqrestore(&dev->lock, flags);
1146 + DEBUG
1147 + ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
1148 + (csr & USB_INCSR_FFNOTEMPT),
1149 + !list_empty(&ep->queue));
1150 + return -EAGAIN;
1151 + }
1152 + flush(ep);
1153 + if (value) {
1154 + usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
1155 + }
1156 + else {
1157 + usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
1158 + usb_setb(dev, ep->csr, USB_INCSR_CDT);
1159 + }
1160 + } else {
1161 +
1162 + flush(ep);
1163 + if (value) {
1164 + usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1165 + }
1166 + else {
1167 + usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1168 + usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
1169 + }
1170 + }
1171 +
1172 + if (value) {
1173 + ep->stopped = 1;
1174 + } else {
1175 + ep->stopped = 0;
1176 + }
1177 +
1178 + spin_unlock_irqrestore(&dev->lock, flags);
1179 +
1180 + DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
1181 +
1182 + return 0;
1183 +}
1184 +
1185 +
1186 +static int jz4740_ep_enable(struct usb_ep *_ep,
1187 + const struct usb_endpoint_descriptor *desc)
1188 +{
1189 + struct jz4740_ep *ep;
1190 + struct jz4740_udc *dev;
1191 + unsigned long flags;
1192 + uint32_t max, csrh = 0;
1193 +
1194 + DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
1195 +
1196 + if (!_ep || !desc)
1197 + return -EINVAL;
1198 +
1199 + ep = container_of(_ep, struct jz4740_ep, ep);
1200 + if (ep->desc || ep->type == ep_control
1201 + || desc->bDescriptorType != USB_DT_ENDPOINT
1202 + || ep->bEndpointAddress != desc->bEndpointAddress) {
1203 + DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
1204 + return -EINVAL;
1205 + }
1206 +
1207 + /* xfer types must match, except that interrupt ~= bulk */
1208 + if (ep->bmAttributes != desc->bmAttributes
1209 + && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
1210 + && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
1211 + DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
1212 + return -EINVAL;
1213 + }
1214 +
1215 + dev = ep->dev;
1216 + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
1217 + DEBUG("%s, bogus device state\n", __FUNCTION__);
1218 + return -ESHUTDOWN;
1219 + }
1220 +
1221 + max = le16_to_cpu(desc->wMaxPacketSize);
1222 +
1223 + spin_lock_irqsave(&ep->dev->lock, flags);
1224 +
1225 + /* Configure the endpoint */
1226 + jz_udc_set_index(dev, desc->bEndpointAddress & 0x0F);
1227 + if (ep_is_in(ep)) {
1228 + usb_writew(dev, JZ_REG_UDC_INMAXP, max);
1229 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1230 + case USB_ENDPOINT_XFER_BULK:
1231 + case USB_ENDPOINT_XFER_INT:
1232 + csrh &= ~USB_INCSRH_ISO;
1233 + break;
1234 + case USB_ENDPOINT_XFER_ISOC:
1235 + csrh |= USB_INCSRH_ISO;
1236 + break;
1237 + }
1238 + usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1239 + }
1240 + else {
1241 + usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1242 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1243 + case USB_ENDPOINT_XFER_BULK:
1244 + csrh &= ~USB_OUTCSRH_ISO;
1245 + break;
1246 + case USB_ENDPOINT_XFER_INT:
1247 + csrh &= ~USB_OUTCSRH_ISO;
1248 + csrh |= USB_OUTCSRH_DNYT;
1249 + break;
1250 + case USB_ENDPOINT_XFER_ISOC:
1251 + csrh |= USB_OUTCSRH_ISO;
1252 + break;
1253 + }
1254 + usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1255 + }
1256 +
1257 +
1258 + ep->stopped = 0;
1259 + ep->desc = desc;
1260 + ep->pio_irqs = 0;
1261 + ep->ep.maxpacket = max;
1262 +
1263 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1264 +
1265 + /* Reset halt state (does flush) */
1266 + jz4740_set_halt(_ep, 0);
1267 +
1268 + DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1269 +
1270 + return 0;
1271 +}
1272 +
1273 +/** Disable EP
1274 + * NOTE: Sets INDEX register
1275 + */
1276 +static int jz4740_ep_disable(struct usb_ep *_ep)
1277 +{
1278 + struct jz4740_ep *ep;
1279 + unsigned long flags;
1280 +
1281 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1282 +
1283 + ep = container_of(_ep, struct jz4740_ep, ep);
1284 + if (!_ep || !ep->desc) {
1285 + DEBUG("%s, %s not enabled\n", __FUNCTION__,
1286 + _ep ? ep->ep.name : NULL);
1287 + return -EINVAL;
1288 + }
1289 +
1290 + spin_lock_irqsave(&ep->dev->lock, flags);
1291 +
1292 + jz_udc_select_ep(ep);
1293 +
1294 + /* Nuke all pending requests (does flush) */
1295 + nuke(ep, -ESHUTDOWN);
1296 +
1297 + /* Disable ep IRQ */
1298 + pio_irq_disable(ep);
1299 +
1300 + ep->desc = 0;
1301 + ep->stopped = 1;
1302 +
1303 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1304 +
1305 + DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1306 + return 0;
1307 +}
1308 +
1309 +static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1310 +{
1311 + struct jz4740_request *req;
1312 +
1313 + DEBUG("%s, %p\n", __FUNCTION__, ep);
1314 +
1315 + req = kzalloc(sizeof(*req), gfp_flags);
1316 + if (!req)
1317 + return 0;
1318 +
1319 + INIT_LIST_HEAD(&req->queue);
1320 +
1321 + return &req->req;
1322 +}
1323 +
1324 +static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1325 +{
1326 + struct jz4740_request *req;
1327 +
1328 + DEBUG("%s, %p\n", __FUNCTION__, ep);
1329 +
1330 + req = container_of(_req, struct jz4740_request, req);
1331 + WARN_ON(!list_empty(&req->queue));
1332 + kfree(req);
1333 +}
1334 +
1335 +/*--------------------------------------------------------------------*/
1336 +
1337 +/** Queue one request
1338 + * Kickstart transfer if needed
1339 + * NOTE: Sets INDEX register
1340 + */
1341 +static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1342 + gfp_t gfp_flags)
1343 +{
1344 + struct jz4740_request *req;
1345 + struct jz4740_ep *ep;
1346 + struct jz4740_udc *dev;
1347 + unsigned long flags;
1348 +
1349 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1350 +
1351 + req = container_of(_req, struct jz4740_request, req);
1352 + if (unlikely
1353 + (!_req || !_req->complete || !_req->buf
1354 + || !list_empty(&req->queue))) {
1355 + DEBUG("%s, bad params\n", __FUNCTION__);
1356 + return -EINVAL;
1357 + }
1358 +
1359 + ep = container_of(_ep, struct jz4740_ep, ep);
1360 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1361 + DEBUG("%s, bad ep\n", __FUNCTION__);
1362 + return -EINVAL;
1363 + }
1364 +
1365 + dev = ep->dev;
1366 + if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1367 + DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1368 + return -ESHUTDOWN;
1369 + }
1370 +
1371 + DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1372 + _req->buf);
1373 +
1374 + spin_lock_irqsave(&dev->lock, flags);
1375 +
1376 + _req->status = -EINPROGRESS;
1377 + _req->actual = 0;
1378 +
1379 + /* kickstart this i/o queue? */
1380 + DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1381 + ep->stopped);
1382 + if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1383 + uint32_t csr;
1384 +
1385 + if (unlikely(ep_index(ep) == 0)) {
1386 + /* EP0 */
1387 + list_add_tail(&req->queue, &ep->queue);
1388 + jz4740_ep0_kick(dev, ep);
1389 + req = 0;
1390 + } else if (use_dma) {
1391 + /* DMA */
1392 + kick_dma(ep, req);
1393 + }
1394 + /* PIO */
1395 + else if (ep_is_in(ep)) {
1396 + /* EP1 & EP2 */
1397 + jz_udc_set_index(dev, ep_index(ep));
1398 + csr = usb_readb(dev, ep->csr);
1399 + pio_irq_enable(ep);
1400 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
1401 + if (write_fifo(ep, req) == 1)
1402 + req = 0;
1403 + }
1404 + } else {
1405 + /* EP1 */
1406 + jz_udc_set_index(dev, ep_index(ep));
1407 + csr = usb_readb(dev, ep->csr);
1408 + pio_irq_enable(ep);
1409 + if (csr & USB_OUTCSR_OUTPKTRDY) {
1410 + if (read_fifo(ep, req) == 1)
1411 + req = 0;
1412 + }
1413 + }
1414 + }
1415 +
1416 + /* pio or dma irq handler advances the queue. */
1417 + if (likely(req != 0))
1418 + list_add_tail(&req->queue, &ep->queue);
1419 +
1420 + spin_unlock_irqrestore(&dev->lock, flags);
1421 +
1422 + return 0;
1423 +}
1424 +
1425 +/* dequeue JUST ONE request */
1426 +static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1427 +{
1428 + struct jz4740_ep *ep;
1429 + struct jz4740_request *req;
1430 + unsigned long flags;
1431 +
1432 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1433 +
1434 + ep = container_of(_ep, struct jz4740_ep, ep);
1435 + if (!_ep || ep->type == ep_control)
1436 + return -EINVAL;
1437 +
1438 + spin_lock_irqsave(&ep->dev->lock, flags);
1439 +
1440 + /* make sure it's actually queued on this endpoint */
1441 + list_for_each_entry(req, &ep->queue, queue) {
1442 + if (&req->req == _req)
1443 + break;
1444 + }
1445 + if (&req->req != _req) {
1446 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1447 + return -EINVAL;
1448 + }
1449 + done(ep, req, -ECONNRESET);
1450 +
1451 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1452 + return 0;
1453 +}
1454 +
1455 +/** Return bytes in EP FIFO
1456 + * NOTE: Sets INDEX register to EP
1457 + */
1458 +static int jz4740_fifo_status(struct usb_ep *_ep)
1459 +{
1460 + uint32_t csr;
1461 + int count = 0;
1462 + struct jz4740_ep *ep;
1463 + unsigned long flags;
1464 +
1465 + ep = container_of(_ep, struct jz4740_ep, ep);
1466 + if (!_ep) {
1467 + DEBUG("%s, bad ep\n", __FUNCTION__);
1468 + return -ENODEV;
1469 + }
1470 +
1471 + DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1472 +
1473 + /* LPD can't report unclaimed bytes from IN fifos */
1474 + if (ep_is_in(ep))
1475 + return -EOPNOTSUPP;
1476 +
1477 + spin_lock_irqsave(&ep->dev->lock, flags);
1478 + jz_udc_set_index(ep->dev, ep_index(ep));
1479 +
1480 + csr = usb_readb(ep->dev, ep->csr);
1481 + if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1482 + csr & 0x1) {
1483 + count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1484 + }
1485 +
1486 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1487 +
1488 + return count;
1489 +}
1490 +
1491 +/** Flush EP FIFO
1492 + * NOTE: Sets INDEX register to EP
1493 + */
1494 +static void jz4740_fifo_flush(struct usb_ep *_ep)
1495 +{
1496 + struct jz4740_ep *ep;
1497 + unsigned long flags;
1498 +
1499 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1500 +
1501 + ep = container_of(_ep, struct jz4740_ep, ep);
1502 + if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1503 + DEBUG("%s, bad ep\n", __FUNCTION__);
1504 + return;
1505 + }
1506 +
1507 + spin_lock_irqsave(&ep->dev->lock, flags);
1508 +
1509 + jz_udc_set_index(ep->dev, ep_index(ep));
1510 + flush(ep);
1511 +
1512 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1513 +}
1514 +
1515 +/****************************************************************/
1516 +/* End Point 0 related functions */
1517 +/****************************************************************/
1518 +
1519 +/* return: 0 = still running, 1 = completed, negative = errno */
1520 +static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1521 +{
1522 + uint32_t max;
1523 + unsigned count;
1524 + int is_last;
1525 +
1526 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1527 + max = ep_maxpacket(ep);
1528 +
1529 + count = write_packet(ep, req, max);
1530 +
1531 + /* last packet is usually short (or a zlp) */
1532 + if (unlikely(count != max))
1533 + is_last = 1;
1534 + else {
1535 + if (likely(req->req.length != req->req.actual) || req->req.zero)
1536 + is_last = 0;
1537 + else
1538 + is_last = 1;
1539 + }
1540 +
1541 + DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1542 + ep->ep.name, count,
1543 + is_last ? "/L" : "", req->req.length - req->req.actual, req);
1544 +
1545 + /* requests complete when all IN data is in the FIFO */
1546 + if (is_last) {
1547 + done(ep, req, 0);
1548 + return 1;
1549 + }
1550 +
1551 + return 0;
1552 +}
1553 +
1554 +static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1555 + unsigned char *cp, int max)
1556 +{
1557 + int bytes;
1558 + int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1559 +
1560 + if (count > max)
1561 + count = max;
1562 + bytes = count;
1563 + while (count--)
1564 + *cp++ = usb_readb(ep->dev, ep->fifo);
1565 +
1566 + return bytes;
1567 +}
1568 +
1569 +static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1570 + unsigned char *cp, int count)
1571 +{
1572 + DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1573 + while (count--)
1574 + usb_writeb(ep->dev, ep->fifo, *cp++);
1575 +}
1576 +
1577 +static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1578 +{
1579 + struct jz4740_udc *dev = ep->dev;
1580 + uint32_t csr;
1581 + uint8_t *buf;
1582 + unsigned bufferspace, count, is_short;
1583 +
1584 + DEBUG_EP0("%s\n", __FUNCTION__);
1585 +
1586 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1587 + if (!(csr & USB_CSR0_OUTPKTRDY))
1588 + return 0;
1589 +
1590 + buf = req->req.buf + req->req.actual;
1591 + prefetchw(buf);
1592 + bufferspace = req->req.length - req->req.actual;
1593 +
1594 + /* read all bytes from this packet */
1595 + if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1596 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1597 + req->req.actual += min(count, bufferspace);
1598 + } else /* zlp */
1599 + count = 0;
1600 +
1601 + is_short = (count < ep->ep.maxpacket);
1602 + DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1603 + ep->ep.name, csr, count,
1604 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
1605 +
1606 + while (likely(count-- != 0)) {
1607 + uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1608 +
1609 + if (unlikely(bufferspace == 0)) {
1610 + /* this happens when the driver's buffer
1611 + * is smaller than what the host sent.
1612 + * discard the extra data.
1613 + */
1614 + if (req->req.status != -EOVERFLOW)
1615 + DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1616 + count);
1617 + req->req.status = -EOVERFLOW;
1618 + } else {
1619 + *buf++ = byte;
1620 + bufferspace--;
1621 + }
1622 + }
1623 +
1624 + /* completion */
1625 + if (is_short || req->req.actual == req->req.length) {
1626 + done(ep, req, 0);
1627 + return 1;
1628 + }
1629 +
1630 + /* finished that packet. the next one may be waiting... */
1631 + return 0;
1632 +}
1633 +
1634 +/**
1635 + * udc_set_address - set the USB address for this device
1636 + * @address:
1637 + *
1638 + * Called from control endpoint function after it decodes a set address setup packet.
1639 + */
1640 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1641 +{
1642 + DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1643 +
1644 + dev->usb_address = address;
1645 + usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1646 +}
1647 +
1648 +/*
1649 + * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1650 + * - if error
1651 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1652 + * - else
1653 + * set USB_CSR0_SVDOUTPKTRDY bit
1654 + if last set USB_CSR0_DATAEND bit
1655 + */
1656 +static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1657 +{
1658 + struct jz4740_request *req;
1659 + struct jz4740_ep *ep = &dev->ep[0];
1660 + int ret;
1661 +
1662 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1663 +
1664 + if (list_empty(&ep->queue))
1665 + req = 0;
1666 + else
1667 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1668 +
1669 + if (req) {
1670 + if (req->req.length == 0) {
1671 + DEBUG_EP0("ZERO LENGTH OUT!\n");
1672 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1673 + dev->ep0state = WAIT_FOR_SETUP;
1674 + return;
1675 + } else if (kickstart) {
1676 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1677 + return;
1678 + }
1679 + ret = read_fifo_ep0(ep, req);
1680 + if (ret) {
1681 + /* Done! */
1682 + DEBUG_EP0("%s: finished, waiting for status\n",
1683 + __FUNCTION__);
1684 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1685 + dev->ep0state = WAIT_FOR_SETUP;
1686 + } else {
1687 + /* Not done yet.. */
1688 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1689 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1690 + }
1691 + } else {
1692 + DEBUG_EP0("NO REQ??!\n");
1693 + }
1694 +}
1695 +
1696 +/*
1697 + * DATA_STATE_XMIT
1698 + */
1699 +static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1700 +{
1701 + struct jz4740_request *req;
1702 + struct jz4740_ep *ep = &dev->ep[0];
1703 + int ret, need_zlp = 0;
1704 +
1705 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1706 +
1707 + if (list_empty(&ep->queue))
1708 + req = 0;
1709 + else
1710 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1711 +
1712 + if (!req) {
1713 + DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1714 + return 0;
1715 + }
1716 +
1717 + if (req->req.length == 0) {
1718 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1719 + dev->ep0state = WAIT_FOR_SETUP;
1720 + return 1;
1721 + }
1722 +
1723 + if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1724 + /* Next write will end with the packet size, */
1725 + /* so we need zero-length-packet */
1726 + need_zlp = 1;
1727 + }
1728 +
1729 + ret = write_fifo_ep0(ep, req);
1730 +
1731 + if (ret == 1 && !need_zlp) {
1732 + /* Last packet */
1733 + DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1734 +
1735 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1736 + dev->ep0state = WAIT_FOR_SETUP;
1737 + } else {
1738 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1739 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1740 + }
1741 +
1742 + if (need_zlp) {
1743 + DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1744 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1745 + dev->ep0state = DATA_STATE_NEED_ZLP;
1746 + }
1747 +
1748 + return 1;
1749 +}
1750 +
1751 +static int jz4740_handle_get_status(struct jz4740_udc *dev,
1752 + struct usb_ctrlrequest *ctrl)
1753 +{
1754 + struct jz4740_ep *ep0 = &dev->ep[0];
1755 + struct jz4740_ep *qep;
1756 + int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1757 + uint16_t val = 0;
1758 +
1759 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1760 +
1761 + if (reqtype == USB_RECIP_INTERFACE) {
1762 + /* This is not supported.
1763 + * And according to the USB spec, this one does nothing..
1764 + * Just return 0
1765 + */
1766 + DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1767 + } else if (reqtype == USB_RECIP_DEVICE) {
1768 + DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1769 + val |= (1 << 0); /* Self powered */
1770 + /*val |= (1<<1); *//* Remote wakeup */
1771 + } else if (reqtype == USB_RECIP_ENDPOINT) {
1772 + int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1773 +
1774 + DEBUG_SETUP
1775 + ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1776 + ep_num, ctrl->wLength);
1777 +
1778 + if (ctrl->wLength > 2 || ep_num > 3)
1779 + return -EOPNOTSUPP;
1780 +
1781 + qep = &dev->ep[ep_num];
1782 + if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1783 + && ep_index(qep) != 0) {
1784 + return -EOPNOTSUPP;
1785 + }
1786 +
1787 + jz_udc_set_index(dev, ep_index(qep));
1788 +
1789 + /* Return status on next IN token */
1790 + switch (qep->type) {
1791 + case ep_control:
1792 + val =
1793 + (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1794 + USB_CSR0_SENDSTALL;
1795 + break;
1796 + case ep_bulk_in:
1797 + case ep_interrupt:
1798 + val =
1799 + (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1800 + USB_INCSR_SENDSTALL;
1801 + break;
1802 + case ep_bulk_out:
1803 + val =
1804 + (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1805 + USB_OUTCSR_SENDSTALL;
1806 + break;
1807 + }
1808 +
1809 + /* Back to EP0 index */
1810 + jz_udc_set_index(dev, 0);
1811 +
1812 + DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1813 + ctrl->wIndex, val);
1814 + } else {
1815 + DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1816 + return -EOPNOTSUPP;
1817 + }
1818 +
1819 + /* Clear "out packet ready" */
1820 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1821 + /* Put status to FIFO */
1822 + jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1823 + /* Issue "In packet ready" */
1824 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1825 +
1826 + return 0;
1827 +}
1828 +
1829 +/*
1830 + * WAIT_FOR_SETUP (OUTPKTRDY)
1831 + * - read data packet from EP0 FIFO
1832 + * - decode command
1833 + * - if error
1834 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1835 + * - else
1836 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1837 + */
1838 +static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1839 +{
1840 + struct jz4740_ep *ep = &dev->ep[0];
1841 + struct usb_ctrlrequest ctrl;
1842 + int i;
1843 +
1844 + DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1845 +
1846 + /* Nuke all previous transfers */
1847 + nuke(ep, -EPROTO);
1848 +
1849 + /* read control req from fifo (8 bytes) */
1850 + jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1851 +
1852 + DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1853 + ctrl.bRequestType, ctrl.bRequest,
1854 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1855 +
1856 + /* Set direction of EP0 */
1857 + if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1858 + ep->bEndpointAddress |= USB_DIR_IN;
1859 + } else {
1860 + ep->bEndpointAddress &= ~USB_DIR_IN;
1861 + }
1862 +
1863 + /* Handle some SETUP packets ourselves */
1864 + switch (ctrl.bRequest) {
1865 + case USB_REQ_SET_ADDRESS:
1866 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1867 + break;
1868 +
1869 + DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1870 + udc_set_address(dev, ctrl.wValue);
1871 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1872 + return;
1873 +
1874 + case USB_REQ_SET_CONFIGURATION:
1875 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1876 + break;
1877 +
1878 + DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1879 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1880 +
1881 + /* Enable RESUME and SUSPEND interrupts */
1882 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1883 + break;
1884 +
1885 + case USB_REQ_SET_INTERFACE:
1886 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1887 + break;
1888 +
1889 + DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1890 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1891 + break;
1892 +
1893 + case USB_REQ_GET_STATUS:
1894 + if (jz4740_handle_get_status(dev, &ctrl) == 0)
1895 + return;
1896 +
1897 + case USB_REQ_CLEAR_FEATURE:
1898 + case USB_REQ_SET_FEATURE:
1899 + if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1900 + struct jz4740_ep *qep;
1901 + int ep_num = (ctrl.wIndex & 0x0f);
1902 +
1903 + /* Support only HALT feature */
1904 + if (ctrl.wValue != 0 || ctrl.wLength != 0
1905 + || ep_num > 3 || ep_num < 1)
1906 + break;
1907 +
1908 + qep = &dev->ep[ep_num];
1909 + spin_unlock(&dev->lock);
1910 + if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1911 + DEBUG_SETUP("SET_FEATURE (%d)\n",
1912 + ep_num);
1913 + jz4740_set_halt(&qep->ep, 1);
1914 + } else {
1915 + DEBUG_SETUP("CLR_FEATURE (%d)\n",
1916 + ep_num);
1917 + jz4740_set_halt(&qep->ep, 0);
1918 + }
1919 + spin_lock(&dev->lock);
1920 +
1921 + jz_udc_set_index(dev, 0);
1922 +
1923 + /* Reply with a ZLP on next IN token */
1924 + usb_setb(dev, JZ_REG_UDC_CSR0,
1925 + (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1926 + return;
1927 + }
1928 + break;
1929 +
1930 + default:
1931 + break;
1932 + }
1933 +
1934 + /* gadget drivers see class/vendor specific requests,
1935 + * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1936 + * and more.
1937 + */
1938 + if (dev->driver) {
1939 + /* device-2-host (IN) or no data setup command, process immediately */
1940 + spin_unlock(&dev->lock);
1941 +
1942 + i = dev->driver->setup(&dev->gadget, &ctrl);
1943 + spin_lock(&dev->lock);
1944 +
1945 + if (unlikely(i < 0)) {
1946 + /* setup processing failed, force stall */
1947 + DEBUG_SETUP
1948 + (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1949 + i);
1950 + jz_udc_set_index(dev, 0);
1951 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1952 +
1953 + /* ep->stopped = 1; */
1954 + dev->ep0state = WAIT_FOR_SETUP;
1955 + }
1956 + else {
1957 + DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1958 +/* if (!ctrl.wLength) {
1959 + usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1960 + }*/
1961 + }
1962 + }
1963 +}
1964 +
1965 +/*
1966 + * DATA_STATE_NEED_ZLP
1967 + */
1968 +static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1969 +{
1970 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1971 +
1972 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1973 + dev->ep0state = WAIT_FOR_SETUP;
1974 +}
1975 +
1976 +/*
1977 + * handle ep0 interrupt
1978 + */
1979 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1980 +{
1981 + struct jz4740_ep *ep = &dev->ep[0];
1982 + uint32_t csr;
1983 +
1984 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1985 + /* Set index 0 */
1986 + jz_udc_set_index(dev, 0);
1987 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1988 +
1989 + DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1990 +
1991 + /*
1992 + * if SENT_STALL is set
1993 + * - clear the SENT_STALL bit
1994 + */
1995 + if (csr & USB_CSR0_SENTSTALL) {
1996 + DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1997 + usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1998 + nuke(ep, -ECONNABORTED);
1999 + dev->ep0state = WAIT_FOR_SETUP;
2000 + return;
2001 + }
2002 +
2003 + /*
2004 + * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
2005 + * - fill EP0 FIFO
2006 + * - if last packet
2007 + * - set IN_PKT_RDY | DATA_END
2008 + * - else
2009 + * set IN_PKT_RDY
2010 + */
2011 + if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
2012 + DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
2013 + __FUNCTION__);
2014 +
2015 + switch (dev->ep0state) {
2016 + case DATA_STATE_XMIT:
2017 + DEBUG_EP0("continue with DATA_STATE_XMIT\n");
2018 + jz4740_ep0_in(dev, csr);
2019 + return;
2020 + case DATA_STATE_NEED_ZLP:
2021 + DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
2022 + jz4740_ep0_in_zlp(dev, csr);
2023 + return;
2024 + default:
2025 + /* Stall? */
2026 +// DEBUG_EP0("Odd state!! state = %s\n",
2027 +// state_names[dev->ep0state]);
2028 + dev->ep0state = WAIT_FOR_SETUP;
2029 + /* nuke(ep, 0); */
2030 + /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
2031 +// break;
2032 + return;
2033 + }
2034 + }
2035 +
2036 + /*
2037 + * if SETUPEND is set
2038 + * - abort the last transfer
2039 + * - set SERVICED_SETUP_END_BIT
2040 + */
2041 + if (csr & USB_CSR0_SETUPEND) {
2042 + DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
2043 +
2044 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
2045 + nuke(ep, 0);
2046 + dev->ep0state = WAIT_FOR_SETUP;
2047 + }
2048 +
2049 + /*
2050 + * if USB_CSR0_OUTPKTRDY is set
2051 + * - read data packet from EP0 FIFO
2052 + * - decode command
2053 + * - if error
2054 + * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
2055 + * - else
2056 + * set SVDOUTPKTRDY | DATAEND bits
2057 + */
2058 + if (csr & USB_CSR0_OUTPKTRDY) {
2059 +
2060 + DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
2061 + csr);
2062 +
2063 + switch (dev->ep0state) {
2064 + case WAIT_FOR_SETUP:
2065 + DEBUG_EP0("WAIT_FOR_SETUP\n");
2066 + jz4740_ep0_setup(dev, csr);
2067 + break;
2068 +
2069 + case DATA_STATE_RECV:
2070 + DEBUG_EP0("DATA_STATE_RECV\n");
2071 + jz4740_ep0_out(dev, csr, 0);
2072 + break;
2073 +
2074 + default:
2075 + /* send stall? */
2076 + DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
2077 + dev->ep0state);
2078 + break;
2079 + }
2080 + }
2081 +}
2082 +
2083 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
2084 +{
2085 + uint32_t csr;
2086 +
2087 + jz_udc_set_index(dev, 0);
2088 +
2089 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
2090 +
2091 + /* Clear "out packet ready" */
2092 +
2093 + if (ep_is_in(ep)) {
2094 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
2095 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2096 + dev->ep0state = DATA_STATE_XMIT;
2097 + jz4740_ep0_in(dev, csr);
2098 + } else {
2099 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2100 + dev->ep0state = DATA_STATE_RECV;
2101 + jz4740_ep0_out(dev, csr, 1);
2102 + }
2103 +}
2104 +
2105 +/** Handle USB RESET interrupt
2106 + */
2107 +static void jz4740_reset_irq(struct jz4740_udc *dev)
2108 +{
2109 + dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
2110 + USB_SPEED_HIGH : USB_SPEED_FULL;
2111 +
2112 + DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, dev->usb_address,
2113 + (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
2114 +}
2115 +
2116 +/*
2117 + * jz4740 usb device interrupt handler.
2118 + */
2119 +static irqreturn_t jz4740_udc_irq(int irq, void *_dev)
2120 +{
2121 + struct jz4740_udc *dev = _dev;
2122 + uint8_t index;
2123 +
2124 + uint32_t intr_usb = usb_readb(dev, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
2125 + uint32_t intr_in = usb_readw(dev, JZ_REG_UDC_INTRIN);
2126 + uint32_t intr_out = usb_readw(dev, JZ_REG_UDC_INTROUT);
2127 + uint32_t intr_dma = usb_readb(dev, JZ_REG_UDC_INTR);
2128 +
2129 + if (!intr_usb && !intr_in && !intr_out && !intr_dma)
2130 + return IRQ_HANDLED;
2131 +
2132 +
2133 + DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
2134 + intr_out, intr_in, intr_usb);
2135 +
2136 + spin_lock(&dev->lock);
2137 + index = usb_readb(dev, JZ_REG_UDC_INDEX);
2138 +
2139 + /* Check for resume from suspend mode */
2140 + if ((intr_usb & USB_INTR_RESUME) &&
2141 + (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
2142 + DEBUG("USB resume\n");
2143 + dev->driver->resume(&dev->gadget); /* We have suspend(), so we must have resume() too. */
2144 + }
2145 +
2146 + /* Check for system interrupts */
2147 + if (intr_usb & USB_INTR_RESET) {
2148 + DEBUG("USB reset\n");
2149 + jz4740_reset_irq(dev);
2150 + }
2151 +
2152 + /* Check for endpoint 0 interrupt */
2153 + if (intr_in & USB_INTR_EP0) {
2154 + DEBUG("USB_INTR_EP0 (control)\n");
2155 + jz4740_handle_ep0(dev, intr_in);
2156 + }
2157 +
2158 + /* Check for Bulk-IN DMA interrupt */
2159 + if (intr_dma & 0x1) {
2160 + int ep_num;
2161 + struct jz4740_ep *ep;
2162 + ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
2163 + ep = &dev->ep[ep_num + 1];
2164 + jz_udc_set_index(dev, ep_num);
2165 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
2166 +/* jz4740_in_epn(dev, ep_num, intr_in);*/
2167 + }
2168 +
2169 + /* Check for Bulk-OUT DMA interrupt */
2170 + if (intr_dma & 0x2) {
2171 + int ep_num;
2172 + ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
2173 + jz4740_out_epn(dev, ep_num, intr_out);
2174 + }
2175 +
2176 + /* Check for each configured endpoint interrupt */
2177 + if (intr_in & USB_INTR_INEP1) {
2178 + DEBUG("USB_INTR_INEP1\n");
2179 + jz4740_in_epn(dev, 1, intr_in);
2180 + }
2181 +
2182 + if (intr_in & USB_INTR_INEP2) {
2183 + DEBUG("USB_INTR_INEP2\n");
2184 + jz4740_in_epn(dev, 2, intr_in);
2185 + }
2186 +
2187 + if (intr_out & USB_INTR_OUTEP1) {
2188 + DEBUG("USB_INTR_OUTEP1\n");
2189 + jz4740_out_epn(dev, 1, intr_out);
2190 + }
2191 +
2192 + /* Check for suspend mode */
2193 + if ((intr_usb & USB_INTR_SUSPEND) &&
2194 + (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
2195 + DEBUG("USB suspend\n");
2196 + dev->driver->suspend(&dev->gadget);
2197 + /* Host unloaded from us, can do something, such as flushing
2198 + the NAND block cache etc. */
2199 + }
2200 +
2201 + jz_udc_set_index(dev, index);
2202 +
2203 + spin_unlock(&dev->lock);
2204 +
2205 + return IRQ_HANDLED;
2206 +}
2207 +
2208 +
2209 +
2210 +/*-------------------------------------------------------------------------*/
2211 +
2212 +/* Common functions - Added by River */
2213 +static struct jz4740_udc udc_dev;
2214 +
2215 +static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
2216 +{
2217 + return container_of(gadget, struct jz4740_udc, gadget);
2218 +}
2219 +/* End added */
2220 +
2221 +static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
2222 +{
2223 + DEBUG("%s, %p\n", __FUNCTION__, _gadget);
2224 + return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
2225 +}
2226 +
2227 +static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
2228 +{
2229 + /* host may not have enabled remote wakeup */
2230 + /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
2231 + return -EHOSTUNREACH;
2232 + udc_set_mask_UDCCR(UDCCR_RSM); */
2233 + return -ENOTSUPP;
2234 +}
2235 +
2236 +static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
2237 +{
2238 + struct jz4740_udc *udc = gadget_to_udc(_gadget);
2239 + unsigned long flags;
2240 +
2241 + local_irq_save(flags);
2242 +
2243 + if (on) {
2244 + udc->state = UDC_STATE_ENABLE;
2245 + udc_enable(udc);
2246 + } else {
2247 + udc->state = UDC_STATE_DISABLE;
2248 + udc_disable(udc);
2249 + }
2250 +
2251 + local_irq_restore(flags);
2252 +
2253 + return 0;
2254 +}
2255 +
2256 +
2257 +static const struct usb_gadget_ops jz4740_udc_ops = {
2258 + .get_frame = jz4740_udc_get_frame,
2259 + .wakeup = jz4740_udc_wakeup,
2260 + .pullup = jz4740_udc_pullup,
2261 + /* current versions must always be self-powered */
2262 +};
2263 +
2264 +static struct usb_ep_ops jz4740_ep_ops = {
2265 + .enable = jz4740_ep_enable,
2266 + .disable = jz4740_ep_disable,
2267 +
2268 + .alloc_request = jz4740_alloc_request,
2269 + .free_request = jz4740_free_request,
2270 +
2271 + .queue = jz4740_queue,
2272 + .dequeue = jz4740_dequeue,
2273 +
2274 + .set_halt = jz4740_set_halt,
2275 + .fifo_status = jz4740_fifo_status,
2276 + .fifo_flush = jz4740_fifo_flush,
2277 +};
2278 +
2279 +
2280 +/*-------------------------------------------------------------------------*/
2281 +
2282 +static struct jz4740_udc udc_dev = {
2283 + .usb_address = 0,
2284 + .gadget = {
2285 + .ops = &jz4740_udc_ops,
2286 + .ep0 = &udc_dev.ep[0].ep,
2287 + .name = "jz-udc",
2288 + .dev = {
2289 + .init_name = "gadget",
2290 + },
2291 + },
2292 +
2293 + /* control endpoint */
2294 + .ep[0] = {
2295 + .ep = {
2296 + .name = "ep0",
2297 + .ops = &jz4740_ep_ops,
2298 + .maxpacket = EP0_MAXPACKETSIZE,
2299 + },
2300 + .dev = &udc_dev,
2301 +
2302 + .bEndpointAddress = 0,
2303 + .bmAttributes = 0,
2304 +
2305 + .type = ep_control,
2306 + .fifo = JZ_REG_UDC_EP_FIFO(0),
2307 + .csr = JZ_REG_UDC_CSR0,
2308 + },
2309 +
2310 + /* bulk out endpoint */
2311 + .ep[1] = {
2312 + .ep = {
2313 + .name = "ep1out-bulk",
2314 + .ops = &jz4740_ep_ops,
2315 + .maxpacket = EPBULK_MAXPACKETSIZE,
2316 + },
2317 + .dev = &udc_dev,
2318 +
2319 + .bEndpointAddress = 1,
2320 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2321 +
2322 + .type = ep_bulk_out,
2323 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2324 + .csr = JZ_REG_UDC_OUTCSR,
2325 + },
2326 +
2327 + /* bulk in endpoint */
2328 + .ep[2] = {
2329 + .ep = {
2330 + .name = "ep1in-bulk",
2331 + .ops = &jz4740_ep_ops,
2332 + .maxpacket = EPBULK_MAXPACKETSIZE,
2333 + },
2334 + .dev = &udc_dev,
2335 +
2336 + .bEndpointAddress = 1 | USB_DIR_IN,
2337 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2338 +
2339 + .type = ep_bulk_in,
2340 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2341 + .csr = JZ_REG_UDC_INCSR,
2342 + },
2343 +
2344 + /* interrupt in endpoint */
2345 + .ep[3] = {
2346 + .ep = {
2347 + .name = "ep2in-int",
2348 + .ops = &jz4740_ep_ops,
2349 + .maxpacket = EPINTR_MAXPACKETSIZE,
2350 + },
2351 + .dev = &udc_dev,
2352 +
2353 + .bEndpointAddress = 2 | USB_DIR_IN,
2354 + .bmAttributes = USB_ENDPOINT_XFER_INT,
2355 +
2356 + .type = ep_interrupt,
2357 + .fifo = JZ_REG_UDC_EP_FIFO(2),
2358 + .csr = JZ_REG_UDC_INCSR,
2359 + },
2360 +};
2361 +
2362 +static void gadget_release(struct device *_dev)
2363 +{
2364 +}
2365 +
2366 +
2367 +static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2368 +{
2369 + struct jz4740_udc *dev = &udc_dev;
2370 + int ret;
2371 +
2372 + spin_lock_init(&dev->lock);
2373 + the_controller = dev;
2374 +
2375 + dev->dev = &pdev->dev;
2376 + dev_set_name(&dev->gadget.dev, "gadget");
2377 + dev->gadget.dev.parent = &pdev->dev;
2378 + dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2379 + dev->gadget.dev.release = gadget_release;
2380 +
2381 + ret = device_register(&dev->gadget.dev);
2382 + if (ret)
2383 + return ret;
2384 +
2385 + dev->clk = clk_get(&pdev->dev, "udc");
2386 + if (IS_ERR(dev->clk)) {
2387 + ret = PTR_ERR(dev->clk);
2388 + dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2389 + goto err_device_unregister;
2390 + }
2391 +
2392 + platform_set_drvdata(pdev, dev);
2393 +
2394 + dev->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2395 +
2396 + if (!dev->mem) {
2397 + ret = -ENOENT;
2398 + dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2399 + goto err_clk_put;
2400 + }
2401 +
2402 + dev->mem = request_mem_region(dev->mem->start, resource_size(dev->mem), pdev->name);
2403 +
2404 + if (!dev->mem) {
2405 + ret = -EBUSY;
2406 + dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2407 + goto err_device_unregister;
2408 + }
2409 +
2410 + dev->base = ioremap(dev->mem->start, resource_size(dev->mem));
2411 +
2412 + if (!dev->base) {
2413 + ret = -EBUSY;
2414 + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2415 + goto err_release_mem_region;
2416 + }
2417 +
2418 + dev->irq = platform_get_irq(pdev, 0);
2419 +
2420 + ret = request_irq(dev->irq, jz4740_udc_irq, IRQF_DISABLED,
2421 + pdev->name, dev);
2422 + if (ret) {
2423 + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2424 + goto err_iounmap;
2425 + }
2426 +
2427 + udc_disable(dev);
2428 + udc_reinit(dev);
2429 +
2430 + return 0;
2431 +
2432 +err_iounmap:
2433 + iounmap(dev->base);
2434 +err_release_mem_region:
2435 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2436 +err_clk_put:
2437 + clk_put(dev->clk);
2438 +err_device_unregister:
2439 + device_unregister(&dev->gadget.dev);
2440 + platform_set_drvdata(pdev, NULL);
2441 +
2442 + the_controller = 0;
2443 +
2444 + return ret;
2445 +}
2446 +
2447 +static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2448 +{
2449 + struct jz4740_udc *dev = platform_get_drvdata(pdev);
2450 +
2451 + if (dev->driver)
2452 + return -EBUSY;
2453 +
2454 + udc_disable(dev);
2455 +
2456 + free_irq(dev->irq, dev);
2457 + iounmap(dev->base);
2458 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2459 + clk_put(dev->clk);
2460 +
2461 + platform_set_drvdata(pdev, NULL);
2462 + device_unregister(&dev->gadget.dev);
2463 + the_controller = NULL;
2464 +
2465 + return 0;
2466 +}
2467 +
2468 +#ifdef CONFIG_PM
2469 +
2470 +static int jz4740_udc_suspend(struct device *dev)
2471 +{
2472 + struct jz4740_udc *udc = dev_get_drvdata(dev);
2473 +
2474 + if (udc->state == UDC_STATE_ENABLE)
2475 + udc_disable(udc);
2476 +
2477 + return 0;
2478 +}
2479 +
2480 +static int jz4740_udc_resume(struct device *dev)
2481 +{
2482 + struct jz4740_udc *udc = dev_get_drvdata(dev);
2483 +
2484 + if (udc->state == UDC_STATE_ENABLE)
2485 + udc_enable(udc);
2486 +
2487 + return 0;
2488 +}
2489 +
2490 +static struct dev_pm_ops jz4740_udc_pm_ops = {
2491 + .suspend = jz4740_udc_suspend,
2492 + .resume = jz4740_udc_resume,
2493 +};
2494 +
2495 +#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2496 +
2497 +#else
2498 +
2499 +#define JZ4740_UDC_PM_OPS NULL
2500 +
2501 +#endif
2502 +
2503 +static struct platform_driver udc_driver = {
2504 + .probe = jz4740_udc_probe,
2505 + .remove = __devexit_p(jz4740_udc_remove),
2506 + .driver = {
2507 + .name = "jz-udc",
2508 + .owner = THIS_MODULE,
2509 + .pm = JZ4740_UDC_PM_OPS,
2510 + },
2511 +};
2512 +
2513 +/*-------------------------------------------------------------------------*/
2514 +
2515 +static int __init udc_init (void)
2516 +{
2517 + return platform_driver_register(&udc_driver);
2518 +}
2519 +module_init(udc_init);
2520 +
2521 +static void __exit udc_exit (void)
2522 +{
2523 + platform_driver_unregister(&udc_driver);
2524 +}
2525 +module_exit(udc_exit);
2526 +
2527 +MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2528 +MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2529 +MODULE_LICENSE("GPL");
2530 diff --git a/drivers/usb/gadget/jz4740_udc.h b/drivers/usb/gadget/jz4740_udc.h
2531 new file mode 100644
2532 index 0000000..ac1540f
2533 --- /dev/null
2534 +++ b/drivers/usb/gadget/jz4740_udc.h
2535 @@ -0,0 +1,99 @@
2536 +/*
2537 + * linux/drivers/usb/gadget/jz4740_udc.h
2538 + *
2539 + * Ingenic JZ4740 on-chip high speed USB device controller
2540 + *
2541 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
2542 + * Author: <jlwei@ingenic.cn>
2543 + *
2544 + * This program is free software; you can redistribute it and/or modify
2545 + * it under the terms of the GNU General Public License as published by
2546 + * the Free Software Foundation; either version 2 of the License, or
2547 + * (at your option) any later version.
2548 + */
2549 +
2550 +#ifndef __USB_GADGET_JZ4740_H__
2551 +#define __USB_GADGET_JZ4740_H__
2552 +
2553 +/*-------------------------------------------------------------------------*/
2554 +
2555 +// Max packet size
2556 +#define EP0_MAXPACKETSIZE 64
2557 +#define EPBULK_MAXPACKETSIZE 512
2558 +#define EPINTR_MAXPACKETSIZE 64
2559 +
2560 +#define UDC_MAX_ENDPOINTS 4
2561 +
2562 +/*-------------------------------------------------------------------------*/
2563 +
2564 +typedef enum ep_type {
2565 + ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2566 +} ep_type_t;
2567 +
2568 +struct jz4740_ep {
2569 + struct usb_ep ep;
2570 + struct jz4740_udc *dev;
2571 +
2572 + const struct usb_endpoint_descriptor *desc;
2573 + unsigned long pio_irqs;
2574 +
2575 + uint8_t stopped;
2576 + uint8_t bEndpointAddress;
2577 + uint8_t bmAttributes;
2578 +
2579 + ep_type_t type;
2580 + size_t fifo;
2581 + u32 csr;
2582 +
2583 + uint32_t reg_addr;
2584 + struct list_head queue;
2585 +};
2586 +
2587 +struct jz4740_request {
2588 + struct usb_request req;
2589 + struct list_head queue;
2590 +};
2591 +
2592 +enum ep0state {
2593 + WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
2594 + DATA_STATE_XMIT, /* data tx stage */
2595 + DATA_STATE_NEED_ZLP, /* data tx zlp stage */
2596 + WAIT_FOR_OUT_STATUS, /* status stages */
2597 + DATA_STATE_RECV, /* data rx stage */
2598 +};
2599 +
2600 +/* For function binding with UDC Disable - Added by River */
2601 +typedef enum {
2602 + UDC_STATE_ENABLE = 0,
2603 + UDC_STATE_DISABLE,
2604 +}udc_state_t;
2605 +
2606 +struct jz4740_udc {
2607 + struct usb_gadget gadget;
2608 + struct usb_gadget_driver *driver;
2609 + struct device *dev;
2610 + spinlock_t lock;
2611 +
2612 + enum ep0state ep0state;
2613 + struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2614 +
2615 + unsigned char usb_address;
2616 +
2617 + udc_state_t state;
2618 +
2619 + struct resource *mem;
2620 + void __iomem *base;
2621 + int irq;
2622 + uint32_t in_mask;
2623 + uint32_t out_mask;
2624 +
2625 + struct clk *clk;
2626 +};
2627 +
2628 +extern struct jz4740_udc *the_controller;
2629 +
2630 +#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
2631 +#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
2632 +#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
2633 +
2634 +#endif /* __USB_GADGET_JZ4740_H__ */
2635 --
2636 1.5.6.5
2637
OpenWrt Source Repository