toolchain/gcc/patches/4.3.5/949-avr32_nan_by_zero_div.patch

   1 --- a/gcc/config/avr32/lib1funcs.S
   2 +++ b/gcc/config/avr32/lib1funcs.S
   3 @@ -1852,7 +1852,11 @@ __avr32_f64_div_res_subnormal:/* Divide
   4          mov     r10, 0
   5          ldm     sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
   6
   7 -17:     /* Return INF. */
   8 +17:
   9 +        /* Check if op1 is zero. */
  10 +        or      r4, r10, r11
  11 +        breq    __avr32_f64_div_op1_zero
  12 +        /* Return INF. */
  13          mov     r11, lr /*Get correct sign*/
  14          andh    r11, 0x8000, COH
  15          orh     r11, 0x7ff0