uboot-sunxi: update to version 2017.07

[openwrt/openwrt.git] / package / boot / uboot-sunxi / patches / 091-sun6i-sync-PLL1-multdiv-with-Boot1.patch

diff --git a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch
index a402feb3cdb6e720bf4eb896c1841d3f5d852230..40d79878ad66f4261e69ac40d39046fd3de25af8 100644 (file)
--- a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch
+++ b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch
@@ -12,9 +12,9 @@ More specifically, the following settings are now used:
  * up to 1152MHz: mul=3, div=2 (unchanged)
  * above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
 
---- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
-+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
-@@ -122,11 +122,12 @@ void clock_set_pll1(unsigned int clk)
+--- a/arch/arm/mach-sunxi/clock_sun6i.c
++++ b/arch/arm/mach-sunxi/clock_sun6i.c
+@@ -107,11 +107,12 @@ void clock_set_pll1(unsigned int clk)
        struct sunxi_ccm_reg * const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
        const int p = 0;