static void ag71xx_ring_free(struct ag71xx_ring *ring)
{
+ int ring_size = BIT(ring->order);
kfree(ring->buf);
if (ring->descs_cpu)
- dma_free_coherent(NULL, ring->size * ring->desc_size,
+ dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
ring->descs_cpu, ring->descs_dma);
}
static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
{
+ int ring_size = BIT(ring->order);
int err;
- ring->desc_size = sizeof(struct ag71xx_desc);
- if (ring->desc_size % cache_line_size()) {
- DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
- ring, ring->desc_size,
- roundup(ring->desc_size, cache_line_size()));
- ring->desc_size = roundup(ring->desc_size, cache_line_size());
- }
-
- ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
+ ring->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
&ring->descs_dma, GFP_ATOMIC);
if (!ring->descs_cpu) {
err = -ENOMEM;
}
- ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
+ ring->buf = kzalloc(ring_size * sizeof(*ring->buf), GFP_KERNEL);
if (!ring->buf) {
err = -ENOMEM;
goto err;
{
struct ag71xx_ring *ring = &ag->tx_ring;
struct net_device *dev = ag->dev;
+ int ring_mask = BIT(ring->order) - 1;
u32 bytes_compl = 0, pkts_compl = 0;
while (ring->curr != ring->dirty) {
struct ag71xx_desc *desc;
- u32 i = ring->dirty % ring->size;
+ u32 i = ring->dirty & ring_mask;
desc = ag71xx_ring_desc(ring, i);
if (!ag71xx_desc_empty(desc)) {
static void ag71xx_ring_tx_init(struct ag71xx *ag)
{
struct ag71xx_ring *ring = &ag->tx_ring;
+ int ring_size = BIT(ring->order);
+ int ring_mask = ring_size - 1;
int i;
- for (i = 0; i < ring->size; i++) {
+ for (i = 0; i < ring_size; i++) {
struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
desc->next = (u32) (ring->descs_dma +
- ring->desc_size * ((i + 1) % ring->size));
+ AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
desc->ctrl = DESC_EMPTY;
ring->buf[i].skb = NULL;
static void ag71xx_ring_rx_clean(struct ag71xx *ag)
{
struct ag71xx_ring *ring = &ag->rx_ring;
+ int ring_size = BIT(ring->order);
int i;
if (!ring->buf)
return;
- for (i = 0; i < ring->size; i++)
+ for (i = 0; i < ring_size; i++)
if (ring->buf[i].rx_buf) {
dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
ag->rx_buf_size, DMA_FROM_DEVICE);
static int ag71xx_ring_rx_init(struct ag71xx *ag)
{
struct ag71xx_ring *ring = &ag->rx_ring;
+ int ring_size = BIT(ring->order);
+ int ring_mask = BIT(ring->order) - 1;
unsigned int i;
int ret;
int offset = ag71xx_buffer_offset(ag);
ret = 0;
- for (i = 0; i < ring->size; i++) {
+ for (i = 0; i < ring_size; i++) {
struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
desc->next = (u32) (ring->descs_dma +
- ring->desc_size * ((i + 1) % ring->size));
+ AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
DBG("ag71xx: RX desc at %p, next is %08x\n",
desc, desc->next);
}
- for (i = 0; i < ring->size; i++) {
+ for (i = 0; i < ring_size; i++) {
struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
static int ag71xx_ring_rx_refill(struct ag71xx *ag)
{
struct ag71xx_ring *ring = &ag->rx_ring;
+ int ring_mask = BIT(ring->order) - 1;
unsigned int count;
int offset = ag71xx_buffer_offset(ag);
struct ag71xx_desc *desc;
unsigned int i;
- i = ring->dirty % ring->size;
+ i = ring->dirty & ring_mask;
desc = ag71xx_ring_desc(ring, i);
if (!ring->buf[i].rx_buf &&
static void ag71xx_hw_setup(struct ag71xx *ag)
{
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ u32 init = MAC_CFG1_INIT;
/* setup MAC configuration registers */
- ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
+ if (pdata->use_flow_control)
+ init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
struct net_device *dev = ag->dev;
u32 reset_mask = pdata->reset_bit;
- u32 rx_ds, tx_ds;
+ u32 rx_ds;
u32 mii_reg;
reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
+ ag71xx_hw_stop(ag);
+ wmb();
+
mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
- tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
+
+ ag71xx_tx_packets(ag, true);
ath79_device_reset_set(reset_mask);
udelay(10);
ag71xx_dma_reset(ag);
ag71xx_hw_setup(ag);
- ag71xx_tx_packets(ag, true);
+ ag->tx_ring.curr = 0;
+ ag->tx_ring.dirty = 0;
+ netdev_reset_queue(ag->dev);
/* setup max frame length */
ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
ag71xx_max_frame_len(ag->dev->mtu));
ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
- ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
ag71xx_hw_set_macaddr(ag, dev->dev_addr);
{
int i;
struct ag71xx_desc *desc;
+ int ring_mask = BIT(ring->order) - 1;
int ndesc = 0;
int split = ring->desc_split;
while (len > 0) {
unsigned int cur_len = len;
- i = (ring->curr + ndesc) % ring->size;
+ i = (ring->curr + ndesc) & ring_mask;
desc = ag71xx_ring_desc(ring, i);
if (!ag71xx_desc_empty(desc))
{
struct ag71xx *ag = netdev_priv(dev);
struct ag71xx_ring *ring = &ag->tx_ring;
+ int ring_mask = BIT(ring->order) - 1;
+ int ring_size = BIT(ring->order);
struct ag71xx_desc *desc;
dma_addr_t dma_addr;
int i, n, ring_min;
dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
DMA_TO_DEVICE);
- i = ring->curr % ring->size;
+ i = ring->curr & ring_mask;
desc = ag71xx_ring_desc(ring, i);
/* setup descriptor fields */
if (n < 0)
goto err_drop_unmap;
- i = (ring->curr + n - 1) % ring->size;
+ i = (ring->curr + n - 1) & ring_mask;
ring->buf[i].len = skb->len;
ring->buf[i].skb = skb;
ring->buf[i].timestamp = jiffies;
netdev_sent_queue(dev, skb->len);
+ skb_tx_timestamp(skb);
+
desc->ctrl &= ~DESC_EMPTY;
ring->curr += n;
if (ring->desc_split)
ring_min *= AG71XX_TX_RING_DS_PER_PKT;
- if (ring->curr - ring->dirty >= ring->size - ring_min) {
+ if (ring->curr - ring->dirty >= ring_size - ring_min) {
DBG("%s: tx queue full\n", dev->name);
netif_stop_queue(dev);
}
if (netif_msg_tx_err(ag))
pr_info("%s: tx timeout\n", ag->dev->name);
- schedule_work(&ag->restart_work);
+ schedule_delayed_work(&ag->restart_work, 1);
}
static void ag71xx_restart_work_func(struct work_struct *work)
{
- struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
+ struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
rtnl_lock();
ag71xx_hw_disable(ag);
{
struct ag71xx_ring *ring = &ag->tx_ring;
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ bool dma_stuck = false;
+ int ring_mask = BIT(ring->order) - 1;
+ int ring_size = BIT(ring->order);
int sent = 0;
int bytes_compl = 0;
int n = 0;
DBG("%s: processing TX ring\n", ag->dev->name);
while (ring->dirty + n != ring->curr) {
- unsigned int i = (ring->dirty + n) % ring->size;
+ unsigned int i = (ring->dirty + n) & ring_mask;
struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
struct sk_buff *skb = ring->buf[i].skb;
if (!flush && !ag71xx_desc_empty(desc)) {
if (pdata->is_ar724x &&
- ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
- schedule_work(&ag->restart_work);
+ ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) {
+ schedule_delayed_work(&ag->restart_work, HZ / 2);
+ dma_stuck = true;
+ }
break;
}
+ if (flush)
+ desc->ctrl |= DESC_EMPTY;
+
n++;
if (!skb)
continue;
return 0;
netdev_completed_queue(ag->dev, sent, bytes_compl);
- if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
+ if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
netif_wake_queue(ag->dev);
+ if (!dma_stuck)
+ cancel_delayed_work(&ag->restart_work);
+
return sent;
}
struct ag71xx_ring *ring = &ag->rx_ring;
int offset = ag71xx_buffer_offset(ag);
unsigned int pktlen_mask = ag->desc_pktlen_mask;
+ int ring_mask = BIT(ring->order) - 1;
+ int ring_size = BIT(ring->order);
+ struct sk_buff_head queue;
+ struct sk_buff *skb;
int done = 0;
DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
dev->name, limit, ring->curr, ring->dirty);
+ skb_queue_head_init(&queue);
+
while (done < limit) {
- unsigned int i = ring->curr % ring->size;
+ unsigned int i = ring->curr & ring_mask;
struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
- struct sk_buff *skb;
int pktlen;
int err = 0;
if (ag71xx_desc_empty(desc))
break;
- if ((ring->dirty + ring->size) == ring->curr) {
+ if ((ring->dirty + ring_size) == ring->curr) {
ag71xx_assert(0);
break;
}
} else {
skb->dev = dev;
skb->ip_summed = CHECKSUM_NONE;
- skb->protocol = eth_type_trans(skb, dev);
- netif_receive_skb(skb);
+ __skb_queue_tail(&queue, skb);
}
next:
ag71xx_ring_rx_refill(ag);
+ while ((skb = __skb_dequeue(&queue)) != NULL) {
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_receive_skb(skb);
+ }
+
DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
dev->name, ring->curr, ring->dirty, done);
struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
struct net_device *dev = ag->dev;
- struct ag71xx_ring *rx_ring;
+ struct ag71xx_ring *rx_ring = &ag->rx_ring;
+ int rx_ring_size = BIT(rx_ring->order);
unsigned long flags;
u32 status;
int tx_done;
ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
- rx_ring = &ag->rx_ring;
- if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
+ if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
goto oom;
status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
struct resource *res;
struct ag71xx *ag;
struct ag71xx_platform_data *pdata;
- int err;
+ int tx_size, err;
pdata = pdev->dev.platform_data;
if (!pdata) {
dev->netdev_ops = &ag71xx_netdev_ops;
dev->ethtool_ops = &ag71xx_ethtool_ops;
- INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
+ INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
init_timer(&ag->oom_timer);
ag->oom_timer.data = (unsigned long) dev;
ag->oom_timer.function = ag71xx_oom_timer_handler;
- ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
- ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
+ tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
+ ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
ag->max_frame_len = pdata->max_frame_len;
ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
if (!pdata->is_ar724x && !pdata->is_ar91xx) {
ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
- ag->tx_ring.size *= AG71XX_TX_RING_DS_PER_PKT;
+ tx_size *= AG71XX_TX_RING_DS_PER_PKT;
}
+ ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
ag->stop_desc = dma_alloc_coherent(NULL,
sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
projects / openwrt / openwrt.git / blobdiff