ar71xx: use ath79_setup_qca955x_eth_cfg helper for QCA955x based boards
[openwrt/openwrt.git] / target / linux / ar71xx / patches-3.10 / 609-MIPS-ath79-ap136-fixes.patch
index 4b530a7..4309712 100644 (file)
@@ -86,7 +86,7 @@
                .gpio           = AP136_GPIO_LED_USB,
                .active_low     = 1,
        }
-@@ -98,65 +106,169 @@ static struct gpio_keys_button ap136_gpi
+@@ -98,65 +106,152 @@ static struct gpio_keys_button ap136_gpi
        },
  };
  
 -      .bus_num        = 0,
 -      .num_chipselect = 1,
 -};
-+static void __init ap136_gmac_setup(void)
-+{
-+      void __iomem *base;
-+      u32 t;
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data ap136_ath9k_data;
-+      base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
--static int ap136_pci_plat_dev_init(struct pci_dev *dev)
--{
--      if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
--              dev->dev.platform_data = &ap136_ath9k_data;
-+      t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
--      return 0;
--}
-+      t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
-+      t |= QCA955X_ETH_CFG_RGMII_EN;
--static void __init ap136_pci_init(u8 *eeprom)
--{
--      memcpy(ap136_ath9k_data.eeprom_data, eeprom,
--             sizeof(ap136_ath9k_data.eeprom_data));
-+      __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
--      ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
--      ath79_register_pci();
-+      iounmap(base);
- }
--#else
--static inline void ap136_pci_init(void) {}
--#endif /* CONFIG_PCI */
--static void __init ap136_setup(void)
 +static void __init ap136_common_setup(void)
- {
-       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++{
++      u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
 +      ath79_register_m25p80(NULL);
 +
-       ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
-                                ap136_leds_gpio);
-       ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
-                                       ARRAY_SIZE(ap136_gpio_keys),
-                                       ap136_gpio_keys);
--      ath79_register_spi(&ap136_spi_data, ap136_spi_info,
--                         ARRAY_SIZE(ap136_spi_info));
++      ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
++                               ap136_leds_gpio);
++      ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
++                                      ARRAY_SIZE(ap136_gpio_keys),
++                                      ap136_gpio_keys);
 +
-       ath79_register_usb();
--      ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
--      ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
++      ath79_register_usb();
 +      ath79_register_nfc();
 +
 +      ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
 +
-+      ap136_gmac_setup();
-+
++      ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ap136_ath9k_data;
 +      ath79_register_mdio(0, 0x0);
-+
+-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
 +      ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
 +
 +      mdiobus_register_board_info(ap136_mdio0_info,
 +}
 +
 +static void __init ap136_010_setup(void)
-+{
+ {
+-      if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
+-              dev->dev.platform_data = &ap136_ath9k_data;
 +      u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
-+
+-      return 0;
 +      /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
 +      ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
 +      ap136_ar8327_pad0_cfg.txclk_delay_en = true;
 +      ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
  }
  
- MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
-            "Atheros AP136-010 reference board",
--           ap136_setup);
+-static void __init ap136_pci_init(u8 *eeprom)
++MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
++           "Atheros AP136-010 reference board",
 +           ap136_010_setup);
 +
 +static void __init ap136_020_common_setup(void)
-+{
+ {
+-      memcpy(ap136_ath9k_data.eeprom_data, eeprom,
+-             sizeof(ap136_ath9k_data.eeprom_data));
 +      /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
 +      ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
 +      ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
 +      ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
 +      ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
 +      ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
-+
+-      ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
+-      ath79_register_pci();
 +      ath79_eth0_pll_data.pll_1000 = 0x56000000;
 +      ath79_eth1_pll_data.pll_1000 = 0x03000101;
 +
 +      ap136_common_setup();
-+}
-+
+ }
+-#else
+-static inline void ap136_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+-static void __init ap136_setup(void)
 +static void __init ap136_020_setup(void)
-+{
-+      u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
-+
+ {
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+-      ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
+-                               ap136_leds_gpio);
+-      ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
+-                                      ARRAY_SIZE(ap136_gpio_keys),
+-                                      ap136_gpio_keys);
+-      ath79_register_spi(&ap136_spi_data, ap136_spi_info,
+-                         ARRAY_SIZE(ap136_spi_info));
+-      ath79_register_usb();
+-      ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
+-      ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
 +      ap136_020_common_setup();
 +      ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
-+}
-+
+ }
+-MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
+-           "Atheros AP136-010 reference board",
+-           ap136_setup);
 +MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
 +           "Atheros AP136-020 reference board",
 +           ap136_020_setup);