+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
--- /dev/null
+++ b/arch/mips/ar231x/board.c
-@@ -0,0 +1,263 @@
+@@ -0,0 +1,229 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+
+void (*ar231x_irq_dispatch)(void);
+
-+static inline bool
-+check_radio_magic(u8 *addr)
++static inline bool check_radio_magic(u8 *addr)
+{
+ addr += 0x7a; /* offset for flash magic */
-+ if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
-+ return 1;
++ return (addr[0] == 0x5a) && (addr[1] == 0xa5);
++}
+
-+ return 0;
++static inline bool check_notempty(u8 *addr)
++{
++ return *(u32 *)addr != 0xffffffff;
+}
+
-+static inline bool
-+check_board_data(u8 *flash_limit, u8 *addr, bool broken)
++static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
+{
+ /* config magic found */
+ if (*((u32 *)addr) == AR231X_BD_MAGIC)
-+ return 1;
++ return true;
+
+ if (!broken)
-+ return 0;
++ return false;
+
+ if (check_radio_magic(addr + 0xf8))
+ ar231x_board.radio = addr + 0xf8;
+ if ((addr < flash_limit + 0x10000) &&
-+ check_radio_magic(addr + 0x10000))
++ check_radio_magic(addr + 0x10000))
+ ar231x_board.radio = addr + 0x10000;
+
+ if (ar231x_board.radio) {
+ /* broken board data detected, use radio data to find the
+ * offset, user will fix this */
-+ return 1;
++ return true;
+ }
-+ return 0;
++
++ return false;
+}
+
-+static u8 *
-+find_board_config(u8 *flash_limit, bool broken)
++static u8 * __init find_board_config(u8 *flash_limit, bool broken)
+{
+ u8 *addr;
-+ int found = 0;
++ u8 *begin = flash_limit - 0x1000;
++ u8 *end = flash_limit - 0x30000;
+
-+ for (addr = flash_limit - 0x1000;
-+ addr >= flash_limit - 0x30000;
-+ addr -= 0x1000) {
++ for (addr = begin; addr >= end; addr -= 0x1000)
++ if (check_board_data(flash_limit, addr, broken))
++ return addr;
+
-+ if (check_board_data(flash_limit, addr, broken)) {
-+ found = 1;
-+ break;
-+ }
-+ }
-+
-+ if (!found)
-+ addr = NULL;
-+
-+ return addr;
++ return NULL;
+}
+
-+static u8 *
-+find_radio_config(u8 *flash_limit, u8 *board_config)
++static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
+{
-+ int found;
-+ u8 *radio_config;
++ u8 *rcfg, *begin, *end;
+
+ /*
+ * Now find the start of Radio Configuration data, using heuristics:
+ * Search forward from Board Configuration data by 0x1000 bytes
+ * at a time until we find non-0xffffffff.
+ */
-+ found = 0;
-+ for (radio_config = board_config + 0x1000;
-+ (radio_config < flash_limit);
-+ radio_config += 0x1000) {
-+ if ((*(u32 *)radio_config != 0xffffffff) &&
-+ check_radio_magic(radio_config)) {
-+ found = 1;
-+ break;
-+ }
-+ }
++ begin = bcfg + 0x1000;
++ end = flash_limit;
++ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
++ if (check_notempty(rcfg) && check_radio_magic(rcfg))
++ return rcfg;
+
+ /* AR2316 relocates radio config to new location */
-+ if (!found) {
-+ for (radio_config = board_config + 0xf8;
-+ (radio_config < flash_limit - 0x1000 + 0xf8);
-+ radio_config += 0x1000) {
-+ if ((*(u32 *)radio_config != 0xffffffff) &&
-+ check_radio_magic(radio_config)) {
-+ found = 1;
-+ break;
-+ }
-+ }
-+ }
++ begin = bcfg + 0xf8;
++ end = flash_limit - 0x1000 + 0xf8;
++ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
++ if (check_notempty(rcfg) && check_radio_magic(rcfg))
++ return rcfg;
+
-+ if (!found) {
-+ pr_warn("WARNING: Could not find Radio Configuration data\n");
-+ radio_config = 0;
-+ }
++ pr_warn("WARNING: Could not find Radio Configuration data\n");
+
-+ return radio_config;
++ return NULL;
+}
+
-+int __init
-+ar231x_find_config(u8 *flash_limit)
++int __init ar231x_find_config(u8 *flash_limit)
+{
+ struct ar231x_boarddata *config;
+ unsigned int rcfg_size;
+ if (broken_boarddata) {
+ pr_warn("WARNING: broken board data detected\n");
+ config = ar231x_board.config;
-+ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
++ if (is_zero_ether_addr(config->enet0_mac)) {
+ pr_info("Fixing up empty mac addresses\n");
+ config->reset_config_gpio = 0xffff;
+ config->sys_led_gpio = 0xffff;
+ }
+ }
+
-+
+ /* Radio config starts 0x100 bytes after board config, regardless
+ * of what the physical layout on the flash chip looks like */
+
+ mac_addr = &radio_data[0x1d * 2];
+ if (is_broadcast_ether_addr(mac_addr)) {
+ pr_info("Radio MAC is blank; using board-data\n");
-+ memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
++ ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
+ }
+
+ return 0;
+}
+
-+static void
-+ar231x_halt(void)
++static void ar231x_halt(void)
+{
+ local_irq_disable();
+ while (1)
+ ;
+}
+
-+void __init
-+plat_mem_setup(void)
++void __init plat_mem_setup(void)
+{
+ _machine_halt = ar231x_halt;
+ pm_power_off = ar231x_halt;
+ write_c0_watchlo0(0);
+}
+
-+
-+asmlinkage void
-+plat_irq_dispatch(void)
++asmlinkage void plat_irq_dispatch(void)
+{
+ ar231x_irq_dispatch();
+}
+
-+void __init
-+plat_time_init(void)
++void __init plat_time_init(void)
+{
+ ar5312_time_init();
+ ar2315_time_init();
+}
+
-+unsigned int __cpuinit
-+get_c0_compare_int(void)
++unsigned int __cpuinit get_c0_compare_int(void)
+{
+ return CP0_LEGACY_COMPARE_IRQ;
+}
+
-+void __init
-+arch_init_irq(void)
++void __init arch_init_irq(void)
+{
+ clear_c0_status(ST0_IM);
+ mips_cpu_irq_init();
+ ar2315_irq_init();
+}
+
-+
--- /dev/null
+++ b/arch/mips/ar231x/prom.c
@@ -0,0 +1,37 @@
+}
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
-@@ -0,0 +1,83 @@
+@@ -0,0 +1,85 @@
+#ifndef __ASM_MACH_AR231X_PLATFORM_H
+#define __ASM_MACH_AR231X_PLATFORM_H
+
++#include <linux/etherdevice.h>
++
+/*
+ * This is board-specific data that is stored in a "fixed" location in flash.
+ * It is shared across operating systems, so it should not be changed lightly.
+ u32 sys_freq; /* System frequency in Hz */
+ u32 cnt_freq; /* Calculated C0_COUNT frequency */
+
-+ u8 wlan0_mac[6];
-+ u8 enet0_mac[6];
-+ u8 enet1_mac[6];
++ u8 wlan0_mac[ETH_ALEN];
++ u8 enet0_mac[ETH_ALEN];
++ u8 enet1_mac[ETH_ALEN];
+
+ u16 pci_id; /* Pseudo PCIID for common code */
+ u16 mem_cap; /* cap bank1 in MB */
+
+ /* version 3 */
-+ u8 wlan1_mac[6]; /* (ar5212) */
++ u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
+};
+
+#define BOARD_CONFIG_BUFSZ 0x1000
+#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
-@@ -0,0 +1,79 @@
+@@ -0,0 +1,77 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+
+ if (dev && dev->bus == &pci_bus_type)
+ return PCI_DMA_OFFSET;
-+ else
+#endif
-+ return 0;
++ return 0;
+}
+
+static inline dma_addr_t
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
-+ return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+#endif /* __ASM_MACH_AR231X_WAR_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
-@@ -0,0 +1,617 @@
+@@ -0,0 +1,614 @@
+/*
+ * Register definitions for AR2315+
+ *
+#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
+#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
+
-+
+/*
+ * Miscellaneous interrupts, which share IP2.
+ */
+#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
+#define AR2315_MISC_IRQ_COUNT 10
+
-+
+/*
+ * Address map
+ */
+#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
+
+/*
-+ * Reset Register
++ * Cold reset register
+ */
+#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
+
+ RESET_COLD_AHB) /* full system */
+#define AR2317_RESET_SYSTEM 0x00000010
+
-+
++/*
++ * Reset register
++ */
+#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
+
+/* warm reset WLAN0 MAC */
+#define AR2315_CONFIG_CPU_MMR 0x00040000
+#define AR2315_CONFIG_BIG 0x00000400
+
-+
+/*
+ * NMI control
+ */
+#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
+#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
+
-+
+/*
+ * Local Bus Interface Registers
+ */
+#define AR2315_LBM_TIMEOUT_SHFT 7
+#define AR2315_LBM_PORTMUX 0x07000000
+
-+
+#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
+
+#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
+#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
-@@ -0,0 +1,253 @@
+@@ -0,0 +1,249 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+/*
+ * IRQs
+ */
-+
+#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
+#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
+#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
+#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
+#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
+
-+
+/*
+ * Miscellaneous interrupts, which share IP6.
+ */
+#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
+#define AR5312_MISC_IRQ_COUNT 10
+
-+
-+/* Address Map */
++/*
++ * Address Map
++ */
+#define AR5312_WLAN0 0x18000000
+#define AR5312_WLAN1 0x18500000
+#define AR5312_ENET0 0x18100000
+#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
+#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
+
-+
+/* AR5312_ENABLE register bit field definitions */
+#define AR5312_ENABLE_WLAN0 0x0001
+#define AR5312_ENABLE_ENET0 0x0002
+#define FLASHCTL_WP 0x04000000 /* Write protect */
+#define FLASHCTL_BM 0x08000000 /* Burst mode */
+#define FLASHCTL_MW 0x30000000 /* Memory width */
-+#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
-+#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
-+#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
++#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
++#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
++#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
+#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
+#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
+#define AR5312_NUM_GPIO 8
+
-+
+#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
-+
--- /dev/null
+++ b/arch/mips/ar231x/ar5312.c
-@@ -0,0 +1,540 @@
+@@ -0,0 +1,534 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ do_IRQ(AR231X_IRQ_CPU_CLOCK);
+}
+
-+
+/* Enable the specified AR5312_MISC_IRQ interrupt */
+static void
+ar5312_misc_irq_unmask(struct irq_data *d)
+ .irq_mask = ar5312_misc_irq_mask,
+};
+
-+
+static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
+{
+ u32 proc1 = ar231x_read_reg(AR5312_PROC1);
+ u32 dma1 = ar231x_read_reg(AR5312_DMA1);
+ u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
+
-+ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
-+ "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
-+ dma1);
++ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
++ proc_addr, proc1, dma_addr, dma1);
+
+ machine_restart("AHB error"); /* Catastrophic failure */
+ return IRQ_HANDLED;
+}
+
-+
+static struct irqaction ar5312_ahb_proc_interrupt = {
+ .handler = ar5312_ahb_proc_handler,
+ .name = "ar5312_ahb_proc_interrupt",
+};
+
-+
+void __init ar5312_irq_init(void)
+{
+ int i;
+ ar231x_irq_dispatch = ar5312_irq_dispatch;
+ for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
+ int irq = AR231X_MISC_IRQ_BASE + i;
++
+ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
+ handle_level_irq);
+ }
+ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
+ u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
++
+ reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
+ ar231x_write_reg(AR5312_GPIO_DO, reg);
+}
+ /* fixup flash width */
+ fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
+ switch (fctl) {
-+ case FLASHCTL_MWx16:
++ case FLASHCTL_MW16:
+ ar5312_flash_data.width = 2;
+ break;
-+ case FLASHCTL_MWx8:
++ case FLASHCTL_MW8:
+ default:
+ ar5312_flash_data.width = 1;
+ break;
+#endif
+
+ /* Fix up MAC addresses if necessary */
-+ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
-+ memcpy(config->enet0_mac, config->enet1_mac, 6);
++ if (is_broadcast_ether_addr(config->enet0_mac))
++ ether_addr_copy(config->enet0_mac, config->enet1_mac);
+
+ /* If ENET0 and ENET1 have the same mac address,
+ * increment the one from ENET1 */
-+ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
++ if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
+ c = config->enet1_mac + 5;
+ while ((c >= config->enet1_mac) && !(++(*c)))
+ c--;
+ return 0;
+}
+
-+
+static void ar5312_restart(char *command)
+{
+ /* reset the system */
+ ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
+}
+
-+
+/*
+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
+ * to determine the predevisor value.
+ */
+static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
+
-+
+static int __init
+ar5312_cpu_frequency(void)
+{
+static int __init
+ar5312_gpio_init(void)
+{
-+ int ret;
-+ ret = gpiochip_add(&ar5312_gpio_chip);
++ int ret = gpiochip_add(&ar5312_gpio_chip);
++
+ if (ret) {
+ pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
+ return ret;
+ devid = ar231x_read_reg(AR5312_REV);
+ devid >>= AR5312_REV_WMAC_MIN_S;
+ devid &= AR5312_REV_CHIP;
-+ ar231x_board.devid = (u16) devid;
++ ar231x_board.devid = (u16)devid;
+ ar5312_gpio_init();
+}
+
+ gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
+ for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
+ int irq = AR231X_MISC_IRQ_BASE + i;
++
+ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
-+ handle_level_irq);
++ handle_level_irq);
+ }
+ for (i = 0; i < AR2315_NUM_GPIO; i++) {
+ int irq = AR231X_GPIO_IRQ_BASE + i;
++
+ irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
-+ handle_level_irq);
++ handle_level_irq);
+ }
+ irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
+ setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
+ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
+ u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
++
+ reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
+ ar231x_write_reg(AR2315_GPIO_DO, reg);
+}
+ mips_reset_vec();
+}
+
-+
+/*
+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
+ * to determine the predevisor value.
+static int __init
+ar2315_gpio_init(void)
+{
-+ int ret;
-+ ret = gpiochip_add(&ar2315_gpio_chip);
++ int ret = gpiochip_add(&ar2315_gpio_chip);
++
+ if (ret) {
+ pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
+ return ret;
+ return ret;
+}
+
-+
-+
+void __init
+ar2315_prom_init(void)
+{
+#endif
--- /dev/null
+++ b/arch/mips/ar231x/devices.c
-@@ -0,0 +1,182 @@
+@@ -0,0 +1,180 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+ }
+};
+
-+
+static struct platform_device ar231x_wmac[] = {
+ {
+ .id = 0,
+const char *get_system_type(void)
+{
+ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
-+ !devtype_strings[ar231x_devtype])
++ !devtype_strings[ar231x_devtype])
+ return devtype_strings[DEV_TYPE_UNKNOWN];
+ return devtype_strings[ar231x_devtype];
+}
+
-+
+int __init
+ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
+ int irq, void *pdata)
projects / openwrt / openwrt.git / blobdiff