---- a/arch/mips/ar231x/Makefile
-+++ b/arch/mips/ar231x/Makefile
-@@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
+ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
+ ops-bcm63xx.o
+ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
++obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
+ obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
+ obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
- obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
- obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
-+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
--- /dev/null
-+++ b/arch/mips/ar231x/pci.c
-@@ -0,0 +1,233 @@
++++ b/arch/mips/pci/pci-ar2315.c
+@@ -0,0 +1,345 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
++/**
++ * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
++ * and interrupt. PCI interface supports MMIO access method, but does not
++ * seem to support I/O ports.
++ *
++ * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
++ * a memory read/write command on the PCI bus. 30 LSBs of address on
++ * the bus are taken from memory read/write request and 2 MSBs are
++ * determined by PCI unit configuration.
++ *
++ * To work with the configuration space instead of memory is necessary set
++ * the CFG_SEL bit in the PCI_MISC_CONFIG register.
++ *
++ * Devices on the bus can perform DMA requests via chip BAR1. PCI host
++ * controller BARs are programmend as if an external device is programmed.
++ * Which means that during configuration, IDSEL pin of the chip should be
++ * asserted.
++ *
++ * We know (and support) only one board that uses the PCI interface -
++ * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
++ * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
++ * and IDSEL pin of AR125 is connected to AD[16] line.
++ */
++
+#include <linux/types.h>
+#include <linux/pci.h>
++#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
-+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <ar231x_platform.h>
+#include <ar231x.h>
+#include <ar2315_regs.h>
-+#include "devices.h"
+
-+#define AR2315_MEM_BASE 0x80800000UL
-+#define AR2315_MEM_SIZE 0x00ffffffUL
-+#define AR2315_IO_SIZE 0x00007fffUL
++/* Arbitrary size of memory region to access the configuration space */
++#define AR2315_PCI_CFG_SIZE 0x00100000
+
-+static unsigned long configspace;
++#define AR2315_PCI_HOST_SLOT 3
++#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
+
-+static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
++static void __iomem *ar2315_pci_cfg_mem;
++
++static int ar2315_pci_cfg_access(int devfn, int where, int size, u32 *ptr,
++ bool write)
+{
-+ unsigned long flags;
+ int func = PCI_FUNC(devfn);
+ int dev = PCI_SLOT(devfn);
-+ u32 value = 0;
-+ int err = 0;
-+ u32 addr;
++ u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
++ u32 mask = 0xffffffff >> 8 * (4 - size);
++ u32 sh = (where & 3) * 8;
++ u32 value, isr;
+
-+ if (((dev != 0) && (dev != 3)) || (func > 2))
++ /* Prevent access past the remapped area */
++ if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
++ /* Clear pending errors */
++ ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
+ /* Select Configuration access */
-+ local_irq_save(flags);
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
-+ mb();
+
-+ addr = (u32)configspace + (1 << (13 + dev)) + (func << 8) + where;
-+ if (size == 1)
-+ addr ^= 0x3;
-+ else if (size == 2)
-+ addr ^= 0x2;
++ mb(); /* PCI must see space change before we begin */
++
++ value = __raw_readl(ar2315_pci_cfg_mem + addr);
++
++ isr = ar231x_read_reg(AR2315_PCI_ISR);
++ if (isr & AR2315_PCI_INT_ABORT)
++ goto exit_err;
+
+ if (write) {
-+ value = *ptr;
-+ if (size == 1)
-+ err = put_dbe(value, (u8 *)addr);
-+ else if (size == 2)
-+ err = put_dbe(value, (u16 *)addr);
-+ else if (size == 4)
-+ err = put_dbe(value, (u32 *)addr);
++ value = (value & ~(mask << sh)) | *ptr << sh;
++ __raw_writel(value, ar2315_pci_cfg_mem + addr);
++ isr = ar231x_read_reg(AR2315_PCI_ISR);
++ if (isr & AR2315_PCI_INT_ABORT)
++ goto exit_err;
+ } else {
-+ if (size == 1)
-+ err = get_dbe(value, (u8 *)addr);
-+ else if (size == 2)
-+ err = get_dbe(value, (u16 *)addr);
-+ else if (size == 4)
-+ err = get_dbe(value, (u32 *)addr);
-+ if (err)
-+ *ptr = 0xffffffff;
-+ else
-+ *ptr = value;
++ *ptr = (value >> sh) & mask;
+ }
+
++ goto exit;
++
++exit_err:
++ ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
++ if (!write)
++ *ptr = 0xffffffff;
++
++exit:
+ /* Select Memory access */
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
-+ local_irq_restore(flags);
+
-+ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
++ return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
++ PCIBIOS_SUCCESSFUL;
+}
+
-+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
-+ int size, u32 *value)
++static inline int ar2315_pci_local_cfg_rd(unsigned devfn, int where, u32 *val)
+{
-+ return config_access(devfn, where, size, value, 0);
++ return ar2315_pci_cfg_access(devfn, where, sizeof(u32), val, false);
+}
+
-+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
-+ int size, u32 value)
++static inline int ar2315_pci_local_cfg_wr(unsigned devfn, int where, u32 val)
+{
-+ return config_access(devfn, where, size, &value, 1);
++ return ar2315_pci_cfg_access(devfn, where, sizeof(u32), &val, true);
+}
+
-+static struct pci_ops ar231x_pci_ops = {
-+ .read = ar231x_pci_read,
-+ .write = ar231x_pci_write,
++static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 *value)
++{
++ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ return ar2315_pci_cfg_access(devfn, where, size, value, 0);
++}
++
++static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 value)
++{
++ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ return ar2315_pci_cfg_access(devfn, where, size, &value, 1);
++}
++
++static struct pci_ops ar2315_pci_ops = {
++ .read = ar2315_pci_cfg_read,
++ .write = ar2315_pci_cfg_write,
+};
+
-+static struct resource ar231x_mem_resource = {
-+ .name = "AR2315 PCI MEM",
-+ .start = AR2315_MEM_BASE,
-+ .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE - 1 +
-+ 0x4000000,
++static struct resource ar2315_mem_resource = {
++ .name = "ar2315-pci-mem",
++ .start = AR2315_PCIEXT,
++ .end = AR2315_PCIEXT + AR2315_PCIEXT_SZ - 1,
+ .flags = IORESOURCE_MEM,
+};
+
-+static struct resource ar231x_io_resource = {
-+ .name = "AR2315 PCI I/O",
-+ .start = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE,
-+ .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - 1,
++/* PCI controller does not support I/O ports */
++static struct resource ar2315_io_resource = {
++ .name = "ar2315-pci-io",
++ .start = 0,
++ .end = 0,
+ .flags = IORESOURCE_IO,
+};
+
-+static struct pci_controller ar231x_pci_controller = {
-+ .pci_ops = &ar231x_pci_ops,
-+ .mem_resource = &ar231x_mem_resource,
-+ .io_resource = &ar231x_io_resource,
++static struct pci_controller ar2315_pci_controller = {
++ .pci_ops = &ar2315_pci_ops,
++ .mem_resource = &ar2315_mem_resource,
++ .io_resource = &ar2315_io_resource,
+ .mem_offset = 0x00000000UL,
+ .io_offset = 0x00000000UL,
+};
+
-+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++static int ar2315_pci_host_setup(void)
++{
++ unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
++ int res;
++ u32 id;
++
++ res = ar2315_pci_local_cfg_rd(devfn, PCI_VENDOR_ID, &id);
++ if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
++ return -ENODEV;
++
++ /* Program MBARs */
++ ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_0,
++ AR2315_PCI_HOST_MBAR0);
++ ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_1,
++ AR2315_PCI_HOST_MBAR1);
++ ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_2,
++ AR2315_PCI_HOST_MBAR2);
++
++ /* Run */
++ ar2315_pci_local_cfg_wr(devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
++ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
++ PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
++
++ return 0;
++}
++
++static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
+{
-+ return AR2315_IRQ_LCBUS_PCI;
++ u32 pending = ar231x_read_reg(AR2315_PCI_ISR) &
++ ar231x_read_reg(AR2315_PCI_IMR);
++
++ if (pending & AR2315_PCI_INT_EXT)
++ generic_handle_irq(AR2315_PCI_IRQ_EXT);
++ else if (pending & AR2315_PCI_INT_ABORT)
++ generic_handle_irq(AR2315_PCI_IRQ_ABORT);
++ else
++ spurious_interrupt();
+}
+
-+int pcibios_plat_dev_init(struct pci_dev *dev)
++static void ar2315_pci_irq_mask(struct irq_data *d)
+{
-+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
-+ pci_write_config_word(dev, 0x40, 0);
++ u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
+
-+ /* Clear any pending Abort or external Interrupts
-+ * and enable interrupt processing */
-+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
-+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT |
-+ AR2315_PCI_EXT_INT));
-+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT |
-+ AR2315_PCI_EXT_INT));
-+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
++ ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
++}
+
-+ return 0;
++static void ar2315_pci_irq_mask_ack(struct irq_data *d)
++{
++ u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
++
++ ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
++ ar231x_write_reg(AR2315_PCI_ISR, m);
+}
+
-+static void
-+ar2315_pci_fixup(struct pci_dev *dev)
++static void ar2315_pci_irq_unmask(struct irq_data *d)
+{
-+ unsigned int devfn = dev->devfn;
-+
-+ if (dev->bus->number != 0)
-+ return;
-+
-+ /* Only fix up the PCI host settings */
-+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
-+ return;
-+
-+ /* Fix up MBARs */
-+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
-+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
-+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
-+ pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
-+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
-+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
-+ PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
++ u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
++
++ ar231x_mask_reg(AR2315_PCI_IMR, 0, m);
+}
-+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
+
-+static int __init
-+ar2315_pci_init(void)
++static struct irq_chip ar2315_pci_irq_chip = {
++ .name = "AR2315-PCI",
++ .irq_mask = ar2315_pci_irq_mask,
++ .irq_mask_ack = ar2315_pci_irq_mask_ack,
++ .irq_unmask = ar2315_pci_irq_unmask,
++};
++
++static void ar2315_pci_irq_init(void)
+{
-+ u32 reg;
++ int i;
+
-+ if (ar231x_devtype != DEV_TYPE_AR2315)
-+ return -ENODEV;
++ ar231x_mask_reg(AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
++ ar231x_mask_reg(AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
++ AR2315_PCI_INT_EXT), 0);
++
++ for (i = 0; i < AR2315_PCI_IRQ_COUNT; ++i) {
++ int irq = AR2315_PCI_IRQ_BASE + i;
++
++ irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip,
++ handle_level_irq);
++ }
++
++ irq_set_chained_handler(AR2315_IRQ_LCBUS_PCI, ar2315_pci_irq_handler);
++
++ /* Clear any pending Abort or external Interrupts
++ * and enable interrupt processing */
++ ar231x_write_reg(AR2315_PCI_ISR, (AR2315_PCI_INT_ABORT |
++ AR2315_PCI_INT_EXT));
++ ar231x_mask_reg(AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
++}
++
++static int ar2315_pci_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ u32 reg;
++ int res;
+
+ /* Remap PCI config space */
-+ configspace = (unsigned long)ioremap_nocache(AR2315_PCIEXT,
-+ 1 * 1024 * 1024);
-+ ar231x_pci_controller.io_map_base =
-+ (unsigned long)ioremap_nocache(AR2315_MEM_BASE +
-+ AR2315_MEM_SIZE, AR2315_IO_SIZE);
-+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/
++ ar2315_pci_cfg_mem = devm_ioremap_nocache(dev, AR2315_PCIEXT,
++ AR2315_PCI_CFG_SIZE);
++ if (!ar2315_pci_cfg_mem) {
++ dev_err(dev, "failed to remap PCI config space\n");
++ return -ENOMEM;
++ }
+
++ /* Reset PCI DMA logic */
+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
+ msleep(20);
-+
+ reg &= ~AR2315_RESET_PCIDMA;
+ ar231x_write_reg(AR2315_RESET, reg);
+ msleep(20);
+
+ msleep(500);
+
-+ /* dirty hack - anyone with a datasheet that knows the memory map ? */
-+ ioport_resource.start = 0x10000000;
-+ ioport_resource.end = 0xffffffff;
++ res = ar2315_pci_host_setup();
++ if (res)
++ return res;
++
++ ar2315_pci_irq_init();
+
-+ register_pci_controller(&ar231x_pci_controller);
++ register_pci_controller(&ar2315_pci_controller);
+
+ return 0;
+}
+
-+arch_initcall(ar2315_pci_init);
---- a/arch/mips/ar231x/Kconfig
-+++ b/arch/mips/ar231x/Kconfig
-@@ -14,3 +14,10 @@ config ATHEROS_AR2315
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- default y
++static struct platform_driver ar2315_pci_driver = {
++ .probe = ar2315_pci_probe,
++ .driver = {
++ .name = "ar2315-pci",
++ .owner = THIS_MODULE,
++ },
++};
+
-+config ATHEROS_AR2315_PCI
-+ bool "PCI support"
-+ depends on ATHEROS_AR2315
-+ select HW_HAS_PCI
-+ select PCI
-+ default y
---- a/arch/mips/ar231x/ar2315.c
-+++ b/arch/mips/ar231x/ar2315.c
-@@ -87,6 +87,28 @@ static void ar2315_misc_irq_handler(unsi
- do_IRQ(AR2315_MISC_IRQ_NONE);
- }
-
-+#ifdef CONFIG_ATHEROS_AR2315_PCI
-+static inline void pci_abort_irq(void)
++static int __init ar2315_pci_init(void)
+{
-+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
++ return platform_driver_register(&ar2315_pci_driver);
+}
++arch_initcall(ar2315_pci_init);
+
-+static inline void pci_ack_irq(void)
++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
-+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
++ return AR2315_PCI_IRQ_EXT;
+}
+
-+static void ar2315_pci_irq(int irq)
++int pcibios_plat_dev_init(struct pci_dev *dev)
+{
-+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
-+ pci_abort_irq();
-+ else {
-+ do_IRQ(irq);
-+ pci_ack_irq();
-+ }
++ return 0;
+}
-+#endif /* CONFIG_ATHEROS_AR2315_PCI */
+--- a/arch/mips/ar231x/Kconfig
++++ b/arch/mips/ar231x/Kconfig
+@@ -8,3 +8,10 @@ config SOC_AR2315
+ bool "Atheros 2315+ support"
+ depends on ATHEROS_AR231X
+ default y
+
- /*
- * Called when an interrupt is received, this function
- * determines exactly which interrupt it was, and it
-@@ -104,6 +126,10 @@ ar2315_irq_dispatch(void)
++config PCI_AR2315
++ bool "AR2315 PCI controller support"
++ depends on SOC_AR2315
++ select HW_HAS_PCI
++ select PCI
++ default y
+--- a/arch/mips/ar231x/ar2315.c
++++ b/arch/mips/ar231x/ar2315.c
+@@ -104,6 +104,10 @@ ar2315_irq_dispatch(void)
do_IRQ(AR2315_IRQ_WLAN0_INTRS);
else if (pending & CAUSEF_IP4)
do_IRQ(AR2315_IRQ_ENET0_INTRS);
-+#ifdef CONFIG_ATHEROS_AR2315_PCI
++#ifdef CONFIG_PCI_AR2315
+ else if (pending & CAUSEF_IP5)
-+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
++ do_IRQ(AR2315_IRQ_LCBUS_PCI);
+#endif
else if (pending & CAUSEF_IP2)
do_IRQ(AR2315_IRQ_MISC_INTRS);
else if (pending & CAUSEF_IP7)
+@@ -568,3 +572,18 @@ ar2315_plat_setup(void)
+ ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
+ ar2315_apb_frequency());
+ }
++
++#ifdef CONFIG_PCI_AR2315
++static int __init ar2315_pci_init(void)
++{
++ struct platform_device *pdev;
++
++ if (!is_2315() || ar231x_devtype != DEV_TYPE_AR2315)
++ return -ENODEV;
++
++ pdev = platform_device_register_simple("ar2315-pci", -1, NULL, 0);
++
++ return pdev ? 0 : -ENODEV;
++}
++arch_initcall(ar2315_pci_init);
++#endif
projects / openwrt / openwrt.git / blobdiff