if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -952,6 +964,8 @@ static void local_r4k_flush_cache_sigtra
+@@ -957,6 +969,8 @@ static void local_r4k_flush_cache_sigtra
}
R4600_HIT_CACHEOP_WAR_IMPL;
if (!cpu_has_ic_fills_f_dc) {
if (dc_lsize)
vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
-@@ -1840,6 +1854,17 @@ static void coherency_setup(void)
+@@ -1845,6 +1859,17 @@ static void coherency_setup(void)
* silly idea of putting something else there ...
*/
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
-@@ -1886,6 +1911,15 @@ void r4k_cache_init(void)
+@@ -1891,6 +1916,15 @@ void r4k_cache_init(void)
extern void build_copy_page(void);
struct cpuinfo_mips *c = ¤t_cpu_data;
probe_pcache();
probe_vcache();
setup_scache();
-@@ -1963,7 +1997,15 @@ void r4k_cache_init(void)
+@@ -1968,7 +2002,15 @@ void r4k_cache_init(void)
*/
local_r4k___flush_cache_all(NULL);
/*
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
-@@ -968,6 +968,9 @@ build_get_pgde32(u32 **p, unsigned int t
+@@ -980,6 +980,9 @@ build_get_pgde32(u32 **p, unsigned int t
uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
uasm_i_addu(p, ptr, tmp, ptr);
#else
UASM_i_LA_mostly(p, ptr, pgdc);
#endif
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
-@@ -1310,6 +1313,9 @@ static void build_r4000_tlb_refill_handl
+@@ -1323,6 +1326,9 @@ static void build_r4000_tlb_refill_handl
#ifdef CONFIG_64BIT
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
#else
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
#endif
-@@ -1321,6 +1327,9 @@ static void build_r4000_tlb_refill_handl
+@@ -1334,6 +1340,9 @@ static void build_r4000_tlb_refill_handl
build_update_entries(&p, K0, K1);
build_tlb_write_entry(&p, &l, &r, tlb_random);
uasm_l_leave(&l, p);
uasm_i_eret(&p); /* return from trap */
}
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
-@@ -2003,6 +2012,9 @@ build_r4000_tlbchange_handler_head(u32 *
+@@ -2021,6 +2030,9 @@ build_r4000_tlbchange_handler_head(u32 *
#ifdef CONFIG_64BIT
build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
#else
build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
#endif
-@@ -2049,6 +2061,9 @@ build_r4000_tlbchange_handler_tail(u32 *
+@@ -2067,6 +2079,9 @@ build_r4000_tlbchange_handler_tail(u32 *
build_tlb_write_entry(p, l, r, tlb_indexed);
uasm_l_leave(l, *p);
build_restore_work_registers(p);