return ret;
}
+void
+ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
+ u16 dbg_addr, u16 *dbg_data)
+{
+ struct mii_bus *bus = priv->mii_bus;
+
+ mutex_lock(&bus->mdio_lock);
+ bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
+ *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
+ mutex_unlock(&bus->mdio_lock);
+}
void
ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
return 0;
usleep_range(1000, 2000);
+ cond_resched();
}
return -ETIMEDOUT;
mib_stats[i] = 0;
else
mib_stats[i] += t;
+ cond_resched();
}
}
break;
udelay(10);
+ cond_resched();
}
pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
{
int timeout = 20;
- while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
- udelay(10);
+ while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
+ udelay(10);
+ cond_resched();
+ }
if (!timeout)
pr_err("ar8216: timeout waiting for atu to become ready\n");
u16 r2, page;
u16 r1_func0, r1_func1, r1_func2;
u32 t, val0, val1, val2;
- int i;
split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
r2 |= 0x10;
if (!*status)
break;
- i = 0;
- t = AR8216_ATU_PORT0;
- while (!(val2 & t) && ++i < priv->dev.ports)
- t <<= 1;
-
- a->port = i;
+ a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
chip->init_globals(priv);
+ chip->atu_flush(priv);
mutex_unlock(&priv->reg_mutex);
*/
for (j = 0; j < i; ++j) {
a1 = &priv->arl_table[j];
- if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
- goto duplicate;
+ if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
+ /* ignore ports already seen in former entry */
+ a->portmap &= ~a1->portmap;
+ if (!a->portmap)
+ goto duplicate;
+ }
}
}
for (j = 0; j < priv->dev.ports; ++j) {
for (k = 0; k < i; ++k) {
a = &priv->arl_table[k];
- if (a->port != j)
+ if (!(a->portmap & BIT(j)))
continue;
len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
"Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
.apply_config = ar8xxx_sw_hw_apply,
.reset_switch = ar8xxx_sw_reset_switch,
.get_port_link = ar8xxx_sw_get_port_link,
+/* The following op is disabled as it hogs the CPU and degrades performance.
+ An implementation has been attempted in 4d8a66d but reading MIB data is slow
+ on ar8xxx switches.
+
+ The high CPU load has been traced down to the ar8xxx_reg_wait() call in
+ ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
+ the request to update the MIB counter is cleared. */
+#if 0
+ .get_port_stats = ar8xxx_sw_get_port_stats,
+#endif
};
static const struct ar8xxx_chip ar8216_chip = {
};
static int
-ar8xxx_id_chip(struct ar8xxx_priv *priv)
+ar8xxx_read_id(struct ar8xxx_priv *priv)
{
u32 val;
u16 id;
priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
priv->chip_rev = (id & AR8216_CTRL_REVISION);
+ return 0;
+}
+
+static int
+ar8xxx_id_chip(struct ar8xxx_priv *priv)
+{
+ int ret;
+
+ ret = ar8xxx_read_id(priv);
+ if(ret)
+ return ret;
switch (priv->chip_ver) {
case AR8XXX_VER_AR8216:
phydev->state = PHY_RUNNING;
netif_carrier_on(phydev->attached_dev);
- phydev->adjust_link(phydev->attached_dev);
+ if (phydev->adjust_link)
+ phydev->adjust_link(phydev->attached_dev);
return 0;
}
int ret;
/* skip PHYs at unused adresses */
- if (phydev->mdio.addr != 0 && phydev->mdio.addr != 4)
+ if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
return -ENODEV;
if (!ar8xxx_is_possible(phydev->mdio.bus))
phydev->supported |= SUPPORTED_1000baseT_Full;
phydev->advertising |= ADVERTISED_1000baseT_Full;
}
+ if (priv->chip->phy_rgmii_set)
+ priv->chip->phy_rgmii_set(priv, phydev);
}
phydev->priv = priv;