#include <linux/lockdep.h>
#include <linux/ar8216_platform.h>
#include <linux/workqueue.h>
+#include <linux/version.h>
+
#include "ar8216.h"
-/* size of the vlan table */
-#define AR8X16_MAX_VLANS 128
-#define AR8X16_PROBE_RETRIES 10
-#define AR8X16_MAX_PORTS 8
+extern const struct ar8xxx_chip ar8327_chip;
+extern const struct ar8xxx_chip ar8337_chip;
#define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
-struct ar8216_priv;
-
-#define AR8XXX_CAP_GIGE BIT(0)
-#define AR8XXX_CAP_MIB_COUNTERS BIT(1)
-
-enum {
- AR8XXX_VER_AR8216 = 0x01,
- AR8XXX_VER_AR8236 = 0x03,
- AR8XXX_VER_AR8316 = 0x10,
- AR8XXX_VER_AR8327 = 0x12,
-};
-
-struct ar8xxx_mib_desc {
- unsigned int size;
- unsigned int offset;
- const char *name;
-};
-
-struct ar8xxx_chip {
- unsigned long caps;
-
- int (*hw_init)(struct ar8216_priv *priv);
- void (*init_globals)(struct ar8216_priv *priv);
- void (*init_port)(struct ar8216_priv *priv, int port);
- void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
- u32 ingress, u32 members, u32 pvid);
- u32 (*read_port_status)(struct ar8216_priv *priv, int port);
- int (*atu_flush)(struct ar8216_priv *priv);
- void (*vtu_flush)(struct ar8216_priv *priv);
- void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
-
- const struct ar8xxx_mib_desc *mib_decs;
- unsigned num_mibs;
-};
-
-struct ar8216_priv {
- struct switch_dev dev;
- struct phy_device *phy;
- u32 (*read)(struct ar8216_priv *priv, int reg);
- void (*write)(struct ar8216_priv *priv, int reg, u32 val);
- const struct net_device_ops *ndo_old;
- struct net_device_ops ndo;
- struct mutex reg_mutex;
- u8 chip_ver;
- u8 chip_rev;
- const struct ar8xxx_chip *chip;
- bool initialized;
- bool port4_phy;
- char buf[2048];
-
- bool init;
- bool mii_lo_first;
-
- struct mutex mib_lock;
- struct delayed_work mib_work;
- int mib_next_port;
- u64 *mib_stats;
-
- /* all fields below are cleared on reset */
- bool vlan;
- u16 vlan_id[AR8X16_MAX_VLANS];
- u8 vlan_table[AR8X16_MAX_VLANS];
- u8 vlan_tagged;
- u16 pvid[AR8X16_MAX_PORTS];
-};
-
#define MIB_DESC(_s , _o, _n) \
{ \
.size = (_s), \
MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
};
-static const struct ar8xxx_mib_desc ar8236_mibs[] = {
+const struct ar8xxx_mib_desc ar8236_mibs[39] = {
MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
};
-#define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
+static DEFINE_MUTEX(ar8xxx_dev_list_lock);
+static LIST_HEAD(ar8xxx_dev_list);
-static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
-{
- return priv->chip->caps & AR8XXX_CAP_GIGE;
+/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
+static int
+ar8xxx_phy_poll_reset(struct mii_bus *bus)
+{
+ unsigned int sleep_msecs = 20;
+ int ret, elapsed, i;
+
+ for (elapsed = sleep_msecs; elapsed <= 600;
+ elapsed += sleep_msecs) {
+ msleep(sleep_msecs);
+ for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
+ ret = mdiobus_read(bus, i, MII_BMCR);
+ if (ret < 0)
+ return ret;
+ if (ret & BMCR_RESET)
+ break;
+ if (i == AR8XXX_NUM_PHYS - 1) {
+ usleep_range(1000, 2000);
+ return 0;
+ }
+ }
+ }
+ return -ETIMEDOUT;
}
-static inline bool ar8xxx_has_mib_counters(struct ar8216_priv *priv)
+static int
+ar8xxx_phy_check_aneg(struct phy_device *phydev)
{
- return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
-}
+ int ret;
-static inline bool chip_is_ar8216(struct ar8216_priv *priv)
-{
- return priv->chip_ver == AR8XXX_VER_AR8216;
+ if (phydev->autoneg != AUTONEG_ENABLE)
+ return 0;
+ /*
+ * BMCR_ANENABLE might have been cleared
+ * by phy_init_hw in certain kernel versions
+ * therefore check for it
+ */
+ ret = phy_read(phydev, MII_BMCR);
+ if (ret < 0)
+ return ret;
+ if (ret & BMCR_ANENABLE)
+ return 0;
+
+ dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
+ ret |= BMCR_ANENABLE | BMCR_ANRESTART;
+ return phy_write(phydev, MII_BMCR, ret);
}
-static inline bool chip_is_ar8236(struct ar8216_priv *priv)
+void
+ar8xxx_phy_init(struct ar8xxx_priv *priv)
{
- return priv->chip_ver == AR8XXX_VER_AR8236;
+ int i;
+ struct mii_bus *bus;
+
+ bus = priv->mii_bus;
+ for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
+ if (priv->chip->phy_fixup)
+ priv->chip->phy_fixup(priv, i);
+
+ /* initialize the port itself */
+ mdiobus_write(bus, i, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
+ if (ar8xxx_has_gige(priv))
+ mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ }
+
+ ar8xxx_phy_poll_reset(bus);
}
-static inline bool chip_is_ar8316(struct ar8216_priv *priv)
+u32
+ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
{
- return priv->chip_ver == AR8XXX_VER_AR8316;
+ struct mii_bus *bus = priv->mii_bus;
+ u16 lo, hi;
+
+ lo = bus->read(bus, phy_id, regnum);
+ hi = bus->read(bus, phy_id, regnum + 1);
+
+ return (hi << 16) | lo;
}
-static inline bool chip_is_ar8327(struct ar8216_priv *priv)
+void
+ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
{
- return priv->chip_ver == AR8XXX_VER_AR8327;
+ struct mii_bus *bus = priv->mii_bus;
+ u16 lo, hi;
+
+ lo = val & 0xffff;
+ hi = (u16) (val >> 16);
+
+ if (priv->chip->mii_lo_first)
+ {
+ bus->write(bus, phy_id, regnum, lo);
+ bus->write(bus, phy_id, regnum + 1, hi);
+ } else {
+ bus->write(bus, phy_id, regnum + 1, hi);
+ bus->write(bus, phy_id, regnum, lo);
+ }
}
-static inline void
-split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
+u32
+ar8xxx_read(struct ar8xxx_priv *priv, int reg)
{
- regaddr >>= 1;
- *r1 = regaddr & 0x1e;
+ struct mii_bus *bus = priv->mii_bus;
+ u16 r1, r2, page;
+ u32 val;
+
+ split_addr((u32) reg, &r1, &r2, &page);
+
+ mutex_lock(&bus->mdio_lock);
+
+ bus->write(bus, 0x18, 0, page);
+ wait_for_page_switch();
+ val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
- regaddr >>= 5;
- *r2 = regaddr & 0x7;
+ mutex_unlock(&bus->mdio_lock);
- regaddr >>= 3;
- *page = regaddr & 0x1ff;
+ return val;
}
-static u32
-ar8216_mii_read(struct ar8216_priv *priv, int reg)
+void
+ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
{
- struct phy_device *phy = priv->phy;
- struct mii_bus *bus = phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, page;
- u16 lo, hi;
split_addr((u32) reg, &r1, &r2, &page);
mutex_lock(&bus->mdio_lock);
bus->write(bus, 0x18, 0, page);
- usleep_range(1000, 2000); /* wait for the page switch to propagate */
- lo = bus->read(bus, 0x10 | r2, r1);
- hi = bus->read(bus, 0x10 | r2, r1 + 1);
+ wait_for_page_switch();
+ ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
mutex_unlock(&bus->mdio_lock);
-
- return (hi << 16) | lo;
}
-static void
-ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
+u32
+ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
{
- struct phy_device *phy = priv->phy;
- struct mii_bus *bus = phy->bus;
- u16 r1, r2, r3;
- u16 lo, hi;
+ struct mii_bus *bus = priv->mii_bus;
+ u16 r1, r2, page;
+ u32 ret;
- split_addr((u32) reg, &r1, &r2, &r3);
- lo = val & 0xffff;
- hi = (u16) (val >> 16);
+ split_addr((u32) reg, &r1, &r2, &page);
mutex_lock(&bus->mdio_lock);
- bus->write(bus, 0x18, 0, r3);
- usleep_range(1000, 2000); /* wait for the page switch to propagate */
- if (priv->mii_lo_first) {
- bus->write(bus, 0x10 | r2, r1, lo);
- bus->write(bus, 0x10 | r2, r1 + 1, hi);
- } else {
- bus->write(bus, 0x10 | r2, r1 + 1, hi);
- bus->write(bus, 0x10 | r2, r1, lo);
- }
+ bus->write(bus, 0x18, 0, page);
+ wait_for_page_switch();
+
+ ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
+ ret &= ~mask;
+ ret |= val;
+ ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
mutex_unlock(&bus->mdio_lock);
+
+ return ret;
}
-static void
-ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
+void
+ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
u16 dbg_addr, u16 dbg_data)
{
- struct mii_bus *bus = priv->phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
mutex_lock(&bus->mdio_lock);
bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
mutex_unlock(&bus->mdio_lock);
}
-static void
-ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
+void
+ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
{
- struct mii_bus *bus = priv->phy->bus;
+ struct mii_bus *bus = priv->mii_bus;
mutex_lock(&bus->mdio_lock);
bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
mutex_unlock(&bus->mdio_lock);
}
-static u32
-ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
-{
- u32 v;
-
- lockdep_assert_held(&priv->reg_mutex);
-
- v = priv->read(priv, reg);
- v &= ~mask;
- v |= val;
- priv->write(priv, reg, v);
-
- return v;
-}
-
-static inline void
-ar8216_reg_set(struct ar8216_priv *priv, int reg, u32 val)
+u16
+ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr)
{
- u32 v;
+ struct mii_bus *bus = priv->mii_bus;
+ u16 data;
- lockdep_assert_held(&priv->reg_mutex);
+ mutex_lock(&bus->mdio_lock);
+ bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
+ data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
+ mutex_unlock(&bus->mdio_lock);
- v = priv->read(priv, reg);
- v |= val;
- priv->write(priv, reg, v);
+ return data;
}
static int
-ar8216_reg_wait(struct ar8216_priv *priv, u32 reg, u32 mask, u32 val,
+ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
unsigned timeout)
{
int i;
for (i = 0; i < timeout; i++) {
u32 t;
- t = priv->read(priv, reg);
+ t = ar8xxx_read(priv, reg);
if ((t & mask) == val)
return 0;
}
static int
-ar8216_mib_op(struct ar8216_priv *priv, u32 op)
+ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
{
- unsigned mib_func;
+ unsigned mib_func = priv->chip->mib_func;
int ret;
lockdep_assert_held(&priv->mib_lock);
- if (chip_is_ar8327(priv))
- mib_func = AR8327_REG_MIB_FUNC;
- else
- mib_func = AR8216_REG_MIB_FUNC;
-
- mutex_lock(&priv->reg_mutex);
/* Capture the hardware statistics for all ports */
- ar8216_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
- mutex_unlock(&priv->reg_mutex);
+ ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
/* Wait for the capturing to complete. */
- ret = ar8216_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
+ ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
if (ret)
goto out;
}
static int
-ar8216_mib_capture(struct ar8216_priv *priv)
+ar8xxx_mib_capture(struct ar8xxx_priv *priv)
{
- return ar8216_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
+ return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
}
static int
-ar8216_mib_flush(struct ar8216_priv *priv)
+ar8xxx_mib_flush(struct ar8xxx_priv *priv)
{
- return ar8216_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
+ return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
}
static void
-ar8216_mib_fetch_port_stat(struct ar8216_priv *priv, int port, bool flush)
+ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
{
unsigned int base;
u64 *mib_stats;
lockdep_assert_held(&priv->mib_lock);
- if (chip_is_ar8327(priv))
- base = AR8327_REG_PORT_STATS_BASE(port);
- else if (chip_is_ar8236(priv) ||
- chip_is_ar8316(priv))
- base = AR8236_REG_PORT_STATS_BASE(port);
- else
- base = AR8216_REG_PORT_STATS_BASE(port);
+ base = priv->chip->reg_port_stats_start +
+ priv->chip->reg_port_stats_length * port;
mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
for (i = 0; i < priv->chip->num_mibs; i++) {
u64 t;
mib = &priv->chip->mib_decs[i];
- t = priv->read(priv, base + mib->offset);
+ t = ar8xxx_read(priv, base + mib->offset);
if (mib->size == 2) {
u64 hi;
- hi = priv->read(priv, base + mib->offset + 4);
+ hi = ar8xxx_read(priv, base + mib->offset + 4);
t |= hi << 32;
}
}
static void
-ar8216_read_port_link(struct ar8216_priv *priv, int port,
+ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
struct switch_port_link *link)
{
u32 status;
link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
if (link->aneg) {
link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
- if (!link->link)
- return;
} else {
link->link = true;
+
+ if (priv->get_port_link) {
+ int err;
+
+ err = priv->get_port_link(port);
+ if (err >= 0)
+ link->link = !!err;
+ }
}
+ if (!link->link)
+ return;
+
link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
+ if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
+ link->eee = priv->chip->read_port_eee_status(priv, port);
+
speed = (status & AR8216_PORT_STATUS_SPEED) >>
AR8216_PORT_STATUS_SPEED_S;
static struct sk_buff *
ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
{
- struct ar8216_priv *priv = dev->phy_ptr;
+ struct ar8xxx_priv *priv = dev->phy_ptr;
unsigned char *buf;
if (unlikely(!priv))
static void
ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
{
- struct ar8216_priv *priv;
+ struct ar8xxx_priv *priv;
unsigned char *buf;
int port, vlan;
buf[15 + 2] = vlan & 0xff;
}
-static int
-ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
+int
+ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
{
int timeout = 20;
u32 t = 0;
while (1) {
- t = priv->read(priv, reg);
+ t = ar8xxx_read(priv, reg);
if ((t & mask) == val)
return 0;
}
static void
-ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
+ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
{
if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
return;
if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
val &= AR8216_VTUDATA_MEMBER;
val |= AR8216_VTUDATA_VALID;
- priv->write(priv, AR8216_REG_VTU_DATA, val);
+ ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
}
op |= AR8216_VTU_ACTIVE;
- priv->write(priv, AR8216_REG_VTU, op);
+ ar8xxx_write(priv, AR8216_REG_VTU, op);
}
static void
-ar8216_vtu_flush(struct ar8216_priv *priv)
+ar8216_vtu_flush(struct ar8xxx_priv *priv)
{
ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
}
static void
-ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
+ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
{
u32 op;
}
static int
-ar8216_atu_flush(struct ar8216_priv *priv)
+ar8216_atu_flush(struct ar8xxx_priv *priv)
{
int ret;
- ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
+ ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
if (!ret)
- priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
+ ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
+ AR8216_ATU_ACTIVE);
+
+ return ret;
+}
+
+static int
+ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
+{
+ u32 t;
+ int ret;
+
+ ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
+ if (!ret) {
+ t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
+ t |= AR8216_ATU_ACTIVE;
+ ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
+ }
return ret;
}
static u32
-ar8216_read_port_status(struct ar8216_priv *priv, int port)
+ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
{
- return priv->read(priv, AR8216_REG_PORT_STATUS(port));
+ return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
}
static void
-ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
- u32 members, u32 pvid)
+ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
{
u32 header;
+ u32 egress, ingress;
+ u32 pvid;
+
+ if (priv->vlan) {
+ pvid = priv->vlan_id[priv->pvid[port]];
+ if (priv->vlan_tagged & (1 << port))
+ egress = AR8216_OUT_ADD_VLAN;
+ else
+ egress = AR8216_OUT_STRIP_VLAN;
+ ingress = AR8216_IN_SECURE;
+ } else {
+ pvid = port;
+ egress = AR8216_OUT_KEEP;
+ ingress = AR8216_IN_PORT_ONLY;
+ }
if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
header = AR8216_PORT_CTRL_HEADER;
else
header = 0;
- ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
+ ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
(egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
(AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
- ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
+ ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
AR8216_PORT_VLAN_DEFAULT_ID,
(members << AR8216_PORT_VLAN_DEST_PORTS_S) |
}
static int
-ar8216_hw_init(struct ar8216_priv *priv)
+ar8216_hw_init(struct ar8xxx_priv *priv)
{
+ if (priv->initialized)
+ return 0;
+
+ ar8xxx_phy_init(priv);
+
+ priv->initialized = true;
return 0;
}
static void
-ar8216_init_globals(struct ar8216_priv *priv)
+ar8216_init_globals(struct ar8xxx_priv *priv)
{
/* standard atheros magic */
- priv->write(priv, 0x38, 0xc000050e);
+ ar8xxx_write(priv, 0x38, 0xc000050e);
- ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8216_GCTRL_MTU, 1518 + 8 + 2);
}
static void
-ar8216_init_port(struct ar8216_priv *priv, int port)
+ar8216_init_port(struct ar8xxx_priv *priv, int port)
{
/* Enable port learning and tx */
- priv->write(priv, AR8216_REG_PORT_CTRL(port),
+ ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
AR8216_PORT_CTRL_LEARN |
(4 << AR8216_PORT_CTRL_STATE_S));
- priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
+ ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
if (port == AR8216_PORT_CPU) {
- priv->write(priv, AR8216_REG_PORT_STATUS(port),
+ ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
AR8216_PORT_STATUS_LINK_UP |
(ar8xxx_has_gige(priv) ?
AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
(chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
AR8216_PORT_STATUS_DUPLEX);
} else {
- priv->write(priv, AR8216_REG_PORT_STATUS(port),
+ ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
AR8216_PORT_STATUS_LINK_AUTO);
}
}
-static const struct ar8xxx_chip ar8216_chip = {
- .caps = AR8XXX_CAP_MIB_COUNTERS,
+static void
+ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
+{
+ int timeout = 20;
- .hw_init = ar8216_hw_init,
- .init_globals = ar8216_init_globals,
- .init_port = ar8216_init_port,
- .setup_port = ar8216_setup_port,
- .read_port_status = ar8216_read_port_status,
- .atu_flush = ar8216_atu_flush,
- .vtu_flush = ar8216_vtu_flush,
- .vtu_load_vlan = ar8216_vtu_load_vlan,
+ while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
+ udelay(10);
- .num_mibs = ARRAY_SIZE(ar8216_mibs),
- .mib_decs = ar8216_mibs,
-};
+ if (!timeout)
+ pr_err("ar8216: timeout waiting for atu to become ready\n");
+}
+
+static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
+ struct arl_entry *a, u32 *status, enum arl_op op)
+{
+ struct mii_bus *bus = priv->mii_bus;
+ u16 r2, page;
+ u16 r1_func0, r1_func1, r1_func2;
+ u32 t, val0, val1, val2;
+ int i;
+
+ split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
+ r2 |= 0x10;
+
+ r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
+ r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
+
+ switch (op) {
+ case AR8XXX_ARL_INITIALIZE:
+ /* all ATU registers are on the same page
+ * therefore set page only once
+ */
+ bus->write(bus, 0x18, 0, page);
+ wait_for_page_switch();
+
+ ar8216_wait_atu_ready(priv, r2, r1_func0);
+
+ ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
+ ar8xxx_mii_write32(priv, r2, r1_func1, 0);
+ ar8xxx_mii_write32(priv, r2, r1_func2, 0);
+ break;
+ case AR8XXX_ARL_GET_NEXT:
+ t = ar8xxx_mii_read32(priv, r2, r1_func0);
+ t |= AR8216_ATU_ACTIVE;
+ ar8xxx_mii_write32(priv, r2, r1_func0, t);
+ ar8216_wait_atu_ready(priv, r2, r1_func0);
+
+ val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
+ val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
+ val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
+
+ *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
+ if (!*status)
+ break;
+
+ i = 0;
+ t = AR8216_ATU_PORT0;
+ while (!(val2 & t) && ++i < priv->dev.ports)
+ t <<= 1;
+
+ a->port = i;
+ a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
+ a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
+ a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
+ a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
+ a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
+ a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
+ break;
+ }
+}
static void
-ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
- u32 members, u32 pvid)
+ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
{
- ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
+ u32 egress, ingress;
+ u32 pvid;
+
+ if (priv->vlan) {
+ pvid = priv->vlan_id[priv->pvid[port]];
+ if (priv->vlan_tagged & (1 << port))
+ egress = AR8216_OUT_ADD_VLAN;
+ else
+ egress = AR8216_OUT_STRIP_VLAN;
+ ingress = AR8216_IN_SECURE;
+ } else {
+ pvid = port;
+ egress = AR8216_OUT_KEEP;
+ ingress = AR8216_IN_PORT_ONLY;
+ }
+
+ ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
(egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
(AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
- ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
+ ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
AR8236_PORT_VLAN_DEFAULT_ID,
(pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
- ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
+ ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
AR8236_PORT_VLAN2_VLAN_MODE |
AR8236_PORT_VLAN2_MEMBER,
(ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
(members << AR8236_PORT_VLAN2_MEMBER_S));
}
-static int
-ar8236_hw_init(struct ar8216_priv *priv)
-{
- int i;
- struct mii_bus *bus;
-
- if (priv->initialized)
- return 0;
-
- /* Initialize the PHYs */
- bus = priv->phy->bus;
- for (i = 0; i < 5; i++) {
- mdiobus_write(bus, i, MII_ADVERTISE,
- ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
- ADVERTISE_PAUSE_ASYM);
- mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- }
- msleep(1000);
-
- priv->initialized = true;
- return 0;
-}
-
static void
-ar8236_init_globals(struct ar8216_priv *priv)
+ar8236_init_globals(struct ar8xxx_priv *priv)
{
/* enable jumbo frames */
- ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8316_GCTRL_MTU, 9018 + 8 + 2);
+ /* enable cpu port to receive arp frames */
+ ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
+ AR8236_ATU_CTRL_RES);
+
+ /* enable cpu port to receive multicast and broadcast frames */
+ ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
+ AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
+
/* Enable MIB counters */
- ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
+ ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
(AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
AR8236_MIB_EN);
}
-static const struct ar8xxx_chip ar8236_chip = {
- .caps = AR8XXX_CAP_MIB_COUNTERS,
- .hw_init = ar8236_hw_init,
- .init_globals = ar8236_init_globals,
- .init_port = ar8216_init_port,
- .setup_port = ar8236_setup_port,
- .read_port_status = ar8216_read_port_status,
- .atu_flush = ar8216_atu_flush,
- .vtu_flush = ar8216_vtu_flush,
- .vtu_load_vlan = ar8216_vtu_load_vlan,
-
- .num_mibs = ARRAY_SIZE(ar8236_mibs),
- .mib_decs = ar8236_mibs,
-};
-
static int
-ar8316_hw_init(struct ar8216_priv *priv)
+ar8316_hw_init(struct ar8xxx_priv *priv)
{
- int i;
u32 val, newval;
- struct mii_bus *bus;
- val = priv->read(priv, 0x8);
+ val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
if (priv->port4_phy) {
/* value taken from Ubiquiti RouterStation Pro */
newval = 0x81461bea;
- printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
+ pr_info("ar8316: Using port 4 as PHY\n");
} else {
newval = 0x01261be2;
- printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
+ pr_info("ar8316: Using port 4 as switch port\n");
}
} else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
/* value taken from AVM Fritz!Box 7390 sources */
newval = 0x010e5b71;
} else {
/* no known value for phy interface */
- printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
- priv->phy->interface);
+ pr_err("ar8316: unsupported mii mode: %d.\n",
+ priv->phy->interface);
return -EINVAL;
}
if (val == newval)
goto out;
- priv->write(priv, 0x8, newval);
-
- /* Initialize the ports */
- bus = priv->phy->bus;
- for (i = 0; i < 5; i++) {
- if ((i == 4) && priv->port4_phy &&
- priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
- /* work around for phy4 rgmii mode */
- ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
- /* rx delay */
- ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
- /* tx delay */
- ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
- msleep(1000);
- }
+ ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
- /* initialize the port itself */
- mdiobus_write(bus, i, MII_ADVERTISE,
- ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
- mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
- mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ if (priv->port4_phy &&
+ priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
+ /* work around for phy4 rgmii mode */
+ ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
+ /* rx delay */
+ ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
+ /* tx delay */
+ ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
msleep(1000);
}
+ ar8xxx_phy_init(priv);
+
out:
priv->initialized = true;
return 0;
}
static void
-ar8316_init_globals(struct ar8216_priv *priv)
+ar8316_init_globals(struct ar8xxx_priv *priv)
{
/* standard atheros magic */
- priv->write(priv, 0x38, 0xc000050e);
+ ar8xxx_write(priv, 0x38, 0xc000050e);
/* enable cpu port to receive multicast and broadcast frames */
- priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
+ ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
/* enable jumbo frames */
- ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8316_GCTRL_MTU, 9018 + 8 + 2);
/* Enable MIB counters */
- ar8216_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
+ ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
(AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
AR8236_MIB_EN);
}
-static const struct ar8xxx_chip ar8316_chip = {
- .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
- .hw_init = ar8316_hw_init,
- .init_globals = ar8316_init_globals,
- .init_port = ar8216_init_port,
- .setup_port = ar8216_setup_port,
- .read_port_status = ar8216_read_port_status,
- .atu_flush = ar8216_atu_flush,
- .vtu_flush = ar8216_vtu_flush,
- .vtu_load_vlan = ar8216_vtu_load_vlan,
-
- .num_mibs = ARRAY_SIZE(ar8236_mibs),
- .mib_decs = ar8236_mibs,
-};
-
-static u32
-ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
+int
+ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
{
- u32 t;
-
- if (!cfg)
- return 0;
-
- t = 0;
- switch (cfg->mode) {
- case AR8327_PAD_NC:
- break;
-
- case AR8327_PAD_MAC2MAC_MII:
- t = AR8327_PAD_MAC_MII_EN;
- if (cfg->rxclk_sel)
- t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
- if (cfg->txclk_sel)
- t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
- break;
-
- case AR8327_PAD_MAC2MAC_GMII:
- t = AR8327_PAD_MAC_GMII_EN;
- if (cfg->rxclk_sel)
- t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
- if (cfg->txclk_sel)
- t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
- break;
-
- case AR8327_PAD_MAC_SGMII:
- t = AR8327_PAD_SGMII_EN;
-
- /*
- * WAR for the QUalcomm Atheros AP136 board.
- * It seems that RGMII TX/RX delay settings needs to be
- * applied for SGMII mode as well, The ethernet is not
- * reliable without this.
- */
- t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
- t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
- if (cfg->rxclk_delay_en)
- t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
- if (cfg->txclk_delay_en)
- t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
-
- break;
-
- case AR8327_PAD_MAC2PHY_MII:
- t = AR8327_PAD_PHY_MII_EN;
- if (cfg->rxclk_sel)
- t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
- if (cfg->txclk_sel)
- t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
- break;
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ priv->vlan = !!val->value.i;
+ return 0;
+}
- case AR8327_PAD_MAC2PHY_GMII:
- t = AR8327_PAD_PHY_GMII_EN;
- if (cfg->pipe_rxclk_sel)
- t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
- if (cfg->rxclk_sel)
- t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
- if (cfg->txclk_sel)
- t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
- break;
+int
+ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ val->value.i = priv->vlan;
+ return 0;
+}
- case AR8327_PAD_MAC_RGMII:
- t = AR8327_PAD_RGMII_EN;
- t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
- t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
- if (cfg->rxclk_delay_en)
- t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
- if (cfg->txclk_delay_en)
- t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
- break;
- case AR8327_PAD_PHY_GMII:
- t = AR8327_PAD_PHYX_GMII_EN;
- break;
+int
+ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
- case AR8327_PAD_PHY_RGMII:
- t = AR8327_PAD_PHYX_RGMII_EN;
- break;
+ /* make sure no invalid PVIDs get set */
- case AR8327_PAD_PHY_MII:
- t = AR8327_PAD_PHYX_MII_EN;
- break;
- }
+ if (vlan >= dev->vlans)
+ return -EINVAL;
- return t;
+ priv->pvid[port] = vlan;
+ return 0;
}
-static void
-ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
-{
- switch (priv->chip_rev) {
- case 1:
- /* For 100M waveform */
- ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
- /* Turn on Gigabit clock */
- ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
- break;
-
- case 2:
- ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
- ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
- /* fallthrough */
- case 4:
- ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
- ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
-
- ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
- ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
- ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
- break;
- }
+int
+ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ *vlan = priv->pvid[port];
+ return 0;
}
static int
-ar8327_hw_init(struct ar8216_priv *priv)
+ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
{
- struct ar8327_platform_data *pdata;
- struct ar8327_led_cfg *led_cfg;
- struct mii_bus *bus;
- u32 pos, new_pos;
- u32 t;
- int i;
-
- pdata = priv->phy->dev.platform_data;
- if (!pdata)
- return -EINVAL;
-
- t = ar8327_get_pad_cfg(pdata->pad0_cfg);
- priv->write(priv, AR8327_REG_PAD0_MODE, t);
- t = ar8327_get_pad_cfg(pdata->pad5_cfg);
- priv->write(priv, AR8327_REG_PAD5_MODE, t);
- t = ar8327_get_pad_cfg(pdata->pad6_cfg);
- priv->write(priv, AR8327_REG_PAD6_MODE, t);
-
- pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
- new_pos = pos;
-
- led_cfg = pdata->led_cfg;
- if (led_cfg) {
- if (led_cfg->open_drain)
- new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
- else
- new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
-
- priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
- priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
- priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
- priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
- }
-
- if (new_pos != pos) {
- new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
- priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
- }
-
- bus = priv->phy->bus;
- for (i = 0; i < AR8327_NUM_PHYS; i++) {
- ar8327_phy_fixup(priv, i);
-
- /* start aneg on the PHY */
- mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
- ADVERTISE_PAUSE_CAP |
- ADVERTISE_PAUSE_ASYM);
- mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
- mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- }
-
- msleep(1000);
-
- return 0;
-}
-
-static void
-ar8327_init_globals(struct ar8216_priv *priv)
-{
- u32 t;
-
- /* enable CPU port and disable mirror port */
- t = AR8327_FWD_CTRL0_CPU_PORT_EN |
- AR8327_FWD_CTRL0_MIRROR_PORT;
- priv->write(priv, AR8327_REG_FWD_CTRL0, t);
-
- /* forward multicast and broadcast frames to CPU */
- t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
- (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
- (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
- priv->write(priv, AR8327_REG_FWD_CTRL1, t);
-
- /* setup MTU */
- ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
- AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
-
- /* Enable MIB counters */
- ar8216_reg_set(priv, AR8327_REG_MODULE_EN,
- AR8327_MODULE_EN_MIB);
-}
-
-static void
-ar8327_config_port(struct ar8216_priv *priv, unsigned int port,
- struct ar8327_port_cfg *cfg)
-{
- u32 t;
-
- if (!cfg || !cfg->force_link) {
- priv->write(priv, AR8327_REG_PORT_STATUS(port),
- AR8216_PORT_STATUS_LINK_AUTO);
- return;
- }
-
- t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
- t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
- t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
- t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
-
- switch (cfg->speed) {
- case AR8327_PORT_SPEED_10:
- t |= AR8216_PORT_SPEED_10M;
- break;
- case AR8327_PORT_SPEED_100:
- t |= AR8216_PORT_SPEED_100M;
- break;
- case AR8327_PORT_SPEED_1000:
- t |= AR8216_PORT_SPEED_1000M;
- break;
- }
-
- priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
-}
-
-static void
-ar8327_init_port(struct ar8216_priv *priv, int port)
-{
- struct ar8327_platform_data *pdata;
- struct ar8327_port_cfg *cfg;
- u32 t;
-
- pdata = priv->phy->dev.platform_data;
-
- if (pdata && port == AR8216_PORT_CPU)
- cfg = &pdata->port0_cfg;
- else if (pdata && port == 6)
- cfg = &pdata->port6_cfg;
- else
- cfg = NULL;
-
- ar8327_config_port(priv, port, cfg);
-
- priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
-
- t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
- t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
- priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
-
- t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
- priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
-
- t = AR8327_PORT_LOOKUP_LEARN;
- t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
- priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
-}
-
-static u32
-ar8327_read_port_status(struct ar8216_priv *priv, int port)
-{
- return priv->read(priv, AR8327_REG_PORT_STATUS(port));
-}
-
-static int
-ar8327_atu_flush(struct ar8216_priv *priv)
-{
- int ret;
-
- ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
- AR8327_ATU_FUNC_BUSY, 0);
- if (!ret)
- priv->write(priv, AR8327_REG_ATU_FUNC,
- AR8327_ATU_FUNC_OP_FLUSH);
-
- return ret;
-}
-
-static void
-ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
-{
- if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
- AR8327_VTU_FUNC1_BUSY, 0))
- return;
-
- if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
- priv->write(priv, AR8327_REG_VTU_FUNC0, val);
-
- op |= AR8327_VTU_FUNC1_BUSY;
- priv->write(priv, AR8327_REG_VTU_FUNC1, op);
-}
-
-static void
-ar8327_vtu_flush(struct ar8216_priv *priv)
-{
- ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
-}
-
-static void
-ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
-{
- u32 op;
- u32 val;
- int i;
-
- op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
- val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
- for (i = 0; i < AR8327_NUM_PORTS; i++) {
- u32 mode;
-
- if ((port_mask & BIT(i)) == 0)
- mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
- else if (priv->vlan == 0)
- mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
- else if (priv->vlan_tagged & BIT(i))
- mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
- else
- mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
-
- val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
- }
- ar8327_vtu_op(priv, op, val);
-}
-
-static void
-ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
- u32 members, u32 pvid)
-{
- u32 t;
- u32 mode;
-
- t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
- t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
- priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
-
- mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
- switch (egress) {
- case AR8216_OUT_KEEP:
- mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
- break;
- case AR8216_OUT_STRIP_VLAN:
- mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
- break;
- case AR8216_OUT_ADD_VLAN:
- mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
- break;
- }
-
- t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
- t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
- priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
-
- t = members;
- t |= AR8327_PORT_LOOKUP_LEARN;
- t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
- t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
- priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
-}
-
-static const struct ar8xxx_chip ar8327_chip = {
- .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
- .hw_init = ar8327_hw_init,
- .init_globals = ar8327_init_globals,
- .init_port = ar8327_init_port,
- .setup_port = ar8327_setup_port,
- .read_port_status = ar8327_read_port_status,
- .atu_flush = ar8327_atu_flush,
- .vtu_flush = ar8327_vtu_flush,
- .vtu_load_vlan = ar8327_vtu_load_vlan,
-
- .num_mibs = ARRAY_SIZE(ar8236_mibs),
- .mib_decs = ar8236_mibs,
-};
-
-static int
-ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
- struct switch_val *val)
-{
- struct ar8216_priv *priv = to_ar8216(dev);
- priv->vlan = !!val->value.i;
- return 0;
-}
-
-static int
-ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
- struct switch_val *val)
-{
- struct ar8216_priv *priv = to_ar8216(dev);
- val->value.i = priv->vlan;
- return 0;
-}
-
-
-static int
-ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
-{
- struct ar8216_priv *priv = to_ar8216(dev);
-
- /* make sure no invalid PVIDs get set */
-
- if (vlan >= dev->vlans)
- return -EINVAL;
-
- priv->pvid[port] = vlan;
- return 0;
-}
-
-static int
-ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
-{
- struct ar8216_priv *priv = to_ar8216(dev);
- *vlan = priv->pvid[port];
- return 0;
-}
-
-static int
-ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
- struct switch_val *val)
-{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
priv->vlan_id[val->port_vlan] = val->value.i;
return 0;
}
static int
-ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
+ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
val->value.i = priv->vlan_id[val->port_vlan];
return 0;
}
-static int
-ar8216_sw_get_port_link(struct switch_dev *dev, int port,
+int
+ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
struct switch_port_link *link)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
ar8216_read_port_link(priv, port, link);
return 0;
}
static int
-ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
+ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
u8 ports = priv->vlan_table[val->port_vlan];
int i;
}
static int
-ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
+ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
u8 *vt = &priv->vlan_table[val->port_vlan];
int i, j;
return 0;
}
-static int
-ar8216_sw_hw_apply(struct switch_dev *dev)
+static void
+ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ int port;
+
+ /* reset all mirror registers */
+ ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
+ AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
+ (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
+ for (port = 0; port < AR8216_NUM_PORTS; port++) {
+ ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
+ AR8216_PORT_CTRL_MIRROR_RX);
+
+ ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
+ AR8216_PORT_CTRL_MIRROR_TX);
+ }
+
+ /* now enable mirroring if necessary */
+ if (priv->source_port >= AR8216_NUM_PORTS ||
+ priv->monitor_port >= AR8216_NUM_PORTS ||
+ priv->source_port == priv->monitor_port) {
+ return;
+ }
+
+ ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
+ AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
+ (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
+
+ if (priv->mirror_rx)
+ ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
+ AR8216_PORT_CTRL_MIRROR_RX);
+
+ if (priv->mirror_tx)
+ ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
+ AR8216_PORT_CTRL_MIRROR_TX);
+}
+
+int
+ar8xxx_sw_hw_apply(struct switch_dev *dev)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
u8 portmask[AR8X16_MAX_PORTS];
int i, j;
/* update the port destination mask registers and tag settings */
for (i = 0; i < dev->ports; i++) {
- int egress, ingress;
- int pvid;
-
- if (priv->vlan) {
- pvid = priv->vlan_id[priv->pvid[i]];
- if (priv->vlan_tagged & (1 << i))
- egress = AR8216_OUT_ADD_VLAN;
- else
- egress = AR8216_OUT_STRIP_VLAN;
- ingress = AR8216_IN_SECURE;
- } else {
- pvid = i;
- egress = AR8216_OUT_KEEP;
- ingress = AR8216_IN_PORT_ONLY;
- }
-
- priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
- pvid);
+ priv->chip->setup_port(priv, i, portmask[i]);
}
+
+ priv->chip->set_mirror_regs(priv);
+
mutex_unlock(&priv->reg_mutex);
return 0;
}
-static int
-ar8216_sw_reset_switch(struct switch_dev *dev)
+int
+ar8xxx_sw_reset_switch(struct switch_dev *dev)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ const struct ar8xxx_chip *chip = priv->chip;
int i;
mutex_lock(&priv->reg_mutex);
- memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
- offsetof(struct ar8216_priv, vlan));
+ memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
+ offsetof(struct ar8xxx_priv, vlan));
for (i = 0; i < AR8X16_MAX_VLANS; i++)
priv->vlan_id[i] = i;
/* Configure all ports */
for (i = 0; i < dev->ports; i++)
- priv->chip->init_port(priv, i);
+ chip->init_port(priv, i);
+
+ priv->mirror_rx = false;
+ priv->mirror_tx = false;
+ priv->source_port = 0;
+ priv->monitor_port = 0;
+
+ chip->init_globals(priv);
- priv->chip->init_globals(priv);
mutex_unlock(&priv->reg_mutex);
- return ar8216_sw_hw_apply(dev);
+ return chip->sw_hw_apply(dev);
}
-static int
-ar8216_sw_set_reset_mibs(struct switch_dev *dev,
+int
+ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
unsigned int len;
int ret;
len = priv->dev.ports * priv->chip->num_mibs *
sizeof(*priv->mib_stats);
memset(priv->mib_stats, '\0', len);
- ret = ar8216_mib_flush(priv);
+ ret = ar8xxx_mib_flush(priv);
if (ret)
goto unlock;
return ret;
}
-static int
-ar8216_sw_set_port_reset_mib(struct switch_dev *dev,
+int
+ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ priv->mirror_rx = !!val->value.i;
+ priv->chip->set_mirror_regs(priv);
+ mutex_unlock(&priv->reg_mutex);
+
+ return 0;
+}
+
+int
+ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ val->value.i = priv->mirror_rx;
+ return 0;
+}
+
+int
+ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ priv->mirror_tx = !!val->value.i;
+ priv->chip->set_mirror_regs(priv);
+ mutex_unlock(&priv->reg_mutex);
+
+ return 0;
+}
+
+int
+ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ val->value.i = priv->mirror_tx;
+ return 0;
+}
+
+int
+ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ priv->monitor_port = val->value.i;
+ priv->chip->set_mirror_regs(priv);
+ mutex_unlock(&priv->reg_mutex);
+
+ return 0;
+}
+
+int
+ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ val->value.i = priv->monitor_port;
+ return 0;
+}
+
+int
+ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+
+ mutex_lock(&priv->reg_mutex);
+ priv->source_port = val->value.i;
+ priv->chip->set_mirror_regs(priv);
+ mutex_unlock(&priv->reg_mutex);
+
+ return 0;
+}
+
+int
+ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ val->value.i = priv->source_port;
+ return 0;
+}
+
+int
+ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
int port;
int ret;
return -EINVAL;
mutex_lock(&priv->mib_lock);
- ret = ar8216_mib_capture(priv);
+ ret = ar8xxx_mib_capture(priv);
if (ret)
goto unlock;
- ar8216_mib_fetch_port_stat(priv, port, true);
+ ar8xxx_mib_fetch_port_stat(priv, port, true);
ret = 0;
return ret;
}
-static int
-ar8216_sw_get_port_mib(struct switch_dev *dev,
+int
+ar8xxx_sw_get_port_mib(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
{
- struct ar8216_priv *priv = to_ar8216(dev);
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
const struct ar8xxx_chip *chip = priv->chip;
u64 *mib_stats;
int port;
return -EINVAL;
mutex_lock(&priv->mib_lock);
- ret = ar8216_mib_capture(priv);
+ ret = ar8xxx_mib_capture(priv);
if (ret)
goto unlock;
- ar8216_mib_fetch_port_stat(priv, port, false);
+ ar8xxx_mib_fetch_port_stat(priv, port, false);
len += snprintf(buf + len, sizeof(priv->buf) - len,
"Port %d MIB counters\n",
return ret;
}
-static struct switch_attr ar8216_globals[] = {
+int
+ar8xxx_sw_get_arl_table(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ struct mii_bus *bus = priv->mii_bus;
+ const struct ar8xxx_chip *chip = priv->chip;
+ char *buf = priv->arl_buf;
+ int i, j, k, len = 0;
+ struct arl_entry *a, *a1;
+ u32 status;
+
+ if (!chip->get_arl_entry)
+ return -EOPNOTSUPP;
+
+ mutex_lock(&priv->reg_mutex);
+ mutex_lock(&bus->mdio_lock);
+
+ chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
+
+ for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
+ a = &priv->arl_table[i];
+ duplicate:
+ chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
+
+ if (!status)
+ break;
+
+ /* avoid duplicates
+ * ARL table can include multiple valid entries
+ * per MAC, just with differing status codes
+ */
+ for (j = 0; j < i; ++j) {
+ a1 = &priv->arl_table[j];
+ if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
+ goto duplicate;
+ }
+ }
+
+ mutex_unlock(&bus->mdio_lock);
+
+ len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
+ "address resolution table\n");
+
+ if (i == AR8XXX_NUM_ARL_RECORDS)
+ len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
+ "Too many entries found, displaying the first %d only!\n",
+ AR8XXX_NUM_ARL_RECORDS);
+
+ for (j = 0; j < priv->dev.ports; ++j) {
+ for (k = 0; k < i; ++k) {
+ a = &priv->arl_table[k];
+ if (a->port != j)
+ continue;
+ len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
+ "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
+ j,
+ a->mac[5], a->mac[4], a->mac[3],
+ a->mac[2], a->mac[1], a->mac[0]);
+ }
+ }
+
+ val->value.s = buf;
+ val->len = len;
+
+ mutex_unlock(&priv->reg_mutex);
+
+ return 0;
+}
+
+static const struct switch_attr ar8xxx_sw_attr_globals[] = {
{
.type = SWITCH_TYPE_INT,
.name = "enable_vlan",
.description = "Enable VLAN mode",
- .set = ar8216_sw_set_vlan,
- .get = ar8216_sw_get_vlan,
+ .set = ar8xxx_sw_set_vlan,
+ .get = ar8xxx_sw_get_vlan,
.max = 1
},
{
.type = SWITCH_TYPE_NOVAL,
.name = "reset_mibs",
.description = "Reset all MIB counters",
- .set = ar8216_sw_set_reset_mibs,
+ .set = ar8xxx_sw_set_reset_mibs,
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_mirror_rx",
+ .description = "Enable mirroring of RX packets",
+ .set = ar8xxx_sw_set_mirror_rx_enable,
+ .get = ar8xxx_sw_get_mirror_rx_enable,
+ .max = 1
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_mirror_tx",
+ .description = "Enable mirroring of TX packets",
+ .set = ar8xxx_sw_set_mirror_tx_enable,
+ .get = ar8xxx_sw_get_mirror_tx_enable,
+ .max = 1
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "mirror_monitor_port",
+ .description = "Mirror monitor port",
+ .set = ar8xxx_sw_set_mirror_monitor_port,
+ .get = ar8xxx_sw_get_mirror_monitor_port,
+ .max = AR8216_NUM_PORTS - 1
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "mirror_source_port",
+ .description = "Mirror source port",
+ .set = ar8xxx_sw_set_mirror_source_port,
+ .get = ar8xxx_sw_get_mirror_source_port,
+ .max = AR8216_NUM_PORTS - 1
+ },
+ {
+ .type = SWITCH_TYPE_STRING,
+ .name = "arl_table",
+ .description = "Get ARL table",
+ .set = NULL,
+ .get = ar8xxx_sw_get_arl_table,
},
-
};
-static struct switch_attr ar8216_port[] = {
+const struct switch_attr ar8xxx_sw_attr_port[2] = {
{
.type = SWITCH_TYPE_NOVAL,
.name = "reset_mib",
.description = "Reset single port MIB counters",
- .set = ar8216_sw_set_port_reset_mib,
+ .set = ar8xxx_sw_set_port_reset_mib,
},
{
.type = SWITCH_TYPE_STRING,
.name = "mib",
.description = "Get port's MIB counters",
.set = NULL,
- .get = ar8216_sw_get_port_mib,
+ .get = ar8xxx_sw_get_port_mib,
},
};
-static struct switch_attr ar8216_vlan[] = {
+const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
{
.type = SWITCH_TYPE_INT,
.name = "vid",
.description = "VLAN ID (0-4094)",
- .set = ar8216_sw_set_vid,
- .get = ar8216_sw_get_vid,
+ .set = ar8xxx_sw_set_vid,
+ .get = ar8xxx_sw_get_vid,
.max = 4094,
},
};
-static const struct switch_dev_ops ar8216_sw_ops = {
+static const struct switch_dev_ops ar8xxx_sw_ops = {
.attr_global = {
- .attr = ar8216_globals,
- .n_attr = ARRAY_SIZE(ar8216_globals),
+ .attr = ar8xxx_sw_attr_globals,
+ .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
},
.attr_port = {
- .attr = ar8216_port,
- .n_attr = ARRAY_SIZE(ar8216_port),
+ .attr = ar8xxx_sw_attr_port,
+ .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
},
.attr_vlan = {
- .attr = ar8216_vlan,
- .n_attr = ARRAY_SIZE(ar8216_vlan),
+ .attr = ar8xxx_sw_attr_vlan,
+ .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
},
- .get_port_pvid = ar8216_sw_get_pvid,
- .set_port_pvid = ar8216_sw_set_pvid,
- .get_vlan_ports = ar8216_sw_get_ports,
- .set_vlan_ports = ar8216_sw_set_ports,
- .apply_config = ar8216_sw_hw_apply,
- .reset_switch = ar8216_sw_reset_switch,
- .get_port_link = ar8216_sw_get_port_link,
+ .get_port_pvid = ar8xxx_sw_get_pvid,
+ .set_port_pvid = ar8xxx_sw_set_pvid,
+ .get_vlan_ports = ar8xxx_sw_get_ports,
+ .set_vlan_ports = ar8xxx_sw_set_ports,
+ .apply_config = ar8xxx_sw_hw_apply,
+ .reset_switch = ar8xxx_sw_reset_switch,
+ .get_port_link = ar8xxx_sw_get_port_link,
+};
+
+static const struct ar8xxx_chip ar8216_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x19000,
+ .reg_port_stats_length = 0xa0,
+
+ .name = "Atheros AR8216",
+ .ports = AR8216_NUM_PORTS,
+ .vlans = AR8216_NUM_VLANS,
+ .swops = &ar8xxx_sw_ops,
+
+ .hw_init = ar8216_hw_init,
+ .init_globals = ar8216_init_globals,
+ .init_port = ar8216_init_port,
+ .setup_port = ar8216_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .atu_flush_port = ar8216_atu_flush_port,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
+ .get_arl_entry = ar8216_get_arl_entry,
+ .sw_hw_apply = ar8xxx_sw_hw_apply,
+
+ .num_mibs = ARRAY_SIZE(ar8216_mibs),
+ .mib_decs = ar8216_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC
+};
+
+static const struct ar8xxx_chip ar8236_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x20000,
+ .reg_port_stats_length = 0x100,
+
+ .name = "Atheros AR8236",
+ .ports = AR8216_NUM_PORTS,
+ .vlans = AR8216_NUM_VLANS,
+ .swops = &ar8xxx_sw_ops,
+
+ .hw_init = ar8216_hw_init,
+ .init_globals = ar8236_init_globals,
+ .init_port = ar8216_init_port,
+ .setup_port = ar8236_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .atu_flush_port = ar8216_atu_flush_port,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
+ .get_arl_entry = ar8216_get_arl_entry,
+ .sw_hw_apply = ar8xxx_sw_hw_apply,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC
+};
+
+static const struct ar8xxx_chip ar8316_chip = {
+ .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x20000,
+ .reg_port_stats_length = 0x100,
+
+ .name = "Atheros AR8316",
+ .ports = AR8216_NUM_PORTS,
+ .vlans = AR8X16_MAX_VLANS,
+ .swops = &ar8xxx_sw_ops,
+
+ .hw_init = ar8316_hw_init,
+ .init_globals = ar8316_init_globals,
+ .init_port = ar8216_init_port,
+ .setup_port = ar8216_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .atu_flush_port = ar8216_atu_flush_port,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
+ .get_arl_entry = ar8216_get_arl_entry,
+ .sw_hw_apply = ar8xxx_sw_hw_apply,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC
};
static int
-ar8216_id_chip(struct ar8216_priv *priv)
+ar8xxx_id_chip(struct ar8xxx_priv *priv)
{
u32 val;
u16 id;
int i;
- val = ar8216_mii_read(priv, AR8216_REG_CTRL);
+ val = ar8xxx_read(priv, AR8216_REG_CTRL);
if (val == ~0)
return -ENODEV;
for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
u16 t;
- val = ar8216_mii_read(priv, AR8216_REG_CTRL);
+ val = ar8xxx_read(priv, AR8216_REG_CTRL);
if (val == ~0)
return -ENODEV;
priv->chip = &ar8316_chip;
break;
case AR8XXX_VER_AR8327:
- priv->mii_lo_first = true;
priv->chip = &ar8327_chip;
break;
+ case AR8XXX_VER_AR8337:
+ priv->chip = &ar8337_chip;
+ break;
default:
- printk(KERN_DEBUG
- "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
- priv->chip_ver, priv->chip_rev,
- mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
- mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
+ pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
+ priv->chip_ver, priv->chip_rev);
return -ENODEV;
}
static void
ar8xxx_mib_work_func(struct work_struct *work)
{
- struct ar8216_priv *priv;
+ struct ar8xxx_priv *priv;
int err;
- priv = container_of(work, struct ar8216_priv, mib_work.work);
+ priv = container_of(work, struct ar8xxx_priv, mib_work.work);
mutex_lock(&priv->mib_lock);
- err = ar8216_mib_capture(priv);
+ err = ar8xxx_mib_capture(priv);
if (err)
goto next_port;
- ar8216_mib_fetch_port_stat(priv, priv->mib_next_port, false);
+ ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
next_port:
priv->mib_next_port++;
}
static int
-ar8xxx_mib_init(struct ar8216_priv *priv)
+ar8xxx_mib_init(struct ar8xxx_priv *priv)
{
unsigned int len;
if (!priv->mib_stats)
return -ENOMEM;
- mutex_init(&priv->mib_lock);
- INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
-
return 0;
}
static void
-ar8xxx_mib_start(struct ar8216_priv *priv)
+ar8xxx_mib_start(struct ar8xxx_priv *priv)
{
if (!ar8xxx_has_mib_counters(priv))
return;
}
static void
-ar8xxx_mib_cleanup(struct ar8216_priv *priv)
+ar8xxx_mib_stop(struct ar8xxx_priv *priv)
{
if (!ar8xxx_has_mib_counters(priv))
return;
cancel_delayed_work(&priv->mib_work);
+}
+
+static struct ar8xxx_priv *
+ar8xxx_create(void)
+{
+ struct ar8xxx_priv *priv;
+
+ priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
+ if (priv == NULL)
+ return NULL;
+
+ mutex_init(&priv->reg_mutex);
+ mutex_init(&priv->mib_lock);
+ INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
+
+ return priv;
+}
+
+static void
+ar8xxx_free(struct ar8xxx_priv *priv)
+{
+ if (priv->chip && priv->chip->cleanup)
+ priv->chip->cleanup(priv);
+
+ kfree(priv->chip_data);
kfree(priv->mib_stats);
+ kfree(priv);
}
static int
-ar8216_config_init(struct phy_device *pdev)
+ar8xxx_probe_switch(struct ar8xxx_priv *priv)
{
- struct ar8216_priv *priv = pdev->priv;
- struct net_device *dev = pdev->attached_dev;
+ const struct ar8xxx_chip *chip;
struct switch_dev *swdev;
int ret;
- if (!priv) {
- priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
- if (priv == NULL)
- return -ENOMEM;
- }
-
- priv->phy = pdev;
-
- ret = ar8216_id_chip(priv);
+ ret = ar8xxx_id_chip(priv);
if (ret)
- goto err_free_priv;
+ return ret;
- if (pdev->addr != 0) {
- if (ar8xxx_has_gige(priv)) {
- pdev->supported |= SUPPORTED_1000baseT_Full;
- pdev->advertising |= ADVERTISED_1000baseT_Full;
- }
+ chip = priv->chip;
- if (chip_is_ar8316(priv)) {
- /* check if we're attaching to the switch twice */
- pdev = pdev->bus->phy_map[0];
- if (!pdev) {
- kfree(priv);
- return 0;
- }
+ swdev = &priv->dev;
+ swdev->cpu_port = AR8216_PORT_CPU;
+ swdev->name = chip->name;
+ swdev->vlans = chip->vlans;
+ swdev->ports = chip->ports;
+ swdev->ops = chip->swops;
- /* switch device has not been initialized, reuse priv */
- if (!pdev->priv) {
- priv->port4_phy = true;
- pdev->priv = priv;
- return 0;
- }
+ ret = ar8xxx_mib_init(priv);
+ if (ret)
+ return ret;
- kfree(priv);
+ return 0;
+}
- /* switch device has been initialized, reinit */
- priv = pdev->priv;
- priv->dev.ports = (AR8216_NUM_PORTS - 1);
- priv->initialized = false;
- priv->port4_phy = true;
- ar8316_hw_init(priv);
- return 0;
- }
+static int
+ar8xxx_start(struct ar8xxx_priv *priv)
+{
+ int ret;
- kfree(priv);
- return 0;
- }
+ priv->init = true;
- if (ar8xxx_has_gige(priv))
- pdev->supported = SUPPORTED_1000baseT_Full;
- else
- pdev->supported = SUPPORTED_100baseT_Full;
- pdev->advertising = pdev->supported;
+ ret = priv->chip->hw_init(priv);
+ if (ret)
+ return ret;
- mutex_init(&priv->reg_mutex);
- priv->read = ar8216_mii_read;
- priv->write = ar8216_mii_write;
+ ret = ar8xxx_sw_reset_switch(&priv->dev);
+ if (ret)
+ return ret;
- pdev->priv = priv;
+ priv->init = false;
- swdev = &priv->dev;
- swdev->cpu_port = AR8216_PORT_CPU;
- swdev->ops = &ar8216_sw_ops;
- swdev->ports = AR8216_NUM_PORTS;
+ ar8xxx_mib_start(priv);
- if (chip_is_ar8316(priv)) {
- swdev->name = "Atheros AR8316";
- swdev->vlans = AR8X16_MAX_VLANS;
+ return 0;
+}
- if (priv->port4_phy) {
- /* port 5 connected to the other mac, therefore unusable */
- swdev->ports = (AR8216_NUM_PORTS - 1);
- }
- } else if (chip_is_ar8236(priv)) {
- swdev->name = "Atheros AR8236";
- swdev->vlans = AR8216_NUM_VLANS;
- swdev->ports = AR8216_NUM_PORTS;
- } else if (chip_is_ar8327(priv)) {
- swdev->name = "Atheros AR8327";
- swdev->vlans = AR8X16_MAX_VLANS;
- swdev->ports = AR8327_NUM_PORTS;
- } else {
- swdev->name = "Atheros AR8216";
- swdev->vlans = AR8216_NUM_VLANS;
- }
+static int
+ar8xxx_phy_config_init(struct phy_device *phydev)
+{
+ struct ar8xxx_priv *priv = phydev->priv;
+ struct net_device *dev = phydev->attached_dev;
+ int ret;
- ret = ar8xxx_mib_init(priv);
- if (ret)
- goto err_free_priv;
+ if (WARN_ON(!priv))
+ return -ENODEV;
- ret = register_switch(&priv->dev, pdev->attached_dev);
- if (ret)
- goto err_cleanup_mib;
+ if (priv->chip->config_at_probe)
+ return ar8xxx_phy_check_aneg(phydev);
- printk(KERN_INFO "%s: %s switch driver attached.\n",
- pdev->attached_dev->name, swdev->name);
+ priv->phy = phydev;
- priv->init = true;
+ if (phydev->addr != 0) {
+ if (chip_is_ar8316(priv)) {
+ /* switch device has been initialized, reinit */
+ priv->dev.ports = (AR8216_NUM_PORTS - 1);
+ priv->initialized = false;
+ priv->port4_phy = true;
+ ar8316_hw_init(priv);
+ return 0;
+ }
- ret = priv->chip->hw_init(priv);
- if (ret)
- goto err_cleanup_mib;
+ return 0;
+ }
- ret = ar8216_sw_reset_switch(&priv->dev);
+ ret = ar8xxx_start(priv);
if (ret)
- goto err_cleanup_mib;
-
- dev->phy_ptr = priv;
+ return ret;
/* VID fixup only needed on ar8216 */
- if (chip_is_ar8216(priv) && pdev->addr == 0) {
+ if (chip_is_ar8216(priv)) {
+ dev->phy_ptr = priv;
dev->priv_flags |= IFF_NO_IP_ALIGN;
dev->eth_mangle_rx = ar8216_mangle_rx;
dev->eth_mangle_tx = ar8216_mangle_tx;
}
- priv->init = false;
+ return 0;
+}
- ar8xxx_mib_start(priv);
+static bool
+ar8xxx_check_link_states(struct ar8xxx_priv *priv)
+{
+ bool link_new, changed = false;
+ u32 status;
+ int i;
- return 0;
+ mutex_lock(&priv->reg_mutex);
-err_cleanup_mib:
- ar8xxx_mib_cleanup(priv);
-err_free_priv:
- kfree(priv);
- return ret;
+ for (i = 0; i < priv->dev.ports; i++) {
+ status = priv->chip->read_port_status(priv, i);
+ link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
+ if (link_new == priv->link_up[i])
+ continue;
+
+ priv->link_up[i] = link_new;
+ changed = true;
+ /* flush ARL entries for this port if it went down*/
+ if (!link_new)
+ priv->chip->atu_flush_port(priv, i);
+ dev_info(&priv->phy->dev, "Port %d is %s\n",
+ i, link_new ? "up" : "down");
+ }
+
+ mutex_unlock(&priv->reg_mutex);
+
+ return changed;
}
static int
-ar8216_read_status(struct phy_device *phydev)
+ar8xxx_phy_read_status(struct phy_device *phydev)
{
- struct ar8216_priv *priv = phydev->priv;
+ struct ar8xxx_priv *priv = phydev->priv;
struct switch_port_link link;
- int ret;
+
+ /* check for switch port link changes */
+ if (phydev->state == PHY_CHANGELINK)
+ ar8xxx_check_link_states(priv);
if (phydev->addr != 0)
return genphy_read_status(phydev);
}
phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
- /* flush the address translation unit */
- mutex_lock(&priv->reg_mutex);
- ret = priv->chip->atu_flush(priv);
- mutex_unlock(&priv->reg_mutex);
-
phydev->state = PHY_RUNNING;
netif_carrier_on(phydev->attached_dev);
phydev->adjust_link(phydev->attached_dev);
- return ret;
+ return 0;
}
static int
-ar8216_config_aneg(struct phy_device *phydev)
+ar8xxx_phy_config_aneg(struct phy_device *phydev)
{
if (phydev->addr == 0)
return 0;
return genphy_config_aneg(phydev);
}
+static const u32 ar8xxx_phy_ids[] = {
+ 0x004dd033,
+ 0x004dd034, /* AR8327 */
+ 0x004dd036, /* AR8337 */
+ 0x004dd041,
+ 0x004dd042,
+ 0x004dd043, /* AR8236 */
+};
+
+static bool
+ar8xxx_phy_match(u32 phy_id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
+ if (phy_id == ar8xxx_phy_ids[i])
+ return true;
+
+ return false;
+}
+
+static bool
+ar8xxx_is_possible(struct mii_bus *bus)
+{
+ unsigned i;
+
+ for (i = 0; i < 4; i++) {
+ u32 phy_id;
+
+ phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
+ phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
+ if (!ar8xxx_phy_match(phy_id)) {
+ pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
+ dev_name(&bus->dev), i, phy_id);
+ return false;
+ }
+ }
+
+ return true;
+}
+
static int
-ar8216_probe(struct phy_device *pdev)
+ar8xxx_phy_probe(struct phy_device *phydev)
{
- struct ar8216_priv *priv;
+ struct ar8xxx_priv *priv;
+ struct switch_dev *swdev;
int ret;
- priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
- if (priv == NULL)
- return -ENOMEM;
+ /* skip PHYs at unused adresses */
+ if (phydev->addr != 0 && phydev->addr != 4)
+ return -ENODEV;
+
+ if (!ar8xxx_is_possible(phydev->bus))
+ return -ENODEV;
- priv->phy = pdev;
+ mutex_lock(&ar8xxx_dev_list_lock);
+ list_for_each_entry(priv, &ar8xxx_dev_list, list)
+ if (priv->mii_bus == phydev->bus)
+ goto found;
- ret = ar8216_id_chip(priv);
- kfree(priv);
+ priv = ar8xxx_create();
+ if (priv == NULL) {
+ ret = -ENOMEM;
+ goto unlock;
+ }
+
+ priv->mii_bus = phydev->bus;
+
+ ret = ar8xxx_probe_switch(priv);
+ if (ret)
+ goto free_priv;
+
+ swdev = &priv->dev;
+ swdev->alias = dev_name(&priv->mii_bus->dev);
+ ret = register_switch(swdev, NULL);
+ if (ret)
+ goto free_priv;
+
+ pr_info("%s: %s rev. %u switch registered on %s\n",
+ swdev->devname, swdev->name, priv->chip_rev,
+ dev_name(&priv->mii_bus->dev));
+
+found:
+ priv->use_count++;
+
+ if (phydev->addr == 0) {
+ if (ar8xxx_has_gige(priv)) {
+ phydev->supported = SUPPORTED_1000baseT_Full;
+ phydev->advertising = ADVERTISED_1000baseT_Full;
+ } else {
+ phydev->supported = SUPPORTED_100baseT_Full;
+ phydev->advertising = ADVERTISED_100baseT_Full;
+ }
+ if (priv->chip->config_at_probe) {
+ priv->phy = phydev;
+
+ ret = ar8xxx_start(priv);
+ if (ret)
+ goto err_unregister_switch;
+ }
+ } else {
+ if (ar8xxx_has_gige(priv)) {
+ phydev->supported |= SUPPORTED_1000baseT_Full;
+ phydev->advertising |= ADVERTISED_1000baseT_Full;
+ }
+ }
+
+ phydev->priv = priv;
+
+ list_add(&priv->list, &ar8xxx_dev_list);
+
+ mutex_unlock(&ar8xxx_dev_list_lock);
+
+ return 0;
+
+err_unregister_switch:
+ if (--priv->use_count)
+ goto unlock;
+
+ unregister_switch(&priv->dev);
+
+free_priv:
+ ar8xxx_free(priv);
+unlock:
+ mutex_unlock(&ar8xxx_dev_list_lock);
return ret;
}
static void
-ar8216_remove(struct phy_device *pdev)
+ar8xxx_phy_detach(struct phy_device *phydev)
{
- struct ar8216_priv *priv = pdev->priv;
- struct net_device *dev = pdev->attached_dev;
+ struct net_device *dev = phydev->attached_dev;
- if (!priv)
+ if (!dev)
return;
+ dev->phy_ptr = NULL;
dev->priv_flags &= ~IFF_NO_IP_ALIGN;
dev->eth_mangle_rx = NULL;
dev->eth_mangle_tx = NULL;
+}
+
+static void
+ar8xxx_phy_remove(struct phy_device *phydev)
+{
+ struct ar8xxx_priv *priv = phydev->priv;
- if (pdev->addr == 0)
- unregister_switch(&priv->dev);
+ if (WARN_ON(!priv))
+ return;
- ar8xxx_mib_cleanup(priv);
- kfree(priv);
+ phydev->priv = NULL;
+ if (--priv->use_count > 0)
+ return;
+
+ mutex_lock(&ar8xxx_dev_list_lock);
+ list_del(&priv->list);
+ mutex_unlock(&ar8xxx_dev_list_lock);
+
+ unregister_switch(&priv->dev);
+ ar8xxx_mib_stop(priv);
+ ar8xxx_free(priv);
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
+static int
+ar8xxx_phy_soft_reset(struct phy_device *phydev)
+{
+ /* we don't need an extra reset */
+ return 0;
}
+#endif
-static struct phy_driver ar8216_driver = {
+static struct phy_driver ar8xxx_phy_driver = {
.phy_id = 0x004d0000,
.name = "Atheros AR8216/AR8236/AR8316",
.phy_id_mask = 0xffff0000,
.features = PHY_BASIC_FEATURES,
- .probe = ar8216_probe,
- .remove = ar8216_remove,
- .config_init = &ar8216_config_init,
- .config_aneg = &ar8216_config_aneg,
- .read_status = &ar8216_read_status,
+ .probe = ar8xxx_phy_probe,
+ .remove = ar8xxx_phy_remove,
+ .detach = ar8xxx_phy_detach,
+ .config_init = ar8xxx_phy_config_init,
+ .config_aneg = ar8xxx_phy_config_aneg,
+ .read_status = ar8xxx_phy_read_status,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
+ .soft_reset = ar8xxx_phy_soft_reset,
+#endif
.driver = { .owner = THIS_MODULE },
};
int __init
-ar8216_init(void)
+ar8xxx_init(void)
{
- return phy_driver_register(&ar8216_driver);
+ return phy_driver_register(&ar8xxx_phy_driver);
}
void __exit
-ar8216_exit(void)
+ar8xxx_exit(void)
{
- phy_driver_unregister(&ar8216_driver);
+ phy_driver_unregister(&ar8xxx_phy_driver);
}
-module_init(ar8216_init);
-module_exit(ar8216_exit);
+module_init(ar8xxx_init);
+module_exit(ar8xxx_exit);
MODULE_LICENSE("GPL");
projects / openwrt / openwrt.git / blobdiff