#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/netlink.h>
+#include <linux/of_device.h>
+#include <linux/of_mdio.h>
+#include <linux/of_net.h>
#include <linux/bitops.h>
#include <net/genetlink.h>
#include <linux/switch.h>
#include <linux/delay.h>
#include <linux/phy.h>
-#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/lockdep.h>
#include <linux/ar8216_platform.h>
if (ret & BMCR_ANENABLE)
return 0;
- dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
+ dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
ret |= BMCR_ANENABLE | BMCR_ANRESTART;
return phy_write(phydev, MII_BMCR, ret);
}
int i;
struct mii_bus *bus;
- bus = priv->mii_bus;
+ bus = priv->sw_mii_bus ?: priv->mii_bus;
for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
if (priv->chip->phy_fixup)
priv->chip->phy_fixup(priv, i);
return ret;
}
+void
+ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
+ u16 dbg_addr, u16 *dbg_data)
+{
+ struct mii_bus *bus = priv->mii_bus;
+
+ mutex_lock(&bus->mdio_lock);
+ bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
+ *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
+ mutex_unlock(&bus->mdio_lock);
+}
void
ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
return 0;
usleep_range(1000, 2000);
+ cond_resched();
}
return -ETIMEDOUT;
mib_stats[i] = 0;
else
mib_stats[i] += t;
+ cond_resched();
}
}
break;
udelay(10);
+ cond_resched();
}
pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
}
static void
-ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
+__ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,
+ bool ath_hdr_en)
{
u32 header;
u32 egress, ingress;
ingress = AR8216_IN_PORT_ONLY;
}
- if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
- header = AR8216_PORT_CTRL_HEADER;
- else
- header = 0;
+ header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;
ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
(pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
}
+static void
+ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
+{
+ return __ar8216_setup_port(priv, port, members,
+ chip_is_ar8216(priv) && priv->vlan &&
+ port == AR8216_PORT_CPU);
+}
+
static int
ar8216_hw_init(struct ar8xxx_priv *priv)
{
if (priv->initialized)
return 0;
+ ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
+ ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
+
ar8xxx_phy_init(priv);
priv->initialized = true;
}
static void
-ar8216_init_port(struct ar8xxx_priv *priv, int port)
+__ar8216_init_port(struct ar8xxx_priv *priv, int port,
+ bool cpu_ge, bool flow_en)
{
/* Enable port learning and tx */
ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
if (port == AR8216_PORT_CPU) {
ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
AR8216_PORT_STATUS_LINK_UP |
- (ar8xxx_has_gige(priv) ?
- AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
+ (cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
AR8216_PORT_STATUS_TXMAC |
AR8216_PORT_STATUS_RXMAC |
- (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
- (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
+ (flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
+ (flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
AR8216_PORT_STATUS_DUPLEX);
} else {
ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
}
}
+static void
+ar8216_init_port(struct ar8xxx_priv *priv, int port)
+{
+ __ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
+ chip_is_ar8316(priv));
+}
+
static void
ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
{
int timeout = 20;
- while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
- udelay(10);
+ while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
+ udelay(10);
+ cond_resched();
+ }
if (!timeout)
pr_err("ar8216: timeout waiting for atu to become ready\n");
u16 r2, page;
u16 r1_func0, r1_func1, r1_func2;
u32 t, val0, val1, val2;
- int i;
split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
r2 |= 0x10;
if (!*status)
break;
- i = 0;
- t = AR8216_ATU_PORT0;
- while (!(val2 & t) && ++i < priv->dev.ports)
- t <<= 1;
-
- a->port = i;
+ a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
}
}
+static int
+ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)
+{
+ u32 t, val = 0xffff;
+ int err;
+
+ if (addr >= AR8216_NUM_PORTS)
+ return 0xffff;
+ t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
+ (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
+ AR8216_MDIO_CTRL_MASTER_EN |
+ AR8216_MDIO_CTRL_BUSY |
+ AR8216_MDIO_CTRL_CMD_READ;
+
+ ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
+ err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
+ AR8216_MDIO_CTRL_BUSY, 0, 5);
+ if (!err)
+ val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);
+
+ return val & AR8216_MDIO_CTRL_DATA_M;
+}
+
+static int
+ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)
+{
+ u32 t;
+ int ret;
+
+ if (addr >= AR8216_NUM_PORTS)
+ return -EINVAL;
+
+ t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
+ (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
+ AR8216_MDIO_CTRL_MASTER_EN |
+ AR8216_MDIO_CTRL_BUSY |
+ AR8216_MDIO_CTRL_CMD_WRITE |
+ val;
+
+ ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
+ ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
+ AR8216_MDIO_CTRL_BUSY, 0, 5);
+
+ return ret;
+}
+
+static int
+ar8229_hw_init(struct ar8xxx_priv *priv)
+{
+ int phy_if_mode;
+
+ if (priv->initialized)
+ return 0;
+
+ ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
+ ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
+
+ phy_if_mode = of_get_phy_mode(priv->pdev->of_node);
+
+ if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
+ ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
+ AR8229_OPER_MODE0_MAC_GMII_EN);
+ } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
+ ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
+ AR8229_OPER_MODE0_PHY_MII_EN);
+ } else {
+ pr_err("ar8229: unsupported mii mode\n");
+ return -EINVAL;
+ }
+
+ if (priv->port4_phy) {
+ ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
+ AR8229_REG_OPER_MODE1_PHY4_MII_EN);
+ /* disable port5 to prevent mii conflict */
+ ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
+ }
+
+ ar8xxx_phy_init(priv);
+
+ priv->initialized = true;
+ return 0;
+}
+
+static void
+ar8229_init_globals(struct ar8xxx_priv *priv)
+{
+
+ /* Enable CPU port, and disable mirror port */
+ ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
+ AR8216_GLOBAL_CPUPORT_EN |
+ (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
+
+ /* Setup TAG priority mapping */
+ ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
+
+ /* Enable aging, MAC replacing */
+ ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
+ 0x2b /* 5 min age time */ |
+ AR8216_ATU_CTRL_AGE_EN |
+ AR8216_ATU_CTRL_LEARN_CHANGE);
+
+ /* Enable ARP frame acknowledge */
+ ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
+ AR8229_QM_CTRL_ARP_EN);
+
+ /* Enable Broadcast/Multicast frames transmitted to the CPU */
+ ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
+ AR8229_FLOOD_MASK_BC_DP(0) |
+ AR8229_FLOOD_MASK_MC_DP(0));
+
+ /* setup MTU */
+ ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
+
+ /* Enable MIB counters */
+ ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
+ AR8236_MIB_EN);
+
+ /* setup Service TAG */
+ ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
+}
+
+static void
+ar8229_init_port(struct ar8xxx_priv *priv, int port)
+{
+ __ar8216_init_port(priv, port, true, true);
+}
+
+
+static int
+ar7240sw_hw_init(struct ar8xxx_priv *priv)
+{
+ if (priv->initialized)
+ return 0;
+
+ ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
+ ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
+
+ priv->port4_phy = 1;
+ /* disable port5 to prevent mii conflict */
+ ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
+
+ ar8xxx_phy_init(priv);
+
+ priv->initialized = true;
+ return 0;
+}
+
+static void
+ar7240sw_init_globals(struct ar8xxx_priv *priv)
+{
+
+ /* Enable CPU port, and disable mirror port */
+ ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
+ AR8216_GLOBAL_CPUPORT_EN |
+ (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
+
+ /* Setup TAG priority mapping */
+ ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
+
+ /* Enable ARP frame acknowledge, aging, MAC replacing */
+ ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
+ AR8216_ATU_CTRL_RESERVED |
+ 0x2b /* 5 min age time */ |
+ AR8216_ATU_CTRL_AGE_EN |
+ AR8216_ATU_CTRL_ARP_EN |
+ AR8216_ATU_CTRL_LEARN_CHANGE);
+
+ /* Enable Broadcast frames transmitted to the CPU */
+ ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
+ AR8236_FM_CPU_BROADCAST_EN);
+
+ /* setup MTU */
+ ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ AR8216_GCTRL_MTU,
+ AR8216_GCTRL_MTU);
+
+ /* setup Service TAG */
+ ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
+}
+
+static void
+ar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
+{
+ return __ar8216_setup_port(priv, port, members, false);
+}
+
static void
ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
{
{
struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
- if (val->port_vlan >= AR8X16_MAX_PORTS)
+ if (val->port_vlan >= AR8X16_MAX_VLANS)
return -EINVAL;
priv->vlan_id[val->port_vlan] = val->value.i;
priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
chip->init_globals(priv);
+ chip->atu_flush(priv);
mutex_unlock(&priv->reg_mutex);
*/
for (j = 0; j < i; ++j) {
a1 = &priv->arl_table[j];
- if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
- goto duplicate;
+ if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
+ /* ignore ports already seen in former entry */
+ a->portmap &= ~a1->portmap;
+ if (!a->portmap)
+ goto duplicate;
+ }
}
}
for (j = 0; j < priv->dev.ports; ++j) {
for (k = 0; k < i; ++k) {
a = &priv->arl_table[k];
- if (a->port != j)
+ if (!(a->portmap & BIT(j)))
continue;
len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
"Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
return ret;
}
+int
+ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
+ struct switch_port_stats *stats)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ u64 *mib_stats;
+
+ if (!ar8xxx_has_mib_counters(priv))
+ return -EOPNOTSUPP;
+
+ if (!(priv->chip->mib_rxb_id || priv->chip->mib_txb_id))
+ return -EOPNOTSUPP;
+
+ if (port >= dev->ports)
+ return -EINVAL;
+
+ mutex_lock(&priv->mib_lock);
+
+ mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
+
+ stats->tx_bytes = mib_stats[priv->chip->mib_txb_id];
+ stats->rx_bytes = mib_stats[priv->chip->mib_rxb_id];
+
+ mutex_unlock(&priv->mib_lock);
+ return 0;
+}
+
+static int
+ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
+{
+ struct ar8xxx_priv *priv = bus->priv;
+ return priv->chip->phy_read(priv, phy_addr, reg_addr);
+}
+
+static int
+ar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,
+ u16 reg_val)
+{
+ struct ar8xxx_priv *priv = bus->priv;
+ return priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val);
+}
+
static const struct switch_attr ar8xxx_sw_attr_globals[] = {
{
.type = SWITCH_TYPE_INT,
.apply_config = ar8xxx_sw_hw_apply,
.reset_switch = ar8xxx_sw_reset_switch,
.get_port_link = ar8xxx_sw_get_port_link,
+ .get_port_stats = ar8xxx_sw_get_port_stats,
+};
+
+static const struct ar8xxx_chip ar7240sw_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x20000,
+ .reg_port_stats_length = 0x100,
+ .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
+
+ .name = "Atheros AR724X/AR933X built-in",
+ .ports = AR7240SW_NUM_PORTS,
+ .vlans = AR8216_NUM_VLANS,
+ .swops = &ar8xxx_sw_ops,
+
+ .hw_init = ar7240sw_hw_init,
+ .init_globals = ar7240sw_init_globals,
+ .init_port = ar8229_init_port,
+ .phy_read = ar8216_phy_read,
+ .phy_write = ar8216_phy_write,
+ .setup_port = ar7240sw_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .atu_flush_port = ar8216_atu_flush_port,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
+ .get_arl_entry = ar8216_get_arl_entry,
+ .sw_hw_apply = ar8xxx_sw_hw_apply,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8236_MIB_RXB_ID,
+ .mib_txb_id = AR8236_MIB_TXB_ID,
};
static const struct ar8xxx_chip ar8216_chip = {
.num_mibs = ARRAY_SIZE(ar8216_mibs),
.mib_decs = ar8216_mibs,
- .mib_func = AR8216_REG_MIB_FUNC
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8216_MIB_RXB_ID,
+ .mib_txb_id = AR8216_MIB_TXB_ID,
+};
+
+static const struct ar8xxx_chip ar8229_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x20000,
+ .reg_port_stats_length = 0x100,
+ .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
+
+ .name = "Atheros AR8229",
+ .ports = AR8216_NUM_PORTS,
+ .vlans = AR8216_NUM_VLANS,
+ .swops = &ar8xxx_sw_ops,
+
+ .hw_init = ar8229_hw_init,
+ .init_globals = ar8229_init_globals,
+ .init_port = ar8229_init_port,
+ .phy_read = ar8216_phy_read,
+ .phy_write = ar8216_phy_write,
+ .setup_port = ar8236_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .atu_flush_port = ar8216_atu_flush_port,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
+ .get_arl_entry = ar8216_get_arl_entry,
+ .sw_hw_apply = ar8xxx_sw_hw_apply,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8236_MIB_RXB_ID,
+ .mib_txb_id = AR8236_MIB_TXB_ID,
};
static const struct ar8xxx_chip ar8236_chip = {
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,
- .mib_func = AR8216_REG_MIB_FUNC
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8236_MIB_RXB_ID,
+ .mib_txb_id = AR8236_MIB_TXB_ID,
};
static const struct ar8xxx_chip ar8316_chip = {
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,
- .mib_func = AR8216_REG_MIB_FUNC
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8236_MIB_RXB_ID,
+ .mib_txb_id = AR8236_MIB_TXB_ID,
};
static int
-ar8xxx_id_chip(struct ar8xxx_priv *priv)
+ar8xxx_read_id(struct ar8xxx_priv *priv)
{
u32 val;
u16 id;
priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
priv->chip_rev = (id & AR8216_CTRL_REVISION);
+ return 0;
+}
+
+static int
+ar8xxx_id_chip(struct ar8xxx_priv *priv)
+{
+ int ret;
+
+ ret = ar8xxx_read_id(priv);
+ if(ret)
+ return ret;
switch (priv->chip_ver) {
case AR8XXX_VER_AR8216:
ar8xxx_mib_work_func(struct work_struct *work)
{
struct ar8xxx_priv *priv;
- int err;
+ int err, i;
priv = container_of(work, struct ar8xxx_priv, mib_work.work);
err = ar8xxx_mib_capture(priv);
if (err)
- goto next_port;
-
- ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
+ goto next_attempt;
-next_port:
- priv->mib_next_port++;
- if (priv->mib_next_port >= priv->dev.ports)
- priv->mib_next_port = 0;
+ for (i = 0; i < priv->dev.ports; i++)
+ ar8xxx_mib_fetch_port_stat(priv, i, false);
+next_attempt:
mutex_unlock(&priv->mib_lock);
schedule_delayed_work(&priv->mib_work,
- msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
+ msecs_to_jiffies(priv->mib_poll_interval));
}
static int
return;
schedule_delayed_work(&priv->mib_work,
- msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
+ msecs_to_jiffies(priv->mib_poll_interval));
}
static void
struct switch_dev *swdev;
int ret;
- ret = ar8xxx_id_chip(priv);
- if (ret)
- return ret;
-
chip = priv->chip;
swdev = &priv->dev;
priv->phy = phydev;
- if (phydev->addr != 0) {
+ if (phydev->mdio.addr != 0) {
if (chip_is_ar8316(priv)) {
/* switch device has been initialized, reinit */
priv->dev.ports = (AR8216_NUM_PORTS - 1);
/* flush ARL entries for this port if it went down*/
if (!link_new)
priv->chip->atu_flush_port(priv, i);
- dev_info(&priv->phy->dev, "Port %d is %s\n",
+ dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
i, link_new ? "up" : "down");
}
if (phydev->state == PHY_CHANGELINK)
ar8xxx_check_link_states(priv);
- if (phydev->addr != 0)
+ if (phydev->mdio.addr != 0)
return genphy_read_status(phydev);
- ar8216_read_port_link(priv, phydev->addr, &link);
+ ar8216_read_port_link(priv, phydev->mdio.addr, &link);
phydev->link = !!link.link;
if (!phydev->link)
return 0;
phydev->state = PHY_RUNNING;
netif_carrier_on(phydev->attached_dev);
- phydev->adjust_link(phydev->attached_dev);
+ if (phydev->adjust_link)
+ phydev->adjust_link(phydev->attached_dev);
return 0;
}
static int
ar8xxx_phy_config_aneg(struct phy_device *phydev)
{
- if (phydev->addr == 0)
+ if (phydev->mdio.addr == 0)
return 0;
return genphy_config_aneg(phydev);
int ret;
/* skip PHYs at unused adresses */
- if (phydev->addr != 0 && phydev->addr != 4)
+ if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
return -ENODEV;
- if (!ar8xxx_is_possible(phydev->bus))
+ if (!ar8xxx_is_possible(phydev->mdio.bus))
return -ENODEV;
mutex_lock(&ar8xxx_dev_list_lock);
list_for_each_entry(priv, &ar8xxx_dev_list, list)
- if (priv->mii_bus == phydev->bus)
+ if (priv->mii_bus == phydev->mdio.bus)
goto found;
priv = ar8xxx_create();
goto unlock;
}
- priv->mii_bus = phydev->bus;
+ priv->mii_bus = phydev->mdio.bus;
+ priv->pdev = &phydev->mdio.dev;
+
+ ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
+ &priv->mib_poll_interval);
+ if (ret)
+ priv->mib_poll_interval = AR8XXX_MIB_WORK_DELAY;
+
+ ret = ar8xxx_id_chip(priv);
+ if (ret)
+ goto free_priv;
ret = ar8xxx_probe_switch(priv);
if (ret)
found:
priv->use_count++;
- if (phydev->addr == 0) {
+ if (phydev->mdio.addr == 0) {
if (ar8xxx_has_gige(priv)) {
phydev->supported = SUPPORTED_1000baseT_Full;
phydev->advertising = ADVERTISED_1000baseT_Full;
phydev->supported |= SUPPORTED_1000baseT_Full;
phydev->advertising |= ADVERTISED_1000baseT_Full;
}
+ if (priv->chip->phy_rgmii_set)
+ priv->chip->phy_rgmii_set(priv, phydev);
}
phydev->priv = priv;
ar8xxx_free(priv);
}
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
static int
ar8xxx_phy_soft_reset(struct phy_device *phydev)
{
/* we don't need an extra reset */
return 0;
}
-#endif
-
-static struct phy_driver ar8xxx_phy_driver = {
- .phy_id = 0x004d0000,
- .name = "Atheros AR8216/AR8236/AR8316",
- .phy_id_mask = 0xffff0000,
- .features = PHY_BASIC_FEATURES,
- .probe = ar8xxx_phy_probe,
- .remove = ar8xxx_phy_remove,
- .detach = ar8xxx_phy_detach,
- .config_init = ar8xxx_phy_config_init,
- .config_aneg = ar8xxx_phy_config_aneg,
- .read_status = ar8xxx_phy_read_status,
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
- .soft_reset = ar8xxx_phy_soft_reset,
-#endif
- .driver = { .owner = THIS_MODULE },
+
+static struct phy_driver ar8xxx_phy_driver[] = {
+ {
+ .phy_id = 0x004d0000,
+ .name = "Atheros AR8216/AR8236/AR8316",
+ .phy_id_mask = 0xffff0000,
+ .features = PHY_BASIC_FEATURES,
+ .probe = ar8xxx_phy_probe,
+ .remove = ar8xxx_phy_remove,
+ .detach = ar8xxx_phy_detach,
+ .config_init = ar8xxx_phy_config_init,
+ .config_aneg = ar8xxx_phy_config_aneg,
+ .read_status = ar8xxx_phy_read_status,
+ .soft_reset = ar8xxx_phy_soft_reset,
+ }
+};
+
+static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
+ {
+ .compatible = "qca,ar7240sw",
+ .data = &ar7240sw_chip,
+ }, {
+ .compatible = "qca,ar8229",
+ .data = &ar8229_chip,
+ }, {
+ .compatible = "qca,ar8236",
+ .data = &ar8236_chip,
+ }, {
+ .compatible = "qca,ar8327",
+ .data = &ar8327_chip,
+ },
+ { /* sentinel */ },
};
-int __init
-ar8xxx_init(void)
+static int
+ar8xxx_mdiodev_probe(struct mdio_device *mdiodev)
{
- return phy_driver_register(&ar8xxx_phy_driver);
+ const struct of_device_id *match;
+ struct ar8xxx_priv *priv;
+ struct switch_dev *swdev;
+ struct device_node *mdio_node;
+ int ret;
+
+ match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);
+ if (!match)
+ return -EINVAL;
+
+ priv = ar8xxx_create();
+ if (priv == NULL)
+ return -ENOMEM;
+
+ priv->mii_bus = mdiodev->bus;
+ priv->pdev = &mdiodev->dev;
+ priv->chip = (const struct ar8xxx_chip *) match->data;
+
+ ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
+ &priv->mib_poll_interval);
+ if (ret)
+ priv->mib_poll_interval = AR8XXX_MIB_WORK_DELAY;
+
+ ret = ar8xxx_read_id(priv);
+ if (ret)
+ goto free_priv;
+
+ ret = ar8xxx_probe_switch(priv);
+ if (ret)
+ goto free_priv;
+
+ if (priv->chip->phy_read && priv->chip->phy_write) {
+ priv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);
+ priv->sw_mii_bus->name = "ar8xxx-mdio";
+ priv->sw_mii_bus->read = ar8xxx_phy_read;
+ priv->sw_mii_bus->write = ar8xxx_phy_write;
+ priv->sw_mii_bus->priv = priv;
+ priv->sw_mii_bus->parent = &mdiodev->dev;
+ snprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, "%s",
+ dev_name(&mdiodev->dev));
+ mdio_node = of_get_child_by_name(priv->pdev->of_node, "mdio-bus");
+ ret = of_mdiobus_register(priv->sw_mii_bus, mdio_node);
+ if (ret)
+ goto free_priv;
+ }
+
+ swdev = &priv->dev;
+ swdev->alias = dev_name(&mdiodev->dev);
+
+ if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) {
+ priv->port4_phy = true;
+ swdev->ports--;
+ }
+
+ ret = register_switch(swdev, NULL);
+ if (ret)
+ goto free_priv;
+
+ pr_info("%s: %s rev. %u switch registered on %s\n",
+ swdev->devname, swdev->name, priv->chip_rev,
+ dev_name(&priv->mii_bus->dev));
+
+ mutex_lock(&ar8xxx_dev_list_lock);
+ list_add(&priv->list, &ar8xxx_dev_list);
+ mutex_unlock(&ar8xxx_dev_list_lock);
+
+ priv->use_count++;
+
+ ret = ar8xxx_start(priv);
+ if (ret)
+ goto err_unregister_switch;
+
+ dev_set_drvdata(&mdiodev->dev, priv);
+
+ return 0;
+
+err_unregister_switch:
+ if (--priv->use_count)
+ return ret;
+
+ unregister_switch(&priv->dev);
+
+free_priv:
+ ar8xxx_free(priv);
+ return ret;
+}
+
+static void
+ar8xxx_mdiodev_remove(struct mdio_device *mdiodev)
+{
+ struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);
+
+ if (WARN_ON(!priv))
+ return;
+
+ mutex_lock(&ar8xxx_dev_list_lock);
+
+ if (--priv->use_count > 0) {
+ mutex_unlock(&ar8xxx_dev_list_lock);
+ return;
+ }
+
+ list_del(&priv->list);
+ mutex_unlock(&ar8xxx_dev_list_lock);
+
+ unregister_switch(&priv->dev);
+ ar8xxx_mib_stop(priv);
+ if(priv->sw_mii_bus)
+ mdiobus_unregister(priv->sw_mii_bus);
+ ar8xxx_free(priv);
+}
+
+static struct mdio_driver ar8xxx_mdio_driver = {
+ .probe = ar8xxx_mdiodev_probe,
+ .remove = ar8xxx_mdiodev_remove,
+ .mdiodrv.driver = {
+ .name = "ar8xxx-switch",
+ .of_match_table = ar8xxx_mdiodev_of_match,
+ },
+};
+
+static int __init ar8216_init(void)
+{
+ int ret;
+
+ ret = phy_drivers_register(ar8xxx_phy_driver,
+ ARRAY_SIZE(ar8xxx_phy_driver),
+ THIS_MODULE);
+ if (ret)
+ return ret;
+
+ ret = mdio_driver_register(&ar8xxx_mdio_driver);
+ if (ret)
+ phy_drivers_unregister(ar8xxx_phy_driver,
+ ARRAY_SIZE(ar8xxx_phy_driver));
+
+ return ret;
}
+module_init(ar8216_init);
-void __exit
-ar8xxx_exit(void)
+static void __exit ar8216_exit(void)
{
- phy_driver_unregister(&ar8xxx_phy_driver);
+ mdio_driver_unregister(&ar8xxx_mdio_driver);
+ phy_drivers_unregister(ar8xxx_phy_driver,
+ ARRAY_SIZE(ar8xxx_phy_driver));
}
+module_exit(ar8216_exit);
-module_init(ar8xxx_init);
-module_exit(ar8xxx_exit);
MODULE_LICENSE("GPL");
projects / openwrt / openwrt.git / blobdiff