generic: ar8216: introduce qca,mib-poll-interval property

[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.h

diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h
index d9508b9ff83c4c3d75978ae86546705660661a7f..35274b480a3f59b534c80d0bc19dbb85714c3bf7 100644 (file)
--- a/target/linux/generic/files/drivers/net/phy/ar8216.h
+++ b/target/linux/generic/files/drivers/net/phy/ar8216.h
@@ -26,6 +26,7 @@
 #define AR8216_PORT_CPU        0
 #define AR8216_NUM_PORTS       6
 #define AR8216_NUM_VLANS       16
+#define AR7240SW_NUM_PORTS     5
 #define AR8316_NUM_VLANS       4096
 
 /* size of the vlan table */
@@ -52,6 +53,8 @@
 #define AR8216_REG_FLOOD_MASK          0x002C
 #define   AR8216_FM_UNI_DEST_PORTS     BITS(0, 6)
 #define   AR8216_FM_MULTI_DEST_PORTS   BITS(16, 6)
+#define   AR8229_FLOOD_MASK_MC_DP(_p)  BIT(16 + (_p))
+#define   AR8229_FLOOD_MASK_BC_DP(_p)  BIT(25 + (_p))
 #define   AR8236_FM_CPU_BROADCAST_EN   BIT(26)
 #define   AR8236_FM_CPU_BCAST_FWD_EN   BIT(25)
 
@@ -112,6 +115,7 @@
 
 #define AR8216_REG_ATU_FUNC2           0x0058
 #define   AR8216_ATU_PORTS             BITS(0, 6)
+#define   AR8216_ATU_PORTS_S           0
 #define   AR8216_ATU_PORT0             BIT(0)
 #define   AR8216_ATU_PORT1             BIT(1)
 #define   AR8216_ATU_PORT2             BIT(2)
@@ -126,6 +130,14 @@
 #define   AR8216_ATU_CTRL_AGE_TIME     BITS(0, 16)
 #define   AR8216_ATU_CTRL_AGE_TIME_S   0
 #define   AR8236_ATU_CTRL_RES          BIT(20)
+#define   AR8216_ATU_CTRL_LEARN_CHANGE BIT(18)
+#define   AR8216_ATU_CTRL_RESERVED     BIT(19)
+#define   AR8216_ATU_CTRL_ARP_EN       BIT(20)
+
+#define AR8216_REG_TAG_PRIORITY        0x0070
+
+#define AR8216_REG_SERVICE_TAG         0x0074
+#define  AR8216_SERVICE_TAG_M          BITS(0, 16)
 
 #define AR8216_REG_MIB_FUNC            0x0080
 #define   AR8216_MIB_TIMER             BITS(0, 16)
@@ -141,6 +153,16 @@
 #define AR8216_REG_GLOBAL_CPUPORT              0x0078
 #define   AR8216_GLOBAL_CPUPORT_MIRROR_PORT    BITS(4, 4)
 #define   AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S  4
+#define   AR8216_GLOBAL_CPUPORT_EN             BIT(8)
+
+#define AR8216_REG_MDIO_CTRL           0x98
+#define   AR8216_MDIO_CTRL_DATA_M      BITS(0, 16)
+#define   AR8216_MDIO_CTRL_REG_ADDR_S  16
+#define   AR8216_MDIO_CTRL_PHY_ADDR_S  21
+#define   AR8216_MDIO_CTRL_CMD_WRITE   0
+#define   AR8216_MDIO_CTRL_CMD_READ    BIT(27)
+#define   AR8216_MDIO_CTRL_MASTER_EN   BIT(30)
+#define   AR8216_MDIO_CTRL_BUSY        BIT(31)
 
 #define AR8216_PORT_OFFSET(_i)         (0x0100 * (_i + 1))
 #define AR8216_REG_PORT_STATUS(_i)     (AR8216_PORT_OFFSET(_i) + 0x0000)
@@ -236,6 +258,19 @@
 #define AR8216_STATS_TXDEFER           0x98
 #define AR8216_STATS_TXLATECOL         0x9c
 
+#define AR8216_MIB_RXB_ID              14      /* RxGoodByte */
+#define AR8216_MIB_TXB_ID              29      /* TxByte */
+
+#define AR8229_REG_OPER_MODE0          0x04
+#define   AR8229_OPER_MODE0_MAC_GMII_EN        BIT(6)
+#define   AR8229_OPER_MODE0_PHY_MII_EN BIT(10)
+
+#define AR8229_REG_OPER_MODE1          0x08
+#define   AR8229_REG_OPER_MODE1_PHY4_MII_EN    BIT(28)
+
+#define AR8229_REG_QM_CTRL             0x3c
+#define   AR8229_QM_CTRL_ARP_EN                BIT(15)
+
 #define AR8236_REG_PORT_VLAN(_i)       (AR8216_PORT_OFFSET((_i)) + 0x0008)
 #define   AR8236_PORT_VLAN_DEFAULT_ID  BITS(16, 12)
 #define   AR8236_PORT_VLAN_DEFAULT_ID_S        16
@@ -289,6 +324,9 @@
 #define AR8236_STATS_TXDEFER           0xa0
 #define AR8236_STATS_TXLATECOL         0xa4
 
+#define AR8236_MIB_RXB_ID              15      /* RxGoodByte */
+#define AR8236_MIB_TXB_ID              31      /* TxByte */
+
 #define AR8316_REG_POSTRIP                     0x0008
 #define   AR8316_POSTRIP_MAC0_GMII_EN          BIT(0)
 #define   AR8316_POSTRIP_MAC0_RGMII_EN         BIT(1)
@@ -367,7 +405,7 @@ enum arl_op {
 };
 
 struct arl_entry {
-       u8 port;
+       u16 portmap;
        u8 mac[6];
 };
 
@@ -412,16 +450,23 @@ struct ar8xxx_chip {
        void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
                              u32 *status, enum arl_op op);
        int (*sw_hw_apply)(struct switch_dev *dev);
+       void (*phy_rgmii_set)(struct ar8xxx_priv *priv, struct phy_device *phydev);
+       int (*phy_read)(struct ar8xxx_priv *priv, int addr, int regnum);
+       int (*phy_write)(struct ar8xxx_priv *priv, int addr, int regnum, u16 val);
 
        const struct ar8xxx_mib_desc *mib_decs;
        unsigned num_mibs;
        unsigned mib_func;
+       int mib_rxb_id;
+       int mib_txb_id;
 };
 
 struct ar8xxx_priv {
        struct switch_dev dev;
        struct mii_bus *mii_bus;
+       struct mii_bus *sw_mii_bus;
        struct phy_device *phy;
+       struct device *pdev;
 
        int (*get_port_link)(unsigned port);
 
@@ -443,8 +488,8 @@ struct ar8xxx_priv {
 
        struct mutex mib_lock;
        struct delayed_work mib_work;
-       int mib_next_port;
        u64 *mib_stats;
+       u32 mib_poll_interval;
 
        struct list_head list;
        unsigned int use_count;
@@ -462,6 +507,7 @@ struct ar8xxx_priv {
        bool mirror_tx;
        int source_port;
        int monitor_port;
+       u8 port_vlan_prio[AR8X16_MAX_PORTS];
 };
 
 u32
@@ -475,6 +521,9 @@ ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
 u32
 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 
+void
+ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
+               u16 dbg_addr, u16 *dbg_data);
 void
 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
                     u16 dbg_addr, u16 dbg_data);
@@ -566,6 +615,9 @@ ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
                                   const struct switch_attr *attr,
                                   struct switch_val *val);
 int
+ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
+                       struct switch_port_stats *stats);
+int
 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 
 static inline struct ar8xxx_priv *