* Marvell 88E61xx switch driver
*
* Copyright (c) 2014 Claudio Leite <leitec@staticky.com>
+ * Copyright (c) 2014 Nikita Nazarenko <nnazarenko@radiofid.com>
*
- * Based on code (c) 2008 Felix Fietkau <nbd@openwrt.org>
+ * Based on code (c) 2008 Felix Fietkau <nbd@nbd.name>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License v2 as published by the
#define MV_PORTS 7
#define MV_PORTS_MASK ((1 << MV_PORTS) - 1)
-#define MV_CPUPORT 6
-
#define MV_BASE 0x10
#define MV_SWITCHPORT_BASE 0x10
enum {
MV_PORT_STATUS = 0x00,
- MV_PORT_FORCE = 0x01,
- MV_PORT_PAUSE = 0x02,
+ MV_PORT_PHYCTL = 0x01,
+ MV_PORT_JAMCTL = 0x02,
MV_PORT_IDENT = 0x03,
MV_PORT_CONTROL = 0x04,
MV_PORT_CONTROL1 = 0x05,
MV_PORT_VLANID = 0x07,
MV_PORT_CONTROL2 = 0x08,
MV_PORT_ASSOC = 0x0b,
- MV_PORT_RXCOUNT = 0x10,
- MV_PORT_TXCOUNT = 0x11,
+ MV_PORT_RX_DISCARD_LOW = 0x10,
+ MV_PORT_RX_DISCARD_HIGH = 0x11,
+ MV_PORT_IN_FILTERED = 0x12,
+ MV_PORT_OUT_ACCEPTED = 0x13,
};
#define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type
MV_PORT_STATUS_LINK = (1 << 11),
};
+enum {
+ MV_PORT_STATUS_CMODE_100BASE_X = 0x8,
+ MV_PORT_STATUS_CMODE_1000BASE_X = 0x9,
+ MV_PORT_STATUS_CMODE_SGMII = 0xa,
+};
+
+#define MV_PORT_STATUS_CMODE_MASK 0xf
+
enum {
MV_PORT_STATUS_SPEED_10 = 0x00,
MV_PORT_STATUS_SPEED_100 = 0x01,
#define MV_PORT_STATUS_SPEED_MASK (3 << 8)
enum {
- MV_PORTCTRL_BLOCK = (1 << 0),
- MV_PORTCTRL_LEARN = (2 << 0),
- MV_PORTCTRL_ENABLED = (3 << 0),
+ MV_PORTCTRL_DISABLED = (0 << 0),
+ MV_PORTCTRL_BLOCKING = (1 << 0),
+ MV_PORTCTRL_LEARNING = (2 << 0),
+ MV_PORTCTRL_FORWARDING = (3 << 0),
MV_PORTCTRL_VLANTUN = (1 << 7),
MV_PORTCTRL_EGRESS = (1 << 12),
};
-#define MV_FORCE_FC_MASK (3 << 6)
+#define MV_PHYCTL_FC_MASK (3 << 6)
enum {
- MV_FORCE_FC_ENABLE = (3 << 6),
- MV_FORCE_FC_DISABLE = (1 << 6),
+ MV_PHYCTL_FC_ENABLE = (3 << 6),
+ MV_PHYCTL_FC_DISABLE = (1 << 6),
};
enum {
MV_8021Q_MODE_SECURE = 0x03,
};
+enum {
+ MV_8021Q_VLAN_ONLY = (1 << 15),
+};
+
#define MV_PORTASSOC_MONITOR (1 << 15)
enum {
- MV_SWITCH_MAC0 = 0x01,
- MV_SWITCH_MAC1 = 0x02,
- MV_SWITCH_MAC2 = 0x03,
+ MV_SWITCH_ATU_FID0 = 0x01,
+ MV_SWITCH_ATU_FID1 = 0x02,
+ MV_SWITCH_ATU_SID = 0x03,
MV_SWITCH_CTRL = 0x04,
MV_SWITCH_ATU_CTRL = 0x0a,
MV_SWITCH_ATU_OP = 0x0b,
enum {
MV_GLOBAL_STATUS = 0x00,
+ MV_GLOBAL_ATU_FID = 0x01,
+ MV_GLOBAL_VTU_FID = 0x02,
+ MV_GLOBAL_VTU_SID = 0x03,
MV_GLOBAL_CONTROL = 0x04,
MV_GLOBAL_VTU_OP = 0x05,
MV_GLOBAL_VTU_VID = 0x06,
MV_GLOBAL_VTU_DATA1 = 0x07,
MV_GLOBAL_VTU_DATA2 = 0x08,
MV_GLOBAL_VTU_DATA3 = 0x09,
+ MV_GLOBAL_CONTROL2 = 0x1c,
};
#define MV_GLOBALREG(_type) MV_SWITCH_GLOBAL, MV_GLOBAL_##_type
enum {
- MV_GLOBAL2_SDET_POLARITY = 0x1D,
+ MV_GLOBAL2_SMI_OP = 0x18,
+ MV_GLOBAL2_SMI_DATA = 0x19,
+ MV_GLOBAL2_SDET_POLARITY = 0x1d,
};
#define MV_GLOBAL2REG(_type) MV_SWITCH_GLOBAL2, MV_GLOBAL2_##_type
enum {
- MV_VTUOP_VALID = (1 << 12),
+ MV_VTU_VID_VALID = (1 << 12),
+};
+
+enum {
+ MV_VTUOP_PURGE = (1 << 12),
MV_VTUOP_LOAD = (3 << 12),
MV_VTUOP_INPROGRESS = (1 << 15),
+ MV_VTUOP_STULOAD = (5 << 12),
+ MV_VTUOP_VTU_GET_NEXT = (4 << 12),
+ MV_VTUOP_STU_GET_NEXT = (6 << 12),
+ MV_VTUOP_GET_VIOLATION = (7 << 12),
};
enum {
};
enum {
- MV_VTUCTL_EGRESS_UNMODIFIED = 0x00,
- MV_VTUCTL_EGRESS_UNTAGGED = 0x01,
- MV_VTUCTL_EGRESS_TAGGED = 0x02,
- MV_VTUCTL_DISCARD = 0x03,
+ MV_VTUCTL_EGRESS_UNMODIFIED = (0 << 0),
+ MV_VTUCTL_EGRESS_UNTAGGED = (1 << 0),
+ MV_VTUCTL_EGRESS_TAGGED = (2 << 0),
+ MV_VTUCTL_DISCARD = (3 << 0),
};
enum {
- MV_8021Q_VLAN_ONLY = (1 << 15),
+ MV_STUCTL_STATE_DISABLED = (0 << 0),
+ MV_STUCTL_STATE_BLOCKING = (1 << 0),
+ MV_STUCTL_STATE_LEARNING = (2 << 0),
+ MV_STUCTL_STATE_FORWARDING = (3 << 0),
};
enum {
#define MV_IDENT_VALUE_6176 0x1760
#define MV_IDENT_STR_6176 "MV88E6176"
+#define MV_IDENT_VALUE_6352 0x3520
+#define MV_IDENT_STR_6352 "MV88E6352"
+
#define MV_PVID_MASK 0x0fff
+#define MV_FDB_HI_MASK 0x00ff
+#define MV_FDB_LO_MASK 0xf000
+#define MV_FDB_HI_SHIFT 4
+#define MV_FDB_LO_SHIFT 12
+
+/* Marvell Specific PHY register */
+#define MII_MV_SPEC_CTRL 16
+enum {
+ MV_SPEC_MDI_CROSS_AUTO = (0x6 << 4),
+ MV_SPEC_ENERGY_DETECT = (0x3 << 8),
+ MV_SPEC_DOWNSHIFT_COUNTER = (0x3 << 12),
+};
+
+#define MII_MV_PAGE 22
+
+#define MV_REG_FIBER_SERDES 0xf
+#define MV_PAGE_FIBER_SERDES 0x1
+
struct mvsw61xx_state {
struct switch_dev dev;
struct mii_bus *bus;
int vlan_enabled;
struct port_state {
+ u16 fdb;
u16 pvid;
u16 mask;
u8 qmode;
u16 mask;
u16 vid;
u32 port_mode;
+ u32 port_sstate;
} vlans[MV_VLANS];
char buf[128];
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