-From b31046c51c72232363711f0c623df08bf28c37e4 Mon Sep 17 00:00:00 2001
+From 4215d5757595e7ec7ca146c2b901beb177f415d8 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Mon, 25 Sep 2017 12:21:30 +0800
-Subject: [PATCH] mmc: layerscape support
+Date: Wed, 17 Jan 2018 15:37:13 +0800
+Subject: [PATCH 24/30] mmc: layerscape support
-This is a integrated patch for layerscape mmc support.
+This is an integrated patch for layerscape mmc support.
Adrian Hunter <adrian.hunter@intel.com>
Jaehoon Chung <jh80.chung@samsung.com>
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-esdhc.h | 52 +++++---
- drivers/mmc/host/sdhci-of-esdhc.c | 251 ++++++++++++++++++++++++++++++++++++--
+ drivers/mmc/host/sdhci-of-esdhc.c | 265 ++++++++++++++++++++++++++++++++++++--
drivers/mmc/host/sdhci.c | 45 ++++---
drivers/mmc/host/sdhci.h | 3 +
- 5 files changed, 306 insertions(+), 46 deletions(-)
+ 5 files changed, 320 insertions(+), 46 deletions(-)
-diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
-index 5274f503..a1135a92 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -144,6 +144,7 @@ config MMC_SDHCI_OF_ESDHC
help
This selects the Freescale eSDHC controller support.
-diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h
-index de132e28..98898a30 100644
--- a/drivers/mmc/host/sdhci-esdhc.h
+++ b/drivers/mmc/host/sdhci-esdhc.h
@@ -24,30 +24,46 @@
-#define ESDHC_CTRL_4BITBUS (0x1 << 1)
-#define ESDHC_CTRL_8BITBUS (0x2 << 1)
-#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
-
+-
-/* OF-specific */
-#define ESDHC_DMA_SYSCTL 0x40c
-#define ESDHC_DMA_SNOOP 0x00000040
+
+-#define ESDHC_HOST_CONTROL_RES 0x01
+/* Present State Register */
+#define ESDHC_PRSSTAT 0x24
+#define ESDHC_CLOCK_STABLE 0x00000008
+/* Tuning Block Control Register */
+#define ESDHC_TBCTL 0x120
+#define ESDHC_TB_EN 0x00000004
-
--#define ESDHC_HOST_CONTROL_RES 0x01
++
+/* Control Register for DMA transfer */
+#define ESDHC_DMA_SYSCTL 0x40c
+#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
+#define ESDHC_DMA_SNOOP 0x00000040
#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
-diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
-index 3c27401c..4b0f375b 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -16,8 +16,12 @@
/**
* esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
* to make it compatible with SD spec.
-@@ -80,6 +88,17 @@ static u32 esdhc_readl_fixup(struct sdhci_host *host,
+@@ -80,6 +88,17 @@ static u32 esdhc_readl_fixup(struct sdhc
return ret;
}
ret = value;
return ret;
}
-@@ -87,6 +106,8 @@ static u32 esdhc_readl_fixup(struct sdhci_host *host,
+@@ -87,6 +106,8 @@ static u32 esdhc_readl_fixup(struct sdhc
static u16 esdhc_readw_fixup(struct sdhci_host *host,
int spec_reg, u32 value)
{
u16 ret;
int shift = (spec_reg & 0x2) * 8;
-@@ -94,6 +115,12 @@ static u16 esdhc_readw_fixup(struct sdhci_host *host,
+@@ -94,6 +115,12 @@ static u16 esdhc_readw_fixup(struct sdhc
ret = value & 0xffff;
else
ret = (value >> shift) & 0xffff;
return ret;
}
-@@ -235,7 +262,11 @@ static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
+@@ -235,7 +262,11 @@ static u32 esdhc_be_readl(struct sdhci_h
u32 ret;
u32 value;
ret = esdhc_readl_fixup(host, reg, value);
return ret;
-@@ -246,7 +277,11 @@ static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
+@@ -246,7 +277,11 @@ static u32 esdhc_le_readl(struct sdhci_h
u32 ret;
u32 value;
ret = esdhc_readl_fixup(host, reg, value);
return ret;
-@@ -404,15 +439,25 @@ static int esdhc_of_enable_dma(struct sdhci_host *host)
+@@ -404,15 +439,25 @@ static int esdhc_of_enable_dma(struct sd
static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
}
static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
-@@ -421,17 +466,34 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
+@@ -421,12 +466,15 @@ static void esdhc_of_set_clock(struct sd
struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
int pre_div = 1;
int div = 1;
/* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
if (esdhc->vendor_ver < VENDOR_V_23)
- pre_div = 2;
-
-+ /*
-+ * Limit SD clock to 167MHz for ls1046a according to its datasheet
-+ */
-+ if (clock > 167000000 &&
-+ of_find_compatible_node(NULL, NULL, "fsl,ls1046a-esdhc"))
-+ clock = 167000000;
-+
-+ /*
-+ * Limit SD clock to 125MHz for ls1012a according to its datasheet
-+ */
-+ if (clock > 125000000 &&
-+ of_find_compatible_node(NULL, NULL, "fsl,ls1012a-esdhc"))
-+ clock = 125000000;
-+
- /* Workaround to reduce the clock frequency for p1010 esdhc */
- if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
- if (clock > 20000000)
-@@ -441,8 +503,8 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
+@@ -454,9 +502,15 @@ static void esdhc_of_set_clock(struct sd
+ clock -= 5000000;
}
++ /* Workaround to reduce the clock frequency for ls1021a esdhc */
++ if (of_find_compatible_node(NULL, NULL, "fsl,ls1021a-esdhc")) {
++ if (clock == 50000000)
++ clock = 46500000;
++ }
++
temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
- temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
- | ESDHC_CLOCK_MASK);
sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
-@@ -462,7 +524,20 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
+@@ -476,7 +530,20 @@ static void esdhc_of_set_clock(struct sd
| (div << ESDHC_DIVIDER_SHIFT)
| (pre_div << ESDHC_PREDIV_SHIFT));
sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
}
static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
-@@ -487,6 +562,33 @@ static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
+@@ -501,12 +568,136 @@ static void esdhc_pltfm_set_bus_width(st
sdhci_writel(host, ctrl, ESDHC_PROCTL);
}
+
static void esdhc_reset(struct sdhci_host *host, u8 mask)
{
++ u32 val;
++
sdhci_reset(host, mask);
-@@ -495,6 +597,95 @@ static void esdhc_reset(struct sdhci_host *host, u8 mask)
- sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
- }
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
++
++ if (mask & SDHCI_RESET_ALL) {
++ val = sdhci_readl(host, ESDHC_TBCTL);
++ val &= ~ESDHC_TB_EN;
++ sdhci_writel(host, val, ESDHC_TBCTL);
++ }
++}
++
+/* The SCFG, Supplemental Configuration Unit, provides SoC specific
+ * configuration and status registers for the device. There is a
+ * SDHC IO VSEL control register on SCFG for some platforms. It's
+ esdhc_clock_enable(host, true);
+
+ return sdhci_execute_tuning(mmc, opcode);
-+}
-+
+ }
+
#ifdef CONFIG_PM_SLEEP
- static u32 esdhc_proctl;
- static int esdhc_of_suspend(struct device *dev)
-@@ -575,10 +766,19 @@ static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
+@@ -589,10 +780,19 @@ static const struct sdhci_pltfm_data sdh
.ops = &sdhci_esdhc_le_ops,
};
u16 host_ver;
pltfm_host = sdhci_priv(host);
-@@ -588,6 +788,36 @@ static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
+@@ -602,6 +802,36 @@ static void esdhc_init(struct platform_d
esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
SDHCI_VENDOR_VER_SHIFT;
esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
}
static int sdhci_esdhc_probe(struct platform_device *pdev)
-@@ -610,6 +840,11 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
+@@ -624,6 +854,11 @@ static int sdhci_esdhc_probe(struct plat
if (IS_ERR(host))
return PTR_ERR(host);
esdhc_init(pdev, host);
sdhci_get_of_property(pdev);
-diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
-index 7d275e72..099c3bf5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
-@@ -1624,26 +1624,24 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+@@ -1624,26 +1624,24 @@ static void sdhci_set_ios(struct mmc_hos
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (!host->preset_enabled) {
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
/*
-@@ -1956,7 +1954,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
+@@ -1956,7 +1954,7 @@ static int sdhci_prepare_hs400_tuning(st
return 0;
}
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
-@@ -2015,6 +2013,9 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+@@ -2015,6 +2013,9 @@ static int sdhci_execute_tuning(struct m
return err;
}
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl |= SDHCI_CTRL_EXEC_TUNING;
if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
-@@ -2127,9 +2128,10 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+@@ -2127,9 +2128,10 @@ static int sdhci_execute_tuning(struct m
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
/*
-@@ -2165,6 +2167,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+@@ -2165,6 +2167,7 @@ out_unlock:
spin_unlock_irqrestore(&host->lock, flags);
return err;
}
static int sdhci_select_drive_strength(struct mmc_card *card,
unsigned int max_dtr, int host_drv,
-@@ -2997,6 +3000,8 @@ struct sdhci_host *sdhci_alloc_host(struct device *dev,
+@@ -2997,6 +3000,8 @@ struct sdhci_host *sdhci_alloc_host(stru
host->flags = SDHCI_SIGNALING_330;
return host;
}
-diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
-index 2570455b..088bed43 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -524,6 +524,8 @@ struct sdhci_host {
unsigned long private[0] ____cacheline_aligned;
};
-@@ -689,6 +691,7 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
+@@ -689,6 +691,7 @@ void sdhci_set_power_noreg(struct sdhci_
void sdhci_set_bus_width(struct sdhci_host *host, int width);
void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
---
-2.14.1
-
projects / openwrt / openwrt.git / blobdiff