ramips: Enable rx of 1536 bytes ethernet frames on MT7621

[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / gsw_mt7620a.c

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c
index 58c209857ee15d17fb40e0109155b8f8d026aba2..325e2433f10b62c0e1ed7617bd760287adb04a6d 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c
@@ -80,7 +80,6 @@
 
 #define SYSC_REG_CHIP_REV_ID   0x0c
 #define SYSC_REG_CFG1          0x14
-#define SYSC_REG_RESET_CTRL     0x34
 #define RST_CTRL_MCM           BIT(2)
 #define SYSC_PAD_RGMII2_MDIO   0x58
 #define SYSC_GPIO_MODE         0x60
@@ -576,10 +575,7 @@ static void gsw_hw_init_mt7621(struct mt7620_gsw *gsw, struct device_node *np)
        u32     val;
 
        /* Hardware reset Switch */
-       val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-       rt_sysc_w32(val | RST_CTRL_MCM, SYSC_REG_RESET_CTRL);
-        udelay(1000);
-       rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+       fe_reset(RST_CTRL_MCM);
         udelay(10000);
 
        /* reduce RGMII2 PAD driving strength */
@@ -596,7 +592,7 @@ static void gsw_hw_init_mt7621(struct mt7620_gsw *gsw, struct device_node *np)
 
        /* turn off all PHYs */
        for (i = 0; i <= 4; i++) {
-               _mt7620_mii_read(gsw, i, 0x0);
+               val = _mt7620_mii_read(gsw, i, 0x0);
                val |= (0x1 << 11);
                _mt7620_mii_write(gsw, i, 0x0, val);
        }
@@ -606,12 +602,12 @@ static void gsw_hw_init_mt7621(struct mt7620_gsw *gsw, struct device_node *np)
        udelay(10);
 
        if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
-               /* (GE1, Force 1000M/FD, FC ON) */
-               gsw_w32(gsw, 0x2005e30b, 0x100);
+               /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
+               gsw_w32(gsw, 0x2105e30b, 0x100);
                mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
        } else {
-               /* (GE1, Force 1000M/FD, FC ON) */
-               gsw_w32(gsw, 0x2005e33b, 0x100);
+               /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
+               gsw_w32(gsw, 0x2105e33b, 0x100);
                mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
        }